Report an Error

VIA Nano X2 U4300

2
Cores
2
Threads
13 W
TDP
1200 MHz
Frequency
1467 MHz
Boost
CNC
Codename
VIA nanoBGA2
Socket
Front
Front
Back
Back
VIA nanoBGA2
VIA nanoBGA2
The VIA Nano X2 U4300 was a mobile processor with 2 cores, launched in January 2011. It is part of the Nano X2 lineup, using the Isaiah (CNC) architecture with VIA nanoBGA2. Nano X2 U4300 has 1 MB of L2 cache per core and operates at 1200 MHz by default, but can boost up to 1467 MHz, depending on the workload. VIA is making the Nano X2 U4300 on a 40 nm production node using 188 million transistors. The silicon die of the chip is not fabricated at VIA, but at the foundry of TSMC. The multiplier is locked on Nano X2 U4300, which limits its overclocking potential.
With a TDP of 13 W, the Nano X2 U4300 consumes very little energy. VIA's processor supports DDR2 and DDR3 memory with a single-channel interface. The highest officially supported memory speed is 1333 MT/s, but with overclocking (and the right memory modules) you can go even higher.
Hardware virtualization is available on the Nano X2 U4300, which greatly improves virtual machine performance.

Physical

Socket: VIA nanoBGA2
Foundry: TSMC
Process Size: 40 nm
Transistors: 188 million
Die Size: 66 mm²
Package: FC-BGA400

Processor

Market: Mobile
Production Status: End-of-life
Release Date: Jan 2011
Part#: unknown

Performance

Frequency: 1200 MHz
Turbo Clock: up to 1467 MHz
Base Clock: 266 MHz
Multiplier: 4.5x
Multiplier Unlocked: No
Voltage: 0.9 V
TDP: 13 W
Idle Power:0.5 W

Architecture

Codename: CNC
Generation: Nano X2
(Isaiah (CNC))
Memory Support: DDR2, DDR3
Rated Speed: 1333 MT/s
Memory Bus: Single-channel
ECC Memory: No
Chipsets: VIA VX900, VIA VN1000, VIA VX11

Core Config

# of Cores: 2
# of Threads: 2
SMP # CPUs: 1
Integrated Graphics: On certain motherboards (Chipset feature)

Cache

Cache L1: 128 KB (per core)
Cache L2: 1 MB (per core)

Features

  • MMX
  • SSE
  • SSE2
  • SSE3
  • SSSE3
  • SSE4.1
  • AES
  • NX-bit
  • VT-x
  • SHA-1
  • SHA-256
  • x86-64
  • VIA Padlock
  • VIA Power Saver
  • Turbo

Notes

VIA V4 Bus is a quad-pumped front side bus architecture, therefore Base Clock*4 gives the advertised FSB.

DRAM, Graphics, I/O, and Audio handled by the VIA MSP chipset used.
Jan 23rd, 2025 00:04 EST change timezone

New Forum Posts

Popular Reviews

Controversial News Posts