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AMD Dragon Range

AMD's Dragon Range GPU uses the RDNA 2.0 architecture and is made using a 5 nm production process at TSMC. With a die size of 264 mm² it is a medium-sized chip. Dragon Range supports DirectX 12 Ultimate (Feature Level 12_2). For GPU compute applications, OpenCL version 2.1 can be used. Additionally, the DirectX 12 Ultimate capability guarantees support for hardware-raytracing, variable-rate shading and more, in upcoming video games. It features 128 shading units, 8 texture mapping units and 4 ROPs. The GPU also contains 2 raytracing acceleration cores.
Further reading: RDNA Whitepaper

Graphics Processor

Released
Jan 3rd, 2023
GPU Name
Dragon Range
Generation
Navi II
Architecture
RDNA 2.0
Foundry
TSMC
Process Size
5 nm
I/O Process
6 nm
Process Type
N5 / N6 FinFET
Transistors
unknown
Die Size
264 mm²
CCD Die Size
71 mm² x2
I/O Die Size
122 mm²
Package
FL1

Graphics Features

DirectX
12 Ultimate (12_2)
OpenGL
4.6
OpenCL
2.1
Vulkan
1.3
Shader Model
6.7
WDDM
3.1
GC
10.3.x
Shader ISA
GFX10.3 (gfx103X)
DCN
3.1.5
VCN
3.1.2
SDMA
5.2.6
MP0
13.0.5

Render Config

Shading Units
128
TMUs
8
ROPs
4
Compute Units
2
RT Cores
2
L0 Cache
32 KB per WGP
L1 Cache
128 KB per Array
L2 Cache
2048 KB
Max. TDP
15 W

All RDNA 2.0 GPUs

AMD GPU Architecture History

Graphics cards using the AMD Dragon Range GPU

Name Chip Memory Shaders TMUs ROPs Base Clock Boost Clock Memory Clock
AMD Radeon 610M
System Shared 128 8 4 400 MHz 2200 MHz System Shared

Dragon Range GPU Notes

Generation: Navi II
Ray Tracing Cores: 1st Gen
Graphics/Compute: 10.3.x
Shader ISA: GFX10.3 (gfx103X)
Display Core Next: 3.1.5
Video Core Next: 3.1.2
System DMA: 5.2.6
Platform Security Processor: 13.0.5

Per SIMD32:
- 10 KB Scalar Register File

Per CU:
- 16 KB Vector Data Cache
- 64 KB Local Data Share (GCN-Mode)

Per WGP:
- 16 KB Scalar Data Cache / K Cache
- 32 KB Instruction Cache
- 128 KB Local Data Share
May 18th, 2024 22:57 EDT change timezone

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