Latest AMD AGESA that Nerfs Ryzen 7000X3D Voltage Control Also Limits Memory Overclocking
The latest AMD AGESA 1.0.0.7 AM5 platform microcode that the company recently released to improve stability of machines powered by Ryzen 7000X3D processors, more importantly, prevent them from physical damage due to increased voltage in voltage-assisted overclocking scenarios; reportedly impacts memory overclocking capabilities, too, reports g01d3nm4ng0. The "PROCHOT Control" and "PROCHOT Deassertation Ramp" toggles that were available in the oldest versions of AGESA for AM5, are not available in the latest production AGESA.
The memory compatibility is also affected. AMD recently added support for odd-density DDR5 memory modules, such as 24 GB and 48 GB, which make up 48 GB and 96 GB 2-module (dual-channel, four sub-channel) kits. It is possible to max out 192 GB, but while the older AGESA 1.0.0.6 allowed memory frequencies of up to DDR5-6000 with SoC voltage of 1.3 V, the newer AGESA is only stable up to DDR5-4400 at this density. To be fair, most motherboards advertise maximum memory frequencies of under DDR5-4800 for memory configurations where there are two DIMMs per channel, and both DIMMs are dual-rank (so four dual-rank DIMMs in all, which is the least optimal memory configuration from a memory frequency and latency perspective).
The memory compatibility is also affected. AMD recently added support for odd-density DDR5 memory modules, such as 24 GB and 48 GB, which make up 48 GB and 96 GB 2-module (dual-channel, four sub-channel) kits. It is possible to max out 192 GB, but while the older AGESA 1.0.0.6 allowed memory frequencies of up to DDR5-6000 with SoC voltage of 1.3 V, the newer AGESA is only stable up to DDR5-4400 at this density. To be fair, most motherboards advertise maximum memory frequencies of under DDR5-4800 for memory configurations where there are two DIMMs per channel, and both DIMMs are dual-rank (so four dual-rank DIMMs in all, which is the least optimal memory configuration from a memory frequency and latency perspective).