Intel today launched its Xeon W-3500 series and Xeon W-2500 series workstation processors. These chips are based on the "Sapphire Rapids" microarchitecture featuring the enterprise version of "Golden Cove" P-cores. These are a refresh over the Xeon W-3400 series and W-2400 series, as they feature higher CPU core counts, L3 cache, and clock speeds, at given price-points. Intel has also slightly de-cluttered its lineup with this series. The key difference between the W-3500 series and the W-2500 series, is that the former comes with 8-channel DDR5 memory interface and 112 PCI-Express Gen 5 lanes; while the latter offers a 4-channel DDR5 memory interface, along with 64 PCI-Express Gen 5 lanes. The W-2500 series also comes with lower CPU core counts compared to the W-3500, which is somewhat made up for with higher CPU clock speeds. Perhaps the highlight of this refresh is that now Intel sells CPU core counts of up to 60-core/120-thread in the workstation segment. The W-3400 series had topped off at 36-core/72-thread.

The series is led by the Xeon W9-3595X. This beast maxes out the "Sapphire Rapids" chip, with a 60-core/120-thread configuration, with each of the 60 cores featuring 2 MB of dedicated L2 cache, and sharing 112.5 MB of L3 cache. The chip comes with a base frequency of 2.00 GHz, and a maximum boost frequency of 4.80 GHz. The next highest SKU sees a rather steep drop in core-counts, with the Xeon W9-3575X coming in with a 44-core/88-thread configuration, along with 97.5 MB of shared L3 cache, besides the 2 MB of dedicated L2 cache per core. This chip ticks at 2.20 GHz base, along with 4.80 GHz maximum boost. There's yet another steep drop in core-counts with the Xeon W7-3545, featuring a 24-core/48-thread configuration, 67.5 MB of shared L3 cache, 2.70 GHz base frequency, and 4.80 GHz maximum boost.

Today, the Open Compute Project Foundation (OCP), the nonprofit organization bringing hyperscale innovations to all, and JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announce a new collaboration to establish a framework for the transfer of technology captured in an OCP-approved specification to JEDEC for inclusion in one of its standards. This alliance brings together members from both the OCP and JEDEC communities to share efforts in developing and maintaining global standards needed to advance the electronics industry.

Under this new alliance, the current effort will be to provide a mechanism to standardize Chiplet part descriptions leveraging OCP Chiplet Data Extensible Markup Language (CDXML) specification to become part of JEDEC JEP30: Part Model Guidelines for use with today's EDA tools. With this updated JEDEC standard, expected to be published in 2023, Chiplet builders will be able to provide electronically a standardized Chiplet part description to their customers paving the way for automating System in Package (SiP) design and build using Chiplets. The description will include information needed by SiP builders such as Chiplet thermal properties, physical and mechanical requirements, behavior specifications, power and signal integrity properties, testing the Chiplet in package, and security parameters.

According to multiple reports and sources close to Tom's Hardware, Intel and Microsoft have quietly resumed operations and a basic level of support in Russia. As to comply with sanctions imposed by Europe, the UK, and US, Intel and Microsoft are forbidden to sell any new technology within the state of Russia. This has made Intel and Microsoft block official software downloads. However, Intel has stated that the company is obliged to provide warranty services that are a part of purchasing an Intel product. "Intel continues to comply with all applicable export regulations and sanctions in the countries in which it operates. This includes compliance with the sanctions and export controls against Russia and Belarus issued by the US and allied nations. Access to resources that meet driver update needs, such as the Intel Download Center and Intel Download Support Assistant (IDSA), are part of Intel's warranty obligations," said Intel, adding that "There have been no recent changes to our operations."

These changes are not exactly "recent," as reports close to Tom's Hardware have noted that downloads were resumed towards the end of 2022. Izvestia and CNews reported that users could access the Intel download portal without VPN and IP masking. This required finding a download section through Google/Yandex, as the official Intel Russia website is still not officially reachable by Russian IPs.

Intel in the second day of its InnovatiON event, turned attention to its next-generation Xeon Scalable "Sapphire Rapids" server processors, and demonstrated on-package accelerators. These are fixed-function hardware components that accelerate specific kinds of popular server workloads (i.e. run them faster than a CPU core can). With these, Intel hopes to close the CPU core-count gap it has with AMD EPYC, with the upcoming "Zen 4" EPYC chips expected to launch with up to 96 cores per socket in its conventional variant, and up to 128 cores per socket in its cloud-optimized variant.

Intel's on-package accelerators include AMX (advanced matrix extensions), which accelerate recommendation-engines, natural language processing (NLP), image-recognition, etc; DLB (dynamic load-balancing), which accelerates security-gateway and load-balancing; DSA (data-streaming accelerator), which speeds up the network stack, guest OS, and migration; IAA (in-memory analysis accelerator), which speeds up big-data (Apache Hadoop), IMDB, and warehousing applications; a feature-rich implementation of the AVX-512 instruction-set for a plethora of content-creation and scientific applications; and lastly, the QAT (QuickAssist Technology), with speed-ups for data compression, OpenSSL, nginx, IPsec, etc. Unlike "Ice Lake-SP," QAT is now implemented on the processor package instead of the PCH.

Intel has just released its "Architecture Instruction Set Extensions and Future Features Programming Reference" manual, which serves the purpose of providing the developers' information about Intel's upcoming hardware additions which developers can utilize later on. Today, thanks to the @InstLatX64 on Twitter we have information that Intel is bringing on-package High Bandwidth Memory (HBM) solution to its next-generation Sapphire Rapids Xeon processors. Specifically, there are two instructions mentioned: 0220H - HBM command/address parity error and 0221H - HBM data parity error. Both instructions are there to address data errors in HBM so the CPU operates with correct data.

The addition of HBM is just one of the many new technologies Sapphire Rapids brings. The platform is supposedly going to bring many new technologies like an eight-channel DDR5 memory controller enriched with Intel's Data Streaming Accelerator (DSA). To connect to all of the external accelerators, the platform uses PCIe 5.0 protocol paired with CXL 1.1 standard to enable cache coherency in the system. And as a reminder, this would not be the first time we see a server CPU use HBM. Fujitsu has developed an A64FX processor with 48 cores and HBM memory, and it is powering today's most powerful supercomputer - Fugaku. That is showing how much can a processor get improved by adding a faster memory on-board. We are waiting to see how Intel manages to play it out and what we end up seeing on the market when Sapphire Rapids is delivered.

Today, thanks to the ServeTheHome forum member "111alan", we have the first pictures of the alleged Intel Sapphire Rapids Xeon processor. Pictured is what appears to be a dual-die design similar to Cascade Lake-SP design with 56 cores and 112 threads that uses two dies. The Sapphire Rapids is a 10 nm SuperFin design that allegedly comes even in the dual-die configuration. To host this processor, the motherboard needs an LGA4677 socket with 4677 pins present. The new LGA socket, along with the new 10 nm Sapphire Rapids Xeon processors are set for delivery in 2021 when Intel is expected to launch its new processors and their respective platforms.

The processor pictured is clearly a dual-die design, meaning that Intel used some of its Multi-Chip Package (MCM) technology that uses EMIB to interconnect the silicon using an active interposer. As a reminder, the new 10 nm Sapphire Rapids platform is supposed to bring many new features like a DDR5 memory controller paired with Intel's Data Streaming Accelerator (DSA); a brand new PCIe 5.0 standard protocol with a 32 GT/s data transfer rate, and a CXL 1.1 support for next-generation accelerators. The exact configuration of this processor is unknown, however, it is an engineering sample with a clock frequency of a modest 2.0 GHz.

VORTEXGEAR, or simply Vortex for convenience, is another keyboard company that goes the path of atypical form factors, similar to Mistel Keyboard whom the company often collaborates with. Vortex especially gained popularity with the enthusiast keyboard market thanks to their 60% form factor Poker keyboard lineup, with the current iteration being the Poker 3, or Pok3r. At Computex, Vortex showed off a low profile Pok3r using the relatively new Cherry MX Low Profile switches, and the Red RGB variant in particular.

The Pok3r Ultra Slim will come with different keycap options to choose from, with some colors seen in the images below. As with the standard Pok3r, it features near-complete programmability with onboard macro support and three layers to work with. The keyboard will use an anodized CNC-machined aluminium case, with a detachable USB Type-C cable as well. Expect pricing to be similar to the standard Pok3r when this comes out later this year. Read past the break for more new keyboards from Vortex!

Mistel Keyboard has been making waves in the mechanical keyboard market for the last few years now, with new products shown off at Computex that then get ready for the retail channels soon after. Their product portfolio has been predominantly based on split keyboards and non-traditional form factors to appeal to a more specific market segment not targeted by the vast majority of other companies. The company has dipped their feet into the TKL form factor before with the MD870 SLEEKER, and at Computex this year they showed off their first full-size keyboard in the form of the HACKER MD800.

The keyboard supports USB (over a Type C detachable cable) and Bluetooth connectivity options, uses a metal case thick enough to ooze build quality and mass alike, OEM-profile thick PBT doubleshot injected keycaps in black, white, or a special mix edition, onboard macro support with three layers for functionality and programming, native Windows and MacOS support, and white LED backlighting with multiple lighting effects to choose from. Powered by AA batteries on the back, as well as the new Mistel logo on the Esc key, the HACKER MD800 arrives in Q3 2019 with a price point the company is finalizing on to appeal to the mass market upon release. Read past the break for more on the new Barocco MD770 keyboard as well.

Digital Media Professionals Inc. (DMP), a leading provider of 2D/3D graphics Intellectual Property (IP) cores, today announced it has become a new member and contributor to the Heterogeneous System Architecture (HSA) Foundation. HSA aims to push standards based architecture and interfaces for common computing use cases between CPU and GPU, enabling more effective hardware accelerated performance and power consumption on next generation compute platforms.

By supporting the HSA Foundation initiative, DMP wants to accelerate and simplify application development for mobile GPGPU platforms. The benefits of heterogeneous architectures and computing will allow smooth user experience for computer vision, image processing and graphics intensive applications on small consumer devices.