Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, announced the successful tape out of one of the industry's first UCIe IP subsystem on TSMC's N2 process, supporting 36G die-to-die data rates. The solution is fully integrated with TSMC's Chip-on-Wafer-on-Substrate (CoWoS ) advanced packaging technology, unlocking breakthrough bandwidth density and scalability for next-generation chiplet architectures.

This milestone builds on the recent release of the Alphawave Semi AI Platform, proving readiness to support the future of disaggregated SoCs and scale-up infrastructure for hyperscale AI and HPC workloads. With this tape-out, Alphawave Semi becomes one of the industry's first to enable UCIe connectivity on 2 nm nanosheet technology, marking a major step forward for the open chiplet ecosystem.

AMD is preparing the next-generation mobile processor based on Zen 6 "Medusa Point" APUs. According to industry leaker HXL, the new lineup will feature a surprisingly high core count, especially on the top-end Ryzen 9 model, which is expected to pack 22 CPU cores. Under the hood, the Ryzen 5 and Ryzen 7 Medusa Point APUs will use a hybrid layout that combines four high-performance classic cores, four dense cores optimized for efficiency, and two ultra-low‑power cores. On the graphics side, these chips will offer eight RDNA 3.5+ compute units, an upgrade from previous designs but still modest compared to some rivals. What really stands out is the Ryzen 9 variant, which reportedly adds a second Core Complex Die from AMD's desktop lineup. That extra 12‑core CCD joins the main ten-core die, bringing the total to 22 cores. While this pushes the CPU core count, AMD keeps the integrated graphics configuration unchanged, with just eight compute units.

Initial performance data hints that this trimmed-down GPU might run about 20 to 25 percent slower than the 12‑CU Radeon 890M used in earlier models. The eight CU GPU is half the power of current generation "Strix Point" with 16 CUs, but Medusa Point packs some RDNA 3.5+ upgrades. Even then, the raw CPU power should appeal to users who rely on heavily threaded applications, particularly in ultraportable laptops and mobile workstations. Medusa Point is built on the FP10 package, allowing for a slightly larger die size that houses the new core arrangement without sacrificing efficiency. Including dedicated low-power cores also marks AMD's first embrace of a heterogeneous x86 approach, similar to Intel's recent Core Ultra series. While more serious graphics work will mandate a combination of discrete GPUs for demanding workloads, Medusa Point will set new expectations for integrated CPU performance in thin, light notebooks.

Die shots of Intel's "Arrow Lake" desktop processors have appeared online, confirming the chiplet design we have known about since the launch. The images annotated by the YouTube channel HighYield show a four‑tile arrangement mounted on a base die made with Intel's 22 nm FinFET process. The compute tile sits at the top left, built on TSMC's N3B node and covering 117.24 mm². To its right are the SoC tile on TSMC's N6 node measuring 86.65 mm², and the GPU tile, which houses four Xe cores alongside an Arc Alchemist render slice. The I/O tile, at 24.48 mm² on the same N6 node, completes the group at the bottom left. Intel has redesigned its hybrid core layout for Arrow Lake, moving away from separate P‑core and E‑core clusters. Four of the eight high‑performance P‑cores line the die's outer edges, with the remaining four in the center. In between these lie the four efficiency E‑core clusters, each sharing 3 MB of L2 cache. A unified 36 MB L3 cache ring bus connects to every core, allowing E‑cores to tap into that larger cache pool for the first time. Intel aims to spread heat more evenly and boost background task performance.

The I/O tile integrates Thunderbolt 4 controllers, PCIe buffers and PHYs. The SoC tile carries display engines, media accelerators and DDR5 memory controllers. All tiles are bonded to the base die via Intel's Foveros Omni stacking technology. Arrow Lake also reflects a shift in Intel's manufacturing strategy. Plans to use Intel's 20A node were dropped in favor of TSMC processes, making this the first desktop CPU from Intel that relies almost entirely on external foundries. On the software side, Intel has begun offering its IPO profiles in select prebuilt systems. These presets optimize CPU and memory settings for a hassle‑free performance boost that remains within warranty limits. Meanwhile, the native 200S Boost overclocking option is rolling out via BIOS updates. Early tests suggest that 200S Boost alone yields modest gains unless paired with very high-speed DDR5 modules, while IPO profiles deliver more consistent improvements with mainstream memory configurations.

Surface defects on the GPU die of a PowerColor Radeon RX 9070 XT Hellhound have been linked to excessive thermal hotspots, according to analysis following Igor's Lab's investigation. Microscopic examination revealed 1,934 pits across the silicon die surface despite proper thermal interface material application. The defects affect over one percent of the chip's surface area, with the largest measuring 12.59 µm in depth and 212.36 µm in diameter—significantly exceeding industry tolerances. These imperfections impede heat transfer, causing localized temperatures to reach 113°C, exceeding the 110°C threshold for RDNA GPUs and triggering thermal throttling. The defects appear to stem from flaws in the backgrinding process that thins silicon wafers for packaging. Improper process control creates surface irregularities that compromise thermal conductivity and structural integrity.

The discovery raises questions about the effectiveness of automated optical inspection systems in detecting subtle surface abnormalities. TSMC, the maker of these chips, uses optical recognition tools to see if any defects occurred. AMD stated: "We are aware of the reported issue and believe this to be an isolated incident. We are working with our partners and internal teams to understand the issue." The company maintains this is an isolated case, though the findings suggest potential gaps in quality control protocols. Users experiencing thermal issues with affected RX 9070 XT units should initiate the RMA process for replacement while AMD and PowerColor investigate whether these defects exist beyond the identified sample. We hope no further issues are present, and so far, PowerColor hasn't received any customer complaints. We are on the lookout for further situation development. We reviewed PowerColor's Radeon RX 9070 Hellhound, and found no issues on our unit, so this indeed remains an isolated case so far.

Blue Cheetah Analog Design today announced the successful tape-outs of its next generation BlueLynx die-to-die (D2D) PHY on Samsung Foundry's SF4X 4 nm advanced manufacturing process. The latest PHY supports both advanced and standard chiplet packaging with an aggregate throughput exceeding 100 Tbps while achieving industry-leading silicon area footprint and power consumption. BlueLynx D2D subsystem IP enables chip architects to meet the bandwidth density and environmental robustness necessary to ensure production deployment success while preserving use case flexibility.

Using Samsung Foundry's SF4X 4 nm advanced process, the latest BlueLynx PHY supports both standard 2D and advanced 2.5D packages and enables system designers to seamlessly change packaging technologies in current and future implementations. Customer deliveries started in 2024 with silicon characterization in both advanced and standard packaging applications expected in early Q2 2025.

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

Thermal Grizzly, a high-performance cooling solutions provider, unveils a new line-up of products specifically designed for Intel's LGA 1851 socket, the latest Intel Core Ultra 200 Arrow Lake CPUs. The product line consists of four new solutions tailored to the improvements of 15th generation CPUs, including a CPU contact frame, a direct die water block, a CPU delidding tool and a delidding heater. Today, three of these products are now officially launched and available for purchase on the Thermal Grizzly web shop and through its Partner Reseller Network.

Intel 1851 CPU Contact Frame V1
In addition to a new internal contour for the contact surface, the new Intel 1851 CPU Contact Frame V1 considers the position of the socket on the motherboard. The thermal hotspot has shifted with the Arrow Lake CPUs and is now located further north compared to its predecessor. With a slight shift of Socket 1851 compared to LGA1700, Intel has attempted to counter the hotspot shift. Thus, CPU coolers designed for Socket 1700 can also be used with Socket 1851. The shift in the socket makes previous contact frames for Socket 1700 incompatible with 1851, which is why Thermal Grizzly now offers the Intel 1851 Contact Frame V1.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today revealed the successful delivery of first silicon for its NuLink -2.0 PHY, manufactured in a 3 nm process. The device achieves 64 Gbps/bump, the industry's highest performance for a die-to-die PHY solution for multi-die architectures. While compatible with UCIe standard, the milestone further confirms Eliyan's ability to extend die-to-die connectivity by 2x higher bandwidth, on standard as well as advanced packaging, at unprecedented power, area, and latency.

The NuLink-2.0 is a multi-mode PHY solution that also supports UMI (Universal Memory Interconnect), a novel chiplet interconnect technology that improves Die-to-Memory bandwidth efficiency by more than 2x. UMI leverages a dynamic bidirectional PHY whose specifications are currently being finalized with the Open Compute Project (OCP) as BoW 2.1.

Based on information shared by a Baidu user called Piglin, we now have access to an annotated die image of Qualcomm's Snapdragon X Elite processor. This analysis provides insights into the architecture of this new system-on-chip, highlighting several key features, including large CPU cores, a GPU, and a complex cache system. The report indicates that the Snapdragon X Elite die measures 169.6 mm² and is fabricated using TSMC's N4P 4 nm-class process. A notable aspect of the die shot is the considerable size of the "Phoenix" Oryon CPU cores, each reportedly measuring around 2.55 mm². These cores are significantly larger than typical Arm CPU cores, which is logical given their original purpose for the data center. The SoC features a total of 12 CPU cores in an 8+4 configuration.

The GPU, called Adreno X1, takes up 24.3 mm² of die area, roughly half the size of the CPU and CPU cache section. Despite its compact size, Qualcomm claims the GPU delivers approximately 4.6 FP32 TFLOPS of raw performance. Interestingly, the 45 TOPS NPU, which Qualcomm has emphasized as a key feature, is not clearly visible in the image. Another significant aspect is the extensive cache system. The three quad-core CPU clusters each occupy 16.1 mm², and feature 12 MB of high-speed L2 cache. Additionally, 6 MB is dedicated to system-level cache on 5.09 mm² area, along with a separate GPU cache. In total, the CPU boasts 54 MB of caches distributed across the die. The report also compares the Snapdragon X Elite to Apple's M4 SoC. However, it's worth noting that this isn't an exact comparison, as Apple utilizes an N3E 3 nm-class node for its chip. Below is the annotated die of Snapdragon X Elite and Apple's M4 from the original report.

EK, the leading computer cooling solutions provider, is rolling out a brand-new water block built from the ground up for the LGA 1700 socket, explicitly designed for delidded Intel Core CPUs. It bears improvements that benefit 14th-generation CPUs and shares almost no parts with the previously released Intel Direct Die water block. It includes a purpose-developed cold plate, cooling fin structure, and mounting mechanism. It relies on standoffs positioned at the four corners of the water block to ensure optimal contact with the CPU, eliminating concerns about applying too much or too little pressure on the bare CPU die, just like the AM5 Direct Die water block. EK's latest water block features EK-Matrix7 compatibility, meaning the product's height and port distance are managed in 7 mm increments for easier loop planning and precise results.

EK-Quantum Velocity² Direct Die D-RGB - 1700 Core Edition
This new direct die LGA 1700 water block is built from scratch and made to squeeze every bit of performance out of the 14th-generation Intel Core CPUs. The top is seethrough glass-like acrylic, with rich D-RGB illumination behind the window, which is riddled with aluminium bars going over the top and two G1/4" extenders that interrupt the flow of the black-anodized aluminium bars. These G1/4" extenders are standard Torque micro extenders. They can be replaced by other products from the EK-Quantum Torque Micro series, be it extenders of different finish, HDP or HDC fittings.

Ahead of the 2024 Optical Fiber Communication Conference (OFC), MediaTek (last week) announced it is launching a next-generation custom ASIC design platform that includes the heterogeneous integration of both high-speed electrical and optical I/Os in the same ASIC implementation. MediaTek will be demonstrating a serviceable socketed implementation that combines 8x800G electrical links and 8x800G optical links for a more flexible deployment. It integrates both MediaTek's in-house SerDes for electrical I/O as well as co-packaged Odin optical engines from Ranovus for optical I/O. Leveraging the heterogeneous solution that includes both 112G LR SerDes and optical modules, this CPO demonstration delivers reduced board space and device costs, boosts bandwidth density, and lowers system power by up to 50% compared to existing solutions.

Additionally, Ranovus' Odin optical engine has the option to provide either internal or external laser optical modules to better align with practical usage scenarios. MediaTek's ASIC experience and capabilities in the 3 nm advanced process, 2.5D and 3D advanced packaging, thermal management, and reliability, combined with optical experience, makes it possible for customers to access the latest technology for high-performance computing (HPC), AI/ML and data center networking.

According to sources close to Seoul Economy, and reported by DigiTimes, Intel has reportedly chosen Samsung as a supplier for its next-generation Lunar Lake processors, set to debut later this year. The report notes that Samsung will provide LPDDR5X memory devices for integration into Intel's processors. This collaboration could be a substantial win for Samsung, given Intel's projection to distribute millions of Lunar Lake CPUs in the coming years. However, it's important to note that this information is based on a leak and has not been officially confirmed. Designed for ultra-portable laptops, the Lunar Lake-MX platform is expected to feature 16 GB or 32 GB of LPDDR5X-8533 memory directly on the processor package. This on-package memory approach aims to minimize the platform's physical size while enhancing performance over traditional memory configurations. With Lunar Lake's exclusive support for on-package memory, Samsung's LPDDR5X-8533 products could significantly boost sales.

While Samsung is currently in the spotlight, it remains unclear if it will be the sole LPDDR5X memory provider for Lunar Lake. Intel's strategy involves selling processors with pre-validated memory, leaving the door open for potential validation of similar memory products from competitors like Micron and SK Hynix. Thanks to a new microarchitecture, Intel has promoted its Lunar Lake processors as a revolutionary leap in performance-per-watt efficiency. The processors are expected to utilize a multi-chipset design with Foveros technology, combining CPU and GPU chipsets, a system-on-chip tile, and dual memory packages. The CPU component is anticipated to include up to eight cores, a mix of four high-performance Lion Cove and four energy-efficient Skymont cores, alongside advanced graphics, cache, and AI acceleration capabilities. Apple's use of on-package memory in its M-series chips has set a precedent in the industry, and with Intel's Lunar Lake MX, this trend could extend across the thin-and-light laptop market. However, systems requiring more flexibility in terms of configuration, repair, and upgrades will likely continue to employ standard memory solutions like SODIMMs and/or the new CAMM2 modules that offer a balance of high performance and energy efficiency.

The PC master race has yielded many interesting activities for enthusiasts alike, with perhaps the pinnacle of activities being overclocking. Usually, subjects for overclocking include CPUs, GPUs, and RAM, with other components not actually being capable of overclocking. However, the enthusiast force never seems to settle, and today, we have proof of overclocking an off-the-shelf 2.5-inch SATA III NAND Flash SSD thanks to Gabriel Ferraz, a Computer Engineering graduate, and TechPowerUp's SSD database maintainer. He uses the RZX Pro 256 GB SSD in the video, a generic NAND Flash drive. The RZX Pro uses the Silicon Motion SM2259XT2 single-core, 32-bit ARC CPU running up to 550 MHz. It has two channels at 400 MHz, each with eight chip enable interconnects, allowing up to 16 NAND Flash dies to operate. The SSD doesn't feature a DRAM cache or support a host memory buffer. It has only one NAND Flash memory chip from Kioxia, uses BiCS FLASH 4 architecture, has 96 layers, and has 256 GB capacity.

While this NAND Flash die is rated for up to 400 MHz or 800 MT/s, it only ran at less than half the speed at 193.75 MHz or 387.5 MT/s at default settings. Gabriel acquired a SATA III to USB 3.0 adapter with a JMS578 bridge chip to perform the overclock. This adapter allows hot swapping of SSDs without the need to turn off the PC. He shorted two terminals in the drive's PCB to get the SSD to operate without its default safe mode. Mass Production Tools (MPTools), which OEMs use to flash SSDs, were used to change the firmware settings. Each NAND Flash architecture has its own special version of MPTools. The software directly shows control of the Flash clock, CPU clock, and output driving. However, additional tweaks like Flash IO driving with subdivisions need modifications. Control and Flash On-Die Termination (ODT) and Schmitt window trigger (referring to the Schmitt trigger comparator circuit) also needed a few modifications to make it work.

During the CES 2024 show, EK unveiled an exciting new addition to their premium all-in-one (AIO) CPU cooler lineup—the EK-Nucleus AIO CR360 Direct Die D-RGB. As the name suggests, this new 360 mm AIO water cooler is purpose-built for direct die cooling of delidded Intel LGA1700 CPUs. The EK-Nucleus Direct Die stands out with its custom cold plate and mounting mechanism, which are exclusively engineered for exposed CPU dies. The nickel-plated copper base ensures compatibility with liquid metal TIMs like the included Thermal Grizzly Conductonaut, which comes in the package. EK has worked with der8auer to provide delidding service kits and tools to facilitate easy DIY removal of the integrated heat spreader (IHS).

The package also contains a contact frame and protective foam for safe liquid metal application. At the heart of the cooler is a powerful AIO pump EK co-developed with the OEM manufacturer, meaning it is not an off-the-shelf pump found in other AIOs and is capable of up to 500 L/h flow rate. The reinforced, sleeved rubber tubing is fitted with aluminium covers for durability. Integrated omnilink connectors allow daisy chaining of the three included 120 mm D-RGB fans for cable management. The EK-Nucleus Direct Die offers extensive RGB lighting customization with illuminated circle accents on the removable pump top covers. The diamond-cut brushed aluminium side panels and radiator cowl add to the premium aesthetic. The new AIO will be available for the Intel LGA1700 platform, with hopefully more versions later. The EK-Nucleus AIO CR360 Direct Die D-RGB is now available for pre-order at €202.90 MSRP price tag.

Thanks to the leaked slides obtained by @InstLatX64, we have more details and some performance estimates about Intel's upcoming 5th Generation Xeon "Emerald Rapids" CPUs, boasting a significant performance leap over its predecessors. Leading the Emerald Rapids family is the top-end SKU, the Xeon 8592+, which features 64 cores and 128 threads, backed by a massive 480 MB L3 cache pool. The upcoming lineup shifts from a 4-tile to a 2-tile design to minimize latency and improve performance. The design utilizes the P-Core architecture under the Raptor Cove ISA and promises up to 40% faster performance than the current 4th Generation "Sapphire Rapids" CPUs in AI applications utilizing Intel AMX engine. Each chiplet has 35 cores, three of which are disabled, and each tile has two DDR5-5600 MT/s memory controllers, which operate two memory channels each and translating that into eight-channel design. There are three PCIe controllers per die, making it six in total.

Newer protocols and AI accelerators also back the upcoming lineup. Now, the Emerald Rapids family supports the Compute Express Link (CXL) Types 1/2/3 in addition to up to 80 PCIe Gen 5 lanes and enhanced Intel Ultra Path Interconnect (UPI). There are four UPI controllers spread over two dies. Moreover, features like the four on-die Intel Accelerator Engines, optimized power mode, and up to 17% improvement in general-purpose workloads make it seem like a big step up from the current generation. Much of this technology is found on the existing Sapphire Rapids SKUs, with the new generation enhancing the AI processing capability further. You can see the die configuration below. The 5th Generation Emerald Rapids designs are supposed to be official on December 14th, just a few days away.

Synopsys, Inc. today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."

NVIDIA's upcoming Blackwell GPU architecture, expected to succeed the current Ada Lovelace architecture, is gearing up to make some significant changes. While we don't have any microarchitectural leaks, rumors are circulating that Blackwell will have different packaging and die structures. One of the most intriguing aspects of the upcoming Blackwell is the mention of a Multi-Chip Module (MCM) design for the GB100 data-center GPU. This advanced packaging approach allows different GPU components to exist on separate dies, providing NVIDIA with more flexibility in chip customization. This could mean that NVIDIA can more easily tailor its chips to meet the specific needs of various consumer and enterprise applications, potentially gaining a competitive edge against rivals like AMD.

While Blackwell's release is still a few years away, these early tidbits paint a picture of an architecture that isn't just an incremental improvement but could represent a more significant shift in how NVIDIA designs its GPUs. NVIDIA's potential competitor is AMD's upcoming MI300 GPU, which utilized chiplets in its designs. Chiplets also provide ease of integration as smaller dies provide better wafer yields, meaning that it makes more sense to switch to smaller dies and utilize chiplets economically.

Tachyum today announced that new EDA tools, utilized during the physical design phase of the Prodigy Universal Processor, have allowed the company to achieve significantly better results with chip specifications than previously anticipated, after the successful change in physical design tools - including an increase in the number of Prodigy cores to 192.

After RTL design coding, Tachyum began work on completing the physical design (the actual placement of transistors and wires) for Prodigy. After the Prodigy design team had to replace IPs, it also had to replace RTL simulation and physical design tools. Armed with a new set of EDA tools, Tachyum was able to optimize settings and options that increased the number of cores by 50 percent, and SERDES from 64 to 96 on each chip. Die size grew minimally, from 500mm2 to 600mm2 to accommodate improved physical capabilities. While Tachyum could add more of its very efficient cores and still fit into the 858mm2 reticle limit, these cores would be memory bandwidth limited, even with 16 DDR5 controllers running in excess of 7200MT/s. Tachyum cores have much higher performance than any other processor cores.

Samsung Electronics today reported financial results for the second quarter ended June 30, 2023. The Company posted KRW 60.01 trillion in consolidated revenue, a 6% decline from the previous quarter, mainly due to a decline in smartphone shipments despite a slight recovery in revenue of the DS (Device Solutions) Division. Operating profit rose sequentially to KRW 0.67 trillion as the DS Division posted a narrower loss, while Samsung Display Corporation (SDC) and the Digital Appliances Business saw improved profitability.

The Memory Business saw results improve from the previous quarter as its focus on High Bandwidth Memory (HBM) and DDR5 products in anticipation of robust demand for AI applications led to higher-than-guided DRAM shipments. System semiconductors posted a decline in profit due to lower utilization rates on weak demand from major applications.

Accelerating the integration of heterogeneous dies to enable the next level of system scalability and functionality, Synopsys, Inc. (Nasdaq: SNPS) has strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. Synopsys provides the industry's most comprehensive EDA and IP solutions for multi-die systems on TSMC's advanced 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard. The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology on TSMC processes allows designers to tackle the biggest challenges of multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.

"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimized for our most advanced technologies."

Although we've known most of the details of AMD's I/O die in its Zen 4 processors, until now, AMD hadn't shared a die shot of the cIOD, but thanks to its ISSCC 2023 presentation, we not only have a die shot of the cIOD, but some friendly people on the internet have also made annotations for us mere mortals. There are no big secrets here, but based on the annotations by @Locuza_ we now know for certain that it's not possible to use the current I/O die with three CCDs, as it only has two GMI3 interfaces, to which the CCDs are connected.

If you're wondering about the 2x 40-bit memory interface, it's for ECC memory support outside of the on-die ECC support of DDR5 memory. Also note that DDR5 memory is two times 32-bit in non ECC mode. That said, it's up to the motherboard makers to implement support for ECC memory, but it would appear all Zen 4 CPUs support it. The addition of a GPU, even a basic one like this, takes up a fair bit of space inside the cIOD, especially once you add things like video decoders/encoders and so on. In fact, it appears that the parts related to the GPU and video decoders/encoders take up at least a third of the space inside the I/O die, yet thanks to a significant die shrink from the Zen 3 era cIOD, it's physically smaller in the Zen 4 processors, while having an estimated 58 percent increase in transistors.

We have recently seen the first high-resolution die shots of AMD's Ryzen 5 5600G Cezanne APU thanks to the work of Fritzchens Fritz. The photos show the internal layout of the processor with its Zen 3 CPU, Vega GPU, and corresponding components. To get these shots, the chip had to be delidded by removing the IHS which has been made harder with the move to a soldered design. The Ryzen 5 5600G is a 6 core, 12 thread part with 7 Vega GPU cores which can all be seen in the annotated diagram of the die created by Locuza. The diagram also shows the suspected locations of various PCIe 3.0, and memory controllers along with cache placements for the CPU and GPU. The processor is manufactured on TSMC's 7 nm process and features a total of 10.7 Billion transistors packed into the 180 mm² die.

AMD is in a constant process of processor development, and there are always new technologies on the horizon. Back in March of 2020, the company has revealed that it is working on new X3D packaging technology, that integrated both 2.5D and 3D approaches to packing semiconductor dies together as tightly as possible. Today, we are finally getting some more information about the X3D technology, as we have the first codename of the processor that is featuring this advanced packaging technology. According to David Schor, we have learned that AMD is working on a CPU that uses X3D tech with stacked dies, and it is called Milan-X.

The Milan-X CPU is AMD's upcoming product designed for data center usage. The rumors suggest that the CPU is designed for heavy bandwidth and presumably a lot of computing power. According to ExecutableFix, the CPU uses a Genesis-IO die to power the connectivity, which is an IO die from EPYC Zen 3 processors. While this solution is in the works, we don't know the exact launch date of the processor. However, we could hear more about it in AMD's virtual keynote at Computex 2021. For now, take this rumor with a grain of salt.

When AMD and Sony collaborated on making the next generation console chip, AMD has internally codenamed it Flute, while Sony codenamed it Oberon or Ariel. This PlayStation 5 SoC die has today been pictured thanks to the Fritzchens Fritz and we get to see a closer look at the die internals. Featuring eight of AMD's Zen2 cores that can reach frequencies of up to 3.5 GHz, the CPU is paired with 36 CU GPU based on the RDNA 2 technology. The GPU is capable of running at speed of up to 2.23 GHz. The SoC has been made to accommodate all of that hardware, and bring IO to connect it all.

When tearing down the console, the heatsink and the SoC are connected by liquid metal, which is used to achieve the best possible heat transfer between two surfaces. Surrounding the die there is a small amount of material used to prevent liquid metal (a conductive material) from possibly spilling and shorting some components. Using a special short wave infrared light (SWIR) microscope, we can take a look at what is happening under the hood without destroying the chip. And really, there are a few distinct areas that are highlighted by the Twitter user @Locuza. As you can see, the die has special sectors with the CPU complex and a GPU matrix with plenty of workgroups and additional components for raytracing.

VideoCardz has recently received a render of the upcoming AMD Ryzen 5000 Cezanne APU which is expected to be unveiled next week. The Zen 3 Cezanne APUs support up to 8 cores and 16 threads just like Zen 2 Renoir APUs. The Cezanne APU should support up to 8 graphics cores and 20 PCIe lanes, it is currently unknown whether these lanes will be PCIe 3.0 or PCIe 4.0. The Cezanne die appears to be ~10% larger than Renoir which comes from the larger Zen 3 core design and a larger L3 cache of 16 MB. The new Ryzen 5000H Cezanne series processors are expected to be announced by AMD next week and will power upcoming low and high power laptops.