TSMC today announced the Open Innovation Platform (OIP) 3DFabric Alliance at the 2022 Open Innovation Platform Ecosystem Forum. The new TSMC 3DFabric Alliance is TSMC's sixth OIP Alliance and the first of its kind in the semiconductor industry that joins forces with partners to accelerate 3D IC ecosystem innovation and readiness, with a full spectrum of best-in-class solutions and services for semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. This alliance will help customers achieve speedy implementation of silicon and system-level innovations and enable next-generation HPC and mobile applications using TSMC's 3DFabric technologies, a comprehensive family of 3D silicon stacking and advanced packaging technologies.

"3D silicon stacking and advanced packaging technologies open the door to a new era of chip-level and system-level innovation, and also require extensive ecosystem collaboration to help designers navigate the best path through the myriad options and approaches available to them," said Dr. L.C. Lu, TSMC fellow and vice president of design and technology platform. "Through the collective leadership of TSMC and our ecosystem partners, our 3DFabric Alliance offers customers an easy and flexible way to unlocking the power of 3D IC in their designs, and we can't wait to see the innovations they can create with our 3DFabric technologies."

Alphawave IP (LSE: AWE), a global leader in high-speed connectivity for the world's technology infrastructure, today announced the successful tapeout of its ZeusCORE100 1-112 Gbps NRZ/PAM4 Serialiser-Deserialiser ("SerDes"), Alphawave's first testchip on TSMC's most advanced N3E process. Alphawave IP will be exhibiting this new product alongside its complete portfolio of high-performance IP, chiplet, and custom silicon solutions at the TSMC OIP Forum on October 26 in Santa Clara, CA as the Platinum sponsor.

ZeusCORE100 is Alphawave's most advanced multi-standard-SerDes, supporting extra-long channels over 45dB and the most requested standards such as 800G Ethernet, OIF 112G-CEI, PCIe GEN6, and CXL 3.0. Attendees will be able to visit the Alphawave booth and meet the company's technology experts including members of the recently acquired OpenFive team. OpenFive is a longstanding partner of TSMC through the OIP Value Chain Aggregator (VCA) program. OpenFive is one of a select few companies with an idea-to-silicon methodology in TSMC's latest technologies, and advanced packaging capabilities, enabling access to the most advanced foundry solution available with the best Power-Performance-Area (PPA). With Alphawave's industry-leading IP portfolio and the addition of OpenFive's capabilities, designers can create systems on a chip (SoCs) that pack more compute power into smaller form factors for networking, AI, storage, and high-performance computing (HPC) applications.

According to the latest TrendForce research, pandemic-induced materials shortages abated in the second half of this year and the supply and delivery of short-term materials has recovered significantly. However, assuming materials supply is secure and demand can be met, the annual growth rate of server shipments in 2023 is estimated to be only 3.7%, which is lower than 5.1% in 2022.

TrendForce indicates that this growth slowdown is due to three factors. First, once material mismatch issues had eased, buyers began adjusting previously placed purchase order overruns. Thus, ODM orders also decreased but this will not affect the 2022 shipment volume of whole servers for the time being. Second, due to the impact of rising inflation and weakness in the overall economy, corporate capital investment may trend more conservative and IT-related investment will emphasize flexibility, such as the replacement of certain server terminals with cloud services. Third, geopolitical changes will drive the continuing emergence of demand for small-scale data centers and previous construction of hyperscale data centers will slow. The recent ban on military/HPC servers issued by the U.S. Department of Commerce on October 7 has a very low market share in terms of its application category, so the impact on the overall server market is limited at present. However, if the scope of the ban is expanded further in the future, it will herald a more significant slowdown risk for China's server shipment momentum in 2023.

When AMD announced that the company would deliver the world's fastest supercomputer, Frontier, the company also took a massive task to provide a machine capable of producing one ExaFLOP of total sustained ability to perform computing tasks. While the system is finally up and running, making a machine of that size run properly is challenging. In the world of High-Performance Computing, getting the hardware is only a portion of running the HPC center. In an interview with InsideHPC, Justin Whitt, program director for the Oak Ridge Leadership Computing Facility (OLCF), provided insight into what it is like to run the world's fastest supercomputer and what kinds of issues it is facing.

The Frontier system is powered by AMD EPYC 7A53s "Trento" 64-core 2.0 GHz CPUs and Instinct MI250X GPUs. Interconnecting everything is the HPE (Cray) Slingshot 64-port switch, which is responsible for sending data in and out of compute blades. The recent interview points out a rather interesting finding: exactly AMD Instinct MI250X GPUs and Slingshot interconnect cause hardware troubles for the Frontier. "It's mostly issues of scale coupled with the breadth of applications, so the issues we're encountering mostly relate to running very, very large jobs using the entire system … and getting all the hardware to work in concert to do that," says Justin Whitt. In addition to the limits of scale "The issues span lots of different categories, the GPUs are just one. A lot of challenges are focused around those, but that's not the majority of the challenges that we're seeing," he said. "It's a pretty good spread among common culprits of parts failures that have been a big part of it. I don't think that at this point that we have a lot of concern over the AMD products. We're dealing with a lot of the early-life kind of things we've seen with other machines that we've deployed, so it's nothing too out of the ordinary."

Samsung Electronics, a world leader in advanced semiconductor technology, announced today a strengthened business strategy for its Foundry Business with the introduction of cutting-edge technologies at its annual Samsung Foundry Forum event. With significant market growth in high-performance computing (HPC), artificial intelligence (AI), 5/6G connectivity and automotive applications, demand for advanced semiconductors has increased dramatically, making innovation in semiconductor process technology critical to the business success of foundry customers. To that end, Samsung highlighted its commitment to bringing its most advanced process technology, 1.4-nanometer (nm), for mass production in 2027.

During the event, Samsung also outlined steps its Foundry Business is taking in order to meet customers' needs, including: foundry process technology innovation, process technology optimization for each specific applications, stable production capabilities, and customized services for customers. "The technology development goal down to 1.4 nm and foundry platforms specialized for each application, together with stable supply through consistent investment are all part of Samsung's strategies to secure customers' trust and support their success," said Dr. Si-young Choi, president and head of Foundry Business at Samsung Electronics. "Realizing every customer's innovations with our partners has been at the core of our foundry service."

DFI, the world's leading brand in embedded motherboards and industrial computers, was invited to participate in "AMD Datacenter Solutions Day" in September, based on the theme of high-performance computing (HPC). As the first in the world to launch the smallest industrial motherboard equipped with AMD products, DFI partnered with its subsidiary, AEWIN, to present their star products and share how ultra-small products can help the trend of software virtualization technologies in the forum. We hope to optimize the development of diverse services in IoT applications.

AMD invited industry giants to the event to discuss the future of high-performance computing and conduct in-depth discussions with their partners related to high-performance computing, cloud computing, and AI. DFI was a speaker in the digital learning AI session during the event. DFI shared their views on software-defined IoT and explained the role of ultra-small products in the application environment.

According to TrendForce research, due to steady weakening of overall demand for consumer electronics, inventory pressure has increased among downstream distributors and brands. Although there are still sporadic shortages of specific components, the curtain has officially fallen on a two-year wave of shortages in general, and brands have gradually suspended stocking in response to changes in market conditions. However, stable demand for automotive and industrial equipment is key to supporting the ongoing growth of foundry output value. At the same time, since the creation of a marginal amount of new capacity in 2Q22 led to growth in wafer shipments and a price hike for certain wafers, this drove output value among top ten foundries to reach US$33.20 billion in 2Q22. Quarterly growth fell to 3.9% on a weakening consumer market.

A prelude to inventory correction was officially revealed in 3Q22. In addition to intensifying severity in the initial wave of order slashing for LDDI/TDDI, and TV SoC, diminishing order volume also extended to non-Apple smartphone APs and peripheral IC PMIC, CIS, and consumer electronics PMICs, and mid-to-low-end MCUs, posing a challenge for foundry capacity utilization. However, the launch of the new iPhone in 3Q22 is expected to prop up a certain amount of stocking momentum for the sluggish market. Therefore, top ten foundry revenue in 3Q22 is expected to maintain a growth trend driven by high-priced processes and quarterly growth rate is expected to be slightly higher than in 2Q22.

NVIDIA's high-performance computing hardware stack is now equipped with the top-of-the-line Hopper H100 GPU. It features 16896 or 14592 CUDA cores, developing if it comes in SXM5 of PCIe variant, with the former being more powerful. Both variants come with a 5120-bit interface, with the SXM5 version using HBM3 memory running at 3.0 Gbps speed and the PCIe version using HBM2E memory running at 2.0 Gbps. Both versions use the same capacity capped at 80 GBs. However, that could soon change with the latest rumor suggesting that NVIDIA could be preparing a PCIe version of Hopper H100 GPU with 120 GBs of an unknown type of memory installed.

According to the Chinese website "s-ss.cc" the 120 GB variant of the H100 PCIe card will feature an entire GH100 chip with everything unlocked. As the site suggests, this version will improve memory capacity and performance over the regular H100 PCIe SKU. With HPC workloads increasing in size and complexity, more significant memory allocation is needed for better performance. With the recent advances in Large Language Models (LLMs), AI workloads use trillions of parameters for tranining, most of which is done on GPUs like NVIDIA H100.

During its GTC 2022 session, NVIDIA introduced its new generation of gaming graphics cards based on the novel Ada Lovelace architecture. Dubbed NVIDIA GeForce RTX 40 series, it brings various updates like more CUDA cores, a new DLSS 3 version, 4th generation Tensor cores, 3rd generation Ray Tracing cores, and much more, which you can read about here. However, today, we also got a new Ada Lovelace card intended for the data center. Called the L40, NVIDIA updated its previous Ampere-based A40 design. While the NVIDIA website provides sparse, the new L40 GPU uses 48 GB GDDR6 memory with ECC error correction. Using NVLink, you can get 96GBs of VRAM. Paired with an unknown SKU, we assume that it uses AD102 with adjusted frequencies to lower the TDP and allow for passive cooling.

NVIDIA is calling this their Omniverse GPU, as it is a part of the push to separate its GPUs used for graphics and AI/HPC models. The "L" model in the current product stack is used to accelerate graphics, with display ports installed on the GPU, while the "H" models (H100) are there to accelerate HPC/AI installments where visual elements are a secondary task. This is a further separation of the entire GPU market, where the HPC/AI SKUs get their own architecture, and GPUs for graphics processing are built on a new architecture as well. You can see the specifications provided by NVIDIA below.

Yesterday, NVIDIA launched its GeForce RTX 40-series, based on the "Ada" graphics architecture. We're yet to receive a technical briefing about the architecture itself, and the various hardware components that make up the silicon; but NVIDIA on its website gave us a first look at what's in store with the key number-crunching components of "Ada," namely the Ada CUDA core, 4th generation Tensor core, and 3rd generation RT core. Besides generational IPC and clock speed improvements, the latest CUDA core benefits from SER (shader execution reordering), an SM or GPC-level feature that reorders execution waves/threads to optimally load each CUDA core and improve parallelism.

Despite using specialized hardware such as the RT cores, the ray tracing pipeline still relies on CUDA cores and the CPU for a handful tasks, and here NVIDIA claims that SER contributes to a 3X ray tracing performance uplift (the performance contribution of CUDA cores). With traditional raster graphics, SER contributes a meaty 25% performance uplift. With Ada, NVIDIA is introducing its 4th generation of Tensor core (after Volta, Turing, and Ampere). The Tensor cores deployed on Ada are functionally identical to the ones on the Hopper H100 Tensor Core HPC processor, featuring the new FP8 Transformer Engine, which delivers up to 5X the AI inference performance over the previous generation Ampere Tensor Core (which itself delivered a similar leap by leveraging sparsity).

The demand for data is insatiable, from 5G to the cloud to smart cities. As a society we want more autonomy, information to fuel our decisions and habits, and connection - to people, stories, and experiences.

To address these demands, the cloud infrastructure of tomorrow will need to handle the coming data explosion and the effective processing of evermore complex workloads … all while increasing power efficiency and minimizing carbon footprint. It's why the industry is increasingly looking to the performance, power efficiency, specialized processing and workload acceleration enabled by Arm Neoverse to redefine and transform the world's computing infrastructure.

AMD today announced it is joining the newly created PyTorch Foundation as a founding member. The foundation, which will be part of the non-profit Linux Foundation, will drive adoption of Artificial Intelligence (AI) tooling by fostering and sustaining an ecosystem of open source projects with PyTorch, the Machine Learning (ML) software framework originally created and fostered by Meta.

As a founding member, AMD joins others in the industry to prioritize the continued growth of PyTorch's vibrant community. Supported by innovations such as the AMD ROCm open software platform, AMD Instinct accelerators, Adaptive SoCs and CPUs, AMD will help the PyTorch Foundation by working to democratize state-of-the-art tools, libraries and other components to make these ML innovations accessible to everyone.

With its recent announcement of the Ryzen 7000 desktop processors, the action now shifts to the server, with AMD preparing a wide launch of its EPYC "Genoa" and "Bergamo" processors this year. Powered by the "Zen 4" microarchitecture, and contemporary I/O that includes PCI-Express Gen 5, CXL, and DDR5, these processors dial the CPU core-counts per socket up to 96 in case of "Genoa," and up to 128 in case of "Bergamo." The EPYC "Genoa" series represents the main trunk of the company's server processor lineup, with various internal configurations targeting specific use-cases.

The 96 cores are spread twelve 5 nm 8-core CCDs, each with a high-bandwidth Infinity Fabric path to the sIOD (server I/O die), which is very likely built on the 6 nm node. Lower core-count models can be built either by lowering the CCD count (ensuring more cores/CCD), or by reducing the number of cores/CCD and keeping the CCD-count constant, to yield more bandwidth/core. The leaked product-stack table below shows several of these sub-classes of "Genoa" and "Bergamo," classified by use-cases. The leaked slide also details the nomenclature AMD is using with its new processors. The leaked roadmap also mentions the upcoming "Genoa-X" processor for HPC and cloud-compute uses, which features the 3D Vertical Cache technology.

Ansys announced that Ansys Mechanical is one of the first commercial finite element analysis (FEA) programs supporting AMD Instinct accelerators, the newest data center GPUs from AMD. The AMD Instinct accelerators are designed to provide exceptional performance for data centers and supercomputers to help solve the world's most complex problems. To support the AMD Instinct accelerators, Ansys developed APDL code in Ansys Mechanical to interface with AMD ROCm libraries on Linux, which will support performance and scaling on the AMD accelerators.

Ansys' latest collaboration with AMD resulted in a solution that, according to Ansys' tests, significantly speeds up simulation of large structural mechanical models—between three and six times faster for Ansys Mechanical applications using the sparse direct solver. Adding support for AMD Instinct accelerators in Ansys Mechanical gives customers greater flexibility in their choice of high-performance computing (HPC) hardware.

Intel today launched its Arctic Sound M line of data-center GPUs. These are not positioned as HPC processors like the "Ponte Vecchio," but GPUs targeting cloud-compute providers, with their main applications being in the realm of visual processing, media, and AI inferencing. Their most interesting aspect has to be the silicon, which are the same 6 nm "ACM-G11" and "ACM-G10" chips powering the Arc "Alchemist" client graphics cards, based on the Xe-HPG architecture. Even more interesting is their typical board power values, ranging between 75 W to 150 W. The cards are built in the PCI-Express add-on card form-factor, with their cooling solutions optimized for rack airflow.

The marketing name for these cards is simply Intel Data Center GPU Flex, with two models being offered: The Data Center GPU Flex-140, and Flex-170. The Flex-170 is a full-sized add-on card based on the larger ACM-G10 silicon, which has 32 Xe Cores (4,096 unified shaders), whereas the Flex-140, interestingly, is a low-profile dual-GPU card with two smaller ACM-G11 chips that each has 8 Xe Cores (1,024 unified shaders). The two chips appear to be sharing a PCIe bridge chip in the renders. Both models come with four Xe Media Engines that pack AV1 encode hardware-acceleration, XMX AI acceleration, real-time ray tracing, and GDDR6 memory.

AMD in its HotChips 22 presentation released a block-diagram of its biggest AI-HPC processor, the Instinct MI250X. Based on the CDNA2 compute architecture, at the heart of the MI250X is the "Aldebaran" MCM (multi-chip module). This MCM contains two logic dies (GPU dies), and eight HBM2E stacks, four per GPU die. The two GPU dies are connected by a 400 GB/s Infinity Fabric link. They each have up to 500 GB/s of external Infinity Fabric bandwidth for inter-socket communications; and PCI-Express 4.0 x16 as the host system bus for AIC form-factors. The two GPU dies together make up 58 billion transistors, and are fabricated on the TSMC N6 (6 nm) node.

The component hierarchy of each GPU die sees eight Shader Engines share a last-level L2 cache. The eight Shader Engines total 112 Compute Units, or 14 CU per engine. The CDNA2 compute unit contains 64 stream processors making up the Shader Core, and four Matrix Core Units. These are specialized hardware for matrix/tensor math operations. There are hence 7,168 stream processors per GPU die, and 14,336 per package. AMD claims a 100% increase in double-precision compute performance over CDNA (MI100). AMD attributes this to increases in frequencies, efficient data paths, extensive operand reuse and forwarding; and power-optimization enabling those higher clocks. The MI200 is already powering the Frontier supercomputer, and is working for more design wins in the HPC space. The company also dropped a major hint that the MI300, based on CDNA3, will be an APU. It will incorporate GPU dies, core-logic, and CPU CCDs onto a single package, in what is a rival solution to NVIDIA Grace Hopper Superchip.

If InnoSilicon's Fenghua gaming GPU hit the scene last November seemingly out of nowhere, then another Chinese GPU developer is making waves at HotChips 22, this time in the enterprise space. The BR100 by BIREN is a large AI-HPC GPU-based processor that's China's answer to the Hopper, Ponte Vecchio, and CDNA2, and ensure China's growth as an AI/HPC leader is unaffected in the event of a tech embargo for whatever reason.

The BR100 is an MCM of two planar-silicon dies built on the 7 nm DUV node, with a striking 77 billion transistor-count between them, and 550 W TDP (typical). The chip features 64 GB of on-package HBM2E memory. System bus interfaces include PCI-Express 5.0 x16 with CXL, and eight lanes of a proprietary interconnect called B-Link, which total 2.3 TB/s of bandwidth. The processor supports nearly all popular compute formats except double-precision floating-point, or FP64. Among the supported ones are single-precision or FP32, TF32+, FP16, BF16, INT16, and INT8. BIREN claims up to 256 TFLOP/s FP32, up to 512 TFLOP/s TF32+, up to 1 PFLOP/s BF16, and 2,048 TOPS INT8. This would put it at 2.4 to 2.8 times faster than NVIDIA's "Ampere" A100.

NVIDIA designed the Grace CPU, a processor in the classical sense, to replace the Intel Xeon or AMD EPYC processors it was having to cram into its pre-built HPC compute servers for serial-processing roles, and mainly because those half-a-dozen GPU HPC processors need to be interconnected by a CPU. The company studied the CPU-level limitations and bottlenecks not just with I/O, but also the machine-architecture, and realized its compute servers need a CPU purpose-built for the role, with an architecture that's heavily optimized for NVIDIA's APIs. This, the NVIDIA Grace CPU was born.

This is NVIDIA's first outing with a CPU with a processing footprint rivaling server processors from Intel and AMD. Built on the TSMC N4 (4 nm EUV) silicon fabrication process, it is a monolithic chip that's deployed standalone with an H100 HPC processor on a single board that NVIDIA calls a "Superchip." A board with a Grace and an H100, makes up a "Grace Hopper" Superchip. A board with two Grace CPUs makes a Grace CPU Superchip. Each Grace CPU contains a 900 GB/s switching fabric, a coherent interface, which has seven times the bandwidth of PCI-Express 5.0 x16. This is key to connecting the companion H100 processor, or neighboring Superchips on the node, with coherent memory access.

With AMD and NVIDIA launching its next-generation HPC compute architectures, "Hopper" and CDNA2, it began seeming like Intel's ambitious "Ponte Vecchio" accelerator based on the Xe-HP architecture, has missed the time-to-market bus. Intel doesn't think so, and in its Hot Chips 34 presentation, disclosed some of the first detailed performance claims that—at least on paper—put the "Hopper" H100 accelerator's published compute performance numbers to shame. We already had some idea of how Ponte Vecchio would perform this spring, at Intel's ISC'22 presentation, but the company hadn't finalized the product's power and thermal characteristics, which are determined by its clock-speed and boosting behavior. Team blue claims to have gotten over the final development hurdles, and is ready with some big numbers.

Intel claims that in classic FP32 (single-precision) and FP64 (double-precision) floating-point tests, its silicon is highly competitive with the H100 "Hopper," with the company claiming 52 TFLOP/s FP32 for the "Ponte Vecchio," compared to 60 TFLOP/s for the H100; and a significantly higher 52 TFLOP/s FP64 for the "Ponte Vecchio," compared to 30 TFLOP/s for the H100. This has to do with the SIMD units of the Xe-HP architecture all being natively capable of double-precision floating-point operations; whereas NVIDIA's architecture typically relies on FP64-specialized streaming multiprocessors.

AMD (NASDAQ: AMD) today announced its 27th annual Corporate Responsibility Report, demonstrating how AMD - together with its employees, customers, partners, and communities - advances computing to help solve the world's most important social and environmental challenges. From advancing sustainable computing to cultivating a diverse workforce, AMD is committed to responsibly delivering on its mission to be the high-performance and adaptive computing leader. AMD now powers the fastest and most energy-efficient supercomputer in the world - the Frontier supercomputer - as well as 17 of the top 20 most efficient supercomputers. To drive continued innovation, diversity hiring remains a component of the company's strategic metrics and milestones to inform its annual bonus program. AMD also entered into a $3 billion sustainability-linked credit facility, demonstrating its commitment to advancing sustainability.

In 2021, AMD announced new corporate responsibility goals for 2025 and 2030 spanning digital impact, environmental sustainability, supply chain responsibility, and diversity, belonging, and inclusion. Today, the company reported it is on track to achieve these goals. "At AMD, it is not just what our semiconductor technology can do that matters, but also how we develop and deliver it," said Susan Moore, AMD corporate vice president, corporate responsibility, and international government affairs. "Together with our employees, partners, and customers, we create possibilities for how our high-performance and adaptive computing can advance an inclusive, sustainable future for our world."

Based on media reports out of Taiwan, TSMC seems to have plenty of customers lined up for its 3 nm node, with Apple being the first customer out the gates when production starts sometime next month. However, TSMC is only expected to start the production with a mere 1,000 wafer starts a month, which seems like a very low figure, especially as this is said to remain unchanged through all of Q4. On the plus side, yields are expected to be better than the initial 5 nm node yields. Full-on mass production for the 3 nm node isn't expected to happen until the second half of 2023 and TSMC will also kick off its N3E node sometime in 2023.

Apart from Apple, major customers for the 3 nm node include AMD, Broadcom, Intel, MediaTek, NVIDIA and Qualcomm. Contrary to earlier reports by TrendForce, it appears that TSMC will continue its rollout of the 3 nm node as previously planned. Apple is expected to produce the A17 smartphone and tablet SoC, as well as advanced versions of the M2, as well as the M3 laptop and desktop processors on the 3 nm node. Intel is still said to be producing its graphics chiplets with TSMC, with the potential for GPU and FPGA products in the future. There's no word on what the other customers are planning to produce on the 3 nm node, but MediaTek and Qualcomm are obviously looking at using the node for future smartphone and tablet SoCs, with AMD and NVIDIA most likely aiming for upcoming GPUs and Broadcom for some kind of HPC related hardware.

Tachyum today announced that it has responded to a U.S. Department of Energy Request for Information soliciting Advanced Computing Ecosystems for DOE national laboratories engaged in scientific and national security research. Tachyum has submitted a proposal to create a 20-exaflop supercomputer based on Tachyum's Prodigy, the world's first universal processor.

The DOE's request calls for computing systems that are five to 10 times faster than those currently available and/or that can perform more complex applications in "data science, artificial intelligence, edge deployments at facilities, and science ecosystem problems, in addition to the traditional modeling and simulation applications."

Infortrend Technology, Inc., the industry-leading enterprise storage provider, released their flagship EonStor GS all-flash unified storage systems. Featuring the latest Intel Xeon D CPU, PCIe Gen4, and 100GbE, the solutions are perfect for applications requiring low latency and high performance such as database, virtualization, HPC, multimedia and entertainment (M&E).

EonStor GS series is designed for enterprises to flexibly deploy and utilize in a variety of applications. It has been chosen and deployed by several global enterprises and organizations. These organizations include world-renowned car-makers, Czechoslovakia's Municipal Library, Turkish media conglomerate Ciner Media Group, etc.

SMART Modular Technologies, Inc. ("SMART"), a division of SGH and a global leader in memory solutions, solid-state drives, and hybrid storage products announces its SMART Zefr Memory, a proprietary process that eliminates more than 90% of memory reliability failures and optimizes memory subsystems for maximum uptime. System start-up delays are frequently attributed to memory errors. These failures reduce system efficiency and may also lead to higher maintenance costs and lower system yield rates. These failures reduce system efficiency and may also lead to higher maintenance costs and lower system yield rates. SMART Zefr Memory has been tested under real-world conditions to identify and filter out marginal components that may undermine memory reliability.

SMART Zefr Memory uses a proprietary screening process developed by SMART that when performed on memory modules ensures the industry's highest levels of uptime and reliability. SMART Zefr Memory is ideally suited for data centers, hyperscalers, high performance computing (HPC) platforms, and other environments that run large memory applications and depend on uptime for customers.

Chinese company Biren Technology has recently unveiled the Biren BR100 HPC GPU during their Biren Explore Summit 2022 event. The Biren BR100 features an in-house chiplet architecture with 77 billion transistors and is manufactured on a 7 nm process using TSMC's 2.5D CoWoS packaging technology. The card is equipped with 300 MB of onboard cache alongside 64 GB of HBM2E memory running at 2.3 TFLOPs. This combination delivers performance above that of the NVIDIA Ampere A100 achieving 1024 TFLOPs in 16-bit floating point operations.

The company also announced the BR104 which features a monolithic design and should offer approximately half the performance of the BR100 at a TDP of 300 W. The Biren BR104 will be available as a standard PCIe card while the BR100 will come in the form of an OAM compatible board with a custom tower cooler. The pricing and availability information for these cards is currently unknown.