Thanks in part to our readers' comments on the back of the new Realtek 10 Gbps Ethernet solutions, we discovered a company that produces what appears to be the only 5 Gbps Ethernet switches in the entire world and it just so happens that they are attending Computex this week. The company goes under the name of Cirinet or Sirivision in China, but after our chat with them at the show, it appears that Apple has taken an issue with the company name, although it might not matter, since the company is largely an ODM/OEM. The company offers two 5 Gbps switches, both are eight port switches and are built around Realtek hardware.

The product on display at Computex is called the SR-S5G3008 and it's an 8-port managed switch, with the unmanaged model being the SRS5G1008. The SR-S5G3008 is a fully managed L3 switch and rather unusually, the company even claims to offers up its firmware for the switch under GPL terms, so at least in theory, it would be possible to download the source code and compile your own version of it. We did also ask about potential retail pricing and the company suggested a price range in the US$150-200 bracket for the unmanaged version. However, with the advent of the new Realtek 10 Gbps PHY, they expect the price difference between a 5 Gbps and a 10 Gbps version, otherwise identical, since the same switching IC would be used, to be less than US$50 in retail. This suggests that 5 Gbps switches might be dead before they've even hit the market, at least if Realtek delivers on their power consumption figures, as both options could be fanless, an advantage these two 5 Gbps switches have over 10 Gbps switches today.

AMD is already looking ahead to its Zen 7 generation and is planning the final details for its next generation of Zen IP. The first hints come from YouTuber "Moore's Law Is Dead," which points to a few interesting decisions. AMD plans to extend its multi‑class core strategy that began with Zen 4c and continued into Zen 5. Zen 7 will reportedly include three types of cores: the familiar performance cores, dense cores built for maximum throughput, and a new low‑power variant aimed at energy‑efficient tasks, just like Intel and its LP/E-Cores. There is even an unspecified "PT" and "3D" core. By swapping out pipeline modules and tweaking their internal libraries, AMD can fine‑tune each core so it performs best in its intended role, from running virtual machines in the cloud to handling AI workloads at the network edge.

On the manufacturing front, Zen 7 compute chiplets (CCDs) are expected to be made on TSMC's A14 process, which will now include a backside power delivery network. This was initially slated for the N2 node but got shifted to the A16/A14 line. The 3D V‑Cache SRAM chiplets underneath the CCDs will remain on TSMC's N4 node. It is a conservative choice, since TSMC has talked up using N2‑based chiplets for stacked memory in advanced packaging, but AMD appears to be playing it safe. Cache sizes should grow, too. Each core will get 2 MB of L2 cache instead of the current 1 MB, and L3 cache per core could expand to 7 MB through stacked V‑Cache slices. Standard CCDs without V‑Cache will still have around 32 MB of shared L3. A bold rumor suggests an EPYC model could feature 33 cores per CCD, totaling 264 cores across eight CCDs. Zen 7 tape‑out is planned for late 2026 or early 2027, and we probably won't see products on shelves until 2028 or later. As always with early-stage plans, take these details with a healthy dose of skepticism. The final Zen 7 lineup could look quite different once AMD locks down its roadmap.

Die shots of Intel's "Arrow Lake" desktop processors have appeared online, confirming the chiplet design we have known about since the launch. The images annotated by the YouTube channel HighYield show a four‑tile arrangement mounted on a base die made with Intel's 22 nm FinFET process. The compute tile sits at the top left, built on TSMC's N3B node and covering 117.24 mm². To its right are the SoC tile on TSMC's N6 node measuring 86.65 mm², and the GPU tile, which houses four Xe cores alongside an Arc Alchemist render slice. The I/O tile, at 24.48 mm² on the same N6 node, completes the group at the bottom left. Intel has redesigned its hybrid core layout for Arrow Lake, moving away from separate P‑core and E‑core clusters. Four of the eight high‑performance P‑cores line the die's outer edges, with the remaining four in the center. In between these lie the four efficiency E‑core clusters, each sharing 3 MB of L2 cache. A unified 36 MB L3 cache ring bus connects to every core, allowing E‑cores to tap into that larger cache pool for the first time. Intel aims to spread heat more evenly and boost background task performance.

The I/O tile integrates Thunderbolt 4 controllers, PCIe buffers and PHYs. The SoC tile carries display engines, media accelerators and DDR5 memory controllers. All tiles are bonded to the base die via Intel's Foveros Omni stacking technology. Arrow Lake also reflects a shift in Intel's manufacturing strategy. Plans to use Intel's 20A node were dropped in favor of TSMC processes, making this the first desktop CPU from Intel that relies almost entirely on external foundries. On the software side, Intel has begun offering its IPO profiles in select prebuilt systems. These presets optimize CPU and memory settings for a hassle‑free performance boost that remains within warranty limits. Meanwhile, the native 200S Boost overclocking option is rolling out via BIOS updates. Early tests suggest that 200S Boost alone yields modest gains unless paired with very high-speed DDR5 modules, while IPO profiles deliver more consistent improvements with mainstream memory configurations.

AMD has confirmed pricing and launch for its newest Ryzen 9000X3D series processors, with the flagship 9950X3D priced at approximately 5599 RMB and the 9900X3D at 4599 RMB, according to preliminary Chinese store JD listings. Both processors will hit retail channels on March 12, with review embargoes reportedly lifting one day prior, as noted by VideoCardz. The Ryzen 9 9950X3D delivers 16 Zen 5 cores with boost frequencies reaching 5.7 GHz and operates within a 170 W TDP envelope. Its unique feature is 144 MB of combined cache memory (L2, L3, and stacked 3D V-Cache).

The 9900X3D scales back to 12 cores with 5.5 GHz peak frequencies and 140 MB total cache while reducing power consumption to 120 W TDP. These processors represent AMD's implementation of vertical cache stacking technology on its 12+ core Zen 5 setup, completing its Q1 2025 desktop portfolio expansion following earlier standard Ryzen 9000 series launches and the eight-core Ryzen 7 9800X3D. The 3D V-Cache technology could help with many workloads, with gaming performance expected to show the most significant gains and productivity expected to follow. We have to wait for official reviews to bring further conclusions, but we hope to hear official confirmation on availability soon.

QNAP Systems, Inc., a leading computing, networking, and storage solutions innovator, today released its first full 10GbE L3 Lite managed switch, QSW-M3224-24T. Featuring twenty-four 10G Multi-Gig ports, L3 Lite management capabilities and MC-LAG network redundancy, QSW-M3224-24T assists enterprises in deploying stable and efficient mid to large-scale high-speed network infrastructure, accelerating 4K video streaming and AV-over-IP applications.

"As enterprises grow in scale and the number of networked devices increases, the demand for switches also escalates, making the management of large network infrastructure more complex and challenging." said Jerry Deng, Product Manager of QNAP, adding "as QNAP's first L3 managed switch offering multi-port 10GbE networking and advanced L3 management features, QSW-M3224-24T not only fulfills the needs of low-latency and high-density 10G network applications, but also supports advanced IP routing and network segmentation management. QSW-M3224-24T is ideal for small and medium-sized enterprises to expand their LAN efficiently and securely within a limited budget."

AMD is preparing to release its next generation of high-performance CPUs, the Ryzen 9000X3D series, and rumors are circulating about potential increases in stacked L3 cache. However, a recent report from Wccftech suggests that the upcoming models will maintain the same 64 MB of additional 3D V-cache as their predecessors. The X3D moniker represents AMD's 3D V-Cache technology, which vertically stacks an extra L3 cache on top of one CPU chiplet. This design has proven particularly effective in enhancing gaming performance, leading AMD to market these processors as the "ultimate gaming" solutions. According to the latest information, the potential Ryzen 9 9950X3D would feature 16 Zen 5 cores with a total of 128 (64+64) MB L3 cache, while a Ryzen 9 9900X3D would offer 12 cores with the same cache capacity. The Ryzen 7 9800X3D is expected to provide 96 (32+64) MB of total L3 cache.

Regarding L2, the CPUs feature one MB of L2 cache per core. Perhaps the most exciting development for overclockers is the reported inclusion of full overclocking support in the new X3D series. This marks a significant evolution from the limited options available in previous generations, potentially allowing enthusiasts to push these gaming-focused chips to new heights of performance. While the release date for the Ryzen 9000X3D series remains unconfirmed, industry speculation suggests a launch window as early as September or October. This timing would coincide with the release of new X870 (E) chipset motherboards. PC enthusiasts would potentially wait to match the next-gen CPU and motherboards, so this should be a significant upgrade cycle for many.