At Computex, Realtek was showing off a new 5 Gbps switch platform which is set to bring much more affordable high-speed Ethernet switches to the consumer market. At the core of the new switch platform sits Realtek's RTL9303 which is an eight port 10 Gbps switch controller. This was released a few years ago as a low cost 10 Gbps switch IC, but as it still required third party PHYs, it never really took off. The RTL9303 is built around an 800 MHz MIPS 34Kc CPU and supports up to 1 GB of DDR3 RAM as well as 64 MB of SPI NOR Flash for the firmware.

When combined with Realtek's RTL8251B 5 Gbps PHY, the end result is a comparably low-cost 5 Gbps switch. According to Ananadtech, Realtek is expecting a US$25 price per port, which is only about $10 more per port than your typical 2.5 Gbps switch today, even though some are as little as US$10 per port. When combined with a Realtek RTL8126 PCIe based 5 Gbps NIC which retails from around US$30, 5 Gbps Ethernet looks like a very sensible option in terms of price/performance. Admittedly 2.5 Gbps Ethernet cards can be had for as little as $13, but they started out at a higher price point compared to what 5 Gbps NICs are already selling for. Meanwhile, 10 Gbps NICs are still stuck at around US$80-90, with switches in most cases costing at least US$45 per port, but often a lot more. 5 Gbps Ethernet also has the advantage of being able to operate on CAT 5e cabling at up to 60 metres and CAT 6 cabling at up 100 metres, which means there's no need to replace older cabling to benefit from it.

MIPS, a leading developer of efficient and configurable IP compute cores, will showcase the company's latest innovations and suite of system deployments at Computex 2024. As part of its activities at Computex 2024, MIPS will highlight its latest solutions demonstrating the company's differentiation around data movement to enable customers to achieve Edge AI innovation. MIPS' architecture enables a bespoke solution with tight integration of the CPU to the overall System-on-Chip (SoC) architecture, managing data movement and memory balancing to predict and solve bottlenecks caused by the increasing throughput demands of new use-cases in AI.

"We are excited to participate in Computex 2024 where we will show how we've evolved as a company and are developing RISC-V tools that give edge AI Embedded customers the freedom to innovate compute," said Durgesh Srivastava, CTO of MIPS. "We remain committed to providing our customers and partners with the innovative solutions they need to succeed in today's rapidly evolving accelerated computing markets. We are anticipating a lot of interest in our technology at the show and look forward to connecting with ecosystem partners, our customers and fellow industry leaders."

MIPS, a leading developer of efficient and configurable IP compute cores, today announced that it has expanded its collaboration with Synopsys, Inc. to accelerate ecosystem enablement of MIPS RISC-V IP and their customer's ability to innovate compute without constraints. MIPS will showcase MIPS' RISC-V IP Core technology utilizing the Synopsys ImperasFPM Fast Processor Models and the Synopsys ImperasPDK Processor Development Kit software simulation tools at embedded world 2024.

The MIPS RISC-V P8700 IP featured in the demo at embedded world, is a versatile processor, available in scalable multicore configurations, capable of running Linux and other high-level operating systems (HLOS) and is suitable for a variety of automotive (and non-automotive) applications. As a key benefit, customers using the Synopsys ImperasFPM and ImperasPDK fast simulation solution can get started early with software development for the MIPS P8700 and I8500.

MIPS, a leading developer of efficient and configurable compute cores, today announced the company's global expansion with the launch of a new R&D center in Austin, TX, making this the second office expansion in Texas after Dallas. MIPS plans to tap into the growing AI engineering talent in Texas and continue to build deeper roots in the community by partnering with local universities and schools. In addition to creating new job opportunities within the local community, each location will support MIPS' RISC-V research and development efforts, while furthering the company's strategic focus on giving customers the freedom to innovate compute in the AI-centric automotive, data center and embedded markets.

"MIPS' global expansion marks a strategic step forward in the company's growth, especially given our focus on AI and the wide and diverse talent available in the cities where we operate," said Sameer Wasson, CEO of MIPS. "The acceleration of AI-based processing and rapid adoption of RISC-V is on an upward trajectory as engineers continue to seek solutions that deliver the ability to innovate and design without constraints. We are rapidly growing our team and accelerating product roadmaps to enable AI-based systems with better scalability, low power efficiency, real-time multi-threading processing and enhanced configurability, while reducing customers' time to market."

MIPS, a leading developer of high- performance RISC-V compute IP, has announced embedded systems industry veteran Sameer Wasson as the company's new CEO. Before joining MIPS, Wasson spent 18 years at Texas Instruments (TI), most recently as Vice President, Business Unit (BU) Manager, Processors, where he was responsible for the company's Processor businesses. In that role, Wasson re-established TI as a mainstream microprocessor (MPU) and microcontroller (MCU) supplier for high growth automotive and industrial markets, and established the company's footprint in embedded AI, software defined vehicles, and electrification.

As the new CEO of MIPS, Wasson will further accelerate the company's leadership in the High-Performance RISC-V market as it continues to expand its footprint in Automotive and Enterprise markets.

Russian business news outlet Kommersant has learned from industry figures that prices of natively-designed computer processors have been on the rise since the beginning of 2023. Domestic manufacturers of PC, server and storage systems are requiring greater supplies of CPUs designed by Baikal Electronics and MCST - the publication posits that growing demand and logistical issues have become the root cause of recent climbs in cost - individuals involved in the computer hardware supply chain have suggested that some processor models have doubled in price. Sergey Ovchinnikov, the chief executive of Norsi-Trans (a server and data storage firm) provided comment: "Production of Russian chips at foreign fabs has become more complex, leading to extended logistics chains and, consequently, an increase in the cost of the final component." International trade sanctions have not prevented the arrival of fresh silicon into the region - Ovchinnikov claims that an unnamed foundry is able to supply (likely via proxy) Russian developers with computer processors.

Kommersant's investigation found out that Baikal's BE-T1000 CPU is now sold for roughly $110 (8900 Rubles) at a popular computer hardware e-tailer (ChipDip) in the region. The very basic dual core MIPS32r5 (28 nm) processor was readily available for $50 (3990 rubles) back in 2018, so its price has risen by 220% in recent times. TSMC was contracted as the manufacturer of Baikal's BE-T1000 CPU, and the Taiwanese foundry started producing these SoCs in 2016. A Baikal Electronics representative has denied any involvement in driving up MSRP, and states that it is up to distributors and retail outfits to determine prices. The company suspects that very old stock is being sold at inflated rates - Kommersant was unable to contact anyone at ChipDip for a statement.

Amid the push for technology independence, Chinese companies are pushing out more products to satisfy the need for the rapidly soaring demand for domestic data processing silicon. Today, we have information that Chinese Loongson has launched a 3D5000 CPU with as many as 32 cores. Utilizing chiplet technology, the 3D5000 represents a combination of two 16-core 3C5000 processors based on LA464 cores, based on LoongArch ISA that follows the combination of RISC and MIPS ISA design principles. The new chip features 64 MB of L3 cache, supports eight-channel DDR4-3200 ECC memory achieving 50 GB/s, and has five HyperTransport (HT) 3.0 interfaces. The TDP configuration of the chip is officially 300 Watts; however, normal operation is usually at around 150 Watts, with LA464 cores running at 2 GHz.

Scaling of the new chip goes beyond the chiplet, and pours over into system, as 3D5000 supports 2P and 4P configurations, where a single motherboard can become a system of up to 128 cores. To connect them, Loongson uses a 7A2000 bridge chip that is reportedly 400% faster than the previous solution, although we have no information about the last chip bridge. Based on the LGA-4129 package, the chip size is 75.4x58.5×6.5 mm. Regarding performance, Loongson compares it to the average Arm chip that goes into smartphones and claims that its designs are up to four times faster. In SPEC2006, performance reaches 425 points, while maintaining a single TeraFLOP at dual-precision 64-bit format. On the other hand, the processor was built for security, as the chip has a custom hardware-baked security to prevent Spectre and Meltdown, has an on-package Trusted Platform Module (TPM), and has a secret China-made security algorithm with an embedded custom security module that does encryption and decryption at 5 Gbps.

MIPS, a leading developer of highly scalable RISC processor IP, announced it is working with Intel to accelerate innovation in open computing. As part of this effort, MIPS' eVocore is being incorporated into the new Intel Pathfinder for RISC-V, a platform designed to deliver new capabilities for pre-silicon development. Intel Pathfinder allows new ways for System-on-a-Chip (SoC) architects and system software developers to define new products and pursue pre-silicon software development on RISC-V.

"MIPS is thrilled to be part of the Intel Pathfinder for RISC-V platform, providing high performance cores with support for multi-cluster, multi-core and multi-threading to accelerate innovation," said Desi Banatao, MIPS CEO. "These multiprocessors have unique features and a high level of scalability that make them ideal for compute-intensive tasks across a broad range of markets and applications."

Tachyum Inc. today announced that it has successfully executed the Linux boot process on the field-programmable gate array (FPGA) prototype of its Prodigy Universal Processor, in 2 months after taking delivery of the IO motherboard from manufacturing. This achievement proves the stability of the Prodigy emulation system and allows the company to move forward with additional testing before advancing to tape out.

Tachyum engineers were able to perform the Linux boot, execute a short user-mode program and shutdown the system on the fully functional FPGA emulation system. Not only does this successful test prove that the basic processor is stable, but interrupts, exceptions, timing, and system-mode transitions are, as well. This is a key milestone, which dramatically reduces risk, as booting and running large and complex pieces of software like Linux reliably on the Tachyum FPGA processor prototype shows that verification and hardware stability are past the most difficult turning point, and it is now obvious that verification and testing should successfully complete in the coming months. Designers are now shifting their attention to debug and verification processes, running hundreds of trillions of test cycles over the next few months, and running large scale user mode applications with compatibility testing to get the processor to production quality.

Tachyum Inc. today announced that it is signing early adopter customers for the software emulation system for its Prodigy Universal Processor, customers may begin the process of native software development (i.e. using Prodigy Instruction Set Architecture) and porting applications to run on Prodigy. Prodigy software emulation systems will be available at the end of January 2021.

Customers and partners can use Prodigy's software emulation for evaluation, development and debug, and with it, they can begin to transition existing applications that demand high performance and low power to run optimally on Prodigy processors. Pre-built systems include a Prodigy emulator, native Linux, toolchains, compilers, user mode applications, x86, ARM and RISC-V emulators. Software updates will be issued as needed.

Tachyum Inc. today announced that it has successfully completed a demonstration showing its Prodigy Universal Processor running faster than any other processor, HPC or AI chips, including ones from NVIDIA and Intel. This is the latest of many recent milestones achieved by Tachyum as the company continues its march towards Prodigy's product release next year.

Tachyum demonstrated how its computational operation and the speed of its product design, using an industry-standard Verilog simulation of the actual Prodigy post layout hardware, is the superior solution to current competitive offerings. Not only does Prodigy execute instructions at very high speeds, but Tachyum now has an infrastructure implemented for automatically checking correct results from the Verilog RTL. These automated tests check Verilog output for correctness compared to Tachyum's C-model, which was used to measure performance, and is now the 'Golden Model' for the Verilog hardware simulation to ensure it produces identical, step-by-step results.

Chiplet design of processors is getting more popular due to many improvements and opportunities it offers. Some of the benefits include lower costs as the dies are smaller compared to one monolithic design, while you are theoretically able to stitch as much of the chiplets together as possible. During the ISSCC 2020 conference, CEA-Leti, a French research institute, created a 96 core CPU made from six 3D stacked 16 core chiplets. The chip is created as a demonstration of what this modular approach offers and what are the capabilities of the chiplet-based CPU design.

The chiplets are manufactured on the 28 nm FD-SOI manufacturing process from STMicroelectronics, while the active interposer die below them that is connecting everything is made using the 65 nm process. Each one of the six dies is housing 16 cores based on MIPS Instruction Set Architecture core. Each chiplet is split into four 4-core clusters that make up for a total of 16 cores per chiplet. When it comes to the core itself, it is a scalar MIPS32v1 core equipped with 16 KiB of L1 instruction and an L1 data cache. For L2 cache, there is 256 KiB per cluster, while the L3 cache is split into four 1 MiB tiles for the whole cluster. The chiplets are stacked on top of an active interposer which connects the chiplets and provides external I/O support.

QNAP Systems, Inc. today released the new TS-832X 8-bay quad-core NAS with two built-in 10GbE SFP ports, providing users with a budget-friendly, high-speed network storage solution. It is also an ARM-based NAS that supports Qtier technology for auto-tiering, and its PCIe slots allow for the installation of peripheral cards like 10GbE NICs, QM2 cards, USB 3.1 10Gbps expansion cards, or wireless network cards to enhance the NAS with greater application potential.

"The TS-832X is a step up from the TS-831X, featuring an advanced 64-bit Cortex -A57 processor and DDR4 memory while also delivering computing power of 32K DMIPS to benefit performance upgrade by 40%," said Dan Lin, Product Manager of QNAP, continuing "Coupled with the 10GbE connectivity and PCIe expandability, it provides a highly cost-efficient private cloud NAS solution."

Graphene has been hailed for some time now as the next natural successor to silicon, today's most used medium for semiconductor technology. However, even before such more exotic solutions to current semiconductor technology are employed (and we are still way off that future, at least when it comes to mass production), engineers and researchers seem to be increasing their focus in one specific part of computing: internal communication between components.

Typically, communication between a computer's Central Processing Unit (CPU) and a system's memory (usually DRAM) have occurred through a bus, which is essentially a communication highway between data stored in the DRAM, and the data that the CPU needs to process/has just finished processing. The fastest CPU and RAM is still only as fast as the bus, and recent workloads have been increasing the amount of data to be processed (and thus transferred) by orders of magnitude. As such, engineers have been trying to figure out ways of increasing communication speed between the CPU and the memory subsystem, as it is looking increasingly likely that the next bottlenecks in HPC will come not through lack of CPU speed or memory throughput, but from a bottleneck in communication between those two.

Linksys, a leader in networking solutions for the home and business and the first to ship 100 million routers, today announced, it is shipping its new 802.11ac Tri-Band MU-MIMO Router. The Linksys Max Stream EA8300 is an AC2200 Tri-Band MU-MIMO router priced under $200, giving users MU-MIMO technology and up to double the performance of a dual-band router* for even faster speeds for downloading, streaming, gaming and surfing. Offering MU-MIMO (Multi-User, Multiple-Input, Multiple Output), the next generation Wi-Fi 802.11ac Wave 2 technology, helps improve overall performance and efficiency of a Wi-Fi network while providing dedicated bandwidth to MU-MIMO capable client devices as if they have their own dedicated router. Linksys offers the largest and broadest portfolio of MU-MIMO home Wi-Fi solutions on the market.

According to a white paper by ABI Research The Importance Of MU-MIMO In The Wi-Fi Ecosystem more than 84% of all wireless 5GHz chipsets will be MU-MIMO enabled by 2019. To keep up with the speeds and performance of client devices coming to market such as 4K TVs, laptops, smart phones, tablets and game consoles, consumers will want to make sure they have the latest Wi-Fi router that can support all the latest devices that have come into the home.

IBM (NYSE:IBM) today announced third-quarter 2013 diluted earnings of $3.68 per share, compared with diluted earnings of $3.33 per share in the third-quarter of 2012, an increase of 11 percent. Operating (non-GAAP) diluted earnings were $3.99 per share compared with operating diluted earnings of $3.62 per share in the third-quarter of 2012, an increase of 10 percent.

Third-quarter net income was $4.0 billion compared with $3.8 billion in the third-quarter of 2012, an increase of 6 percent. Operating (non-GAAP) net income was $4.4 billion, as compared with $4.2 billion in the third-quarter of 2012, an increase of 6 percent. Total revenues for the third-quarter of 2013 of $23.7 billion were down 4 percent (down 2 percent, adjusting for currency) from the third-quarter of 2012.

"In the third-quarter we continued to expand operating margins and increased earnings per share, but fell short on revenue. Where we had identified high growth opportunities and pursued them aggressively --- cloud, mobile, business analytics, and security --- we continued to show strong growth. This underscores our strategy to continuously transform the company to high value," said Ginni Rometty, IBM chairman, president and chief executive officer.

ARM today announced that it is a leading member of Bridge Crossing LLC, a consortium of major technology companies affiliated with Allied Security Trust, which has entered into an agreement with MIPS to obtain rights to its patent portfolio. The MIPS patent portfolio includes 580 patents and patent applications covering microprocessor design, system-on-chip design and other related technology fields. The consortium will pay $350 million in cash to acquire rights to the portfolio, of which ARM will contribute $167.5 million.

The transaction will, upon completion, support continued innovation in system-on-chip design, whilst removing any potential litigation risk presented by the MIPS patent portfolio with respect to the consortium members. The consortium will make licenses to the patent portfolio available to companies not within the consortium.

MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multimedia solutions, announced today the world's first 1T1R 802.11ac dual-band concurrent Wi-Fi router and dongle solutions. MT7620 + MT7610E and MT7610U provide the mass market with 1T1R 802.11ac router and dongle to enable high quality data transmission, voice and video applications in connected homes. MediaTek will demonstrate its latest wireless technologies, connectivity devices and applications to its customers during Computex Taipei 2012.

MT7620 family integrates a 2T2R 802.11n Wi-Fi radio, a 600 MHz MIPS 24KEc CPU, 5p FE switch, 2xrGMII, USB, PCIe, SD-HC. The PCI Express interface will connect to 2nd Wi-Fi chipset for 11n 2x2 DBC router or to an 11ac chipset for 1x1 DBC 11ac routers. The high performance USB 2.0 allows MT7620 to add 3G/LTE support on a router or can add a UVC cam to enable the best cost/performance IP-Cam. And to support the wireless storage application, MT7620 supports NAND flash interface, SD-HC, USB 2.0 and storage accelerator for NAS, Wi-Fi HDD and Wi-Fi card reader. Audio interface I2S and PCM will enable wireless speaker and VoIP applications. MT7620 also steps up to the leading Hardware Network Address Translation (HNAT) milestone by supporting 2Gbps wired speed with IPv6 forwarding. The cost effective rGMII iNIC interface (2.4G or dual-band concurrent) can be utilized for cable, PON, xDSL and broadband wireless router.

MediaTek Inc., a leading fabless semiconductor company for wireless communications and digital multimedia solutions, today announced that its Wi-Fi system-on-a-chip (SoC), the RT6856, has been incorporated into D-Link's latest Wi-Fi cloud routers. As a global leader in connectivity, D-Link will be shipping several new cloud routers this spring.

The MediaTek RT6856 Wi-Fi SoC contains a powerful 700 MHz MIPS 34KEc CPU core and dual PCI Express interfaces to simultaneously enable two Wi-Fi streams for "dual band concurrent" home networks providing high quality data, voice and video applications. This powerful SoC allows consumers to create two wireless networks both running at full bandwidth speeds, thus offering a significant increase in total network capacity.

AMD and Google are locked in a race to buy out MIPS, an application processor architecture designer competitive to ARM. AMD comes from a decades old presence in the microprocessor industry, while Google is a satrap with smartphones, tablets, and other mobile computing devices thanks to its Android operating system. With Microsoft opening up to ARM architecture with Windows 8 RT, it is in Google's interests to hedge its bets on an alternative machine architecture to both x86 and ARM. The easiest way to that is buying out MIPS and funding development of powerful processors based on it. For AMD, it's a bid to stay competitive in the low-power processor market as Intel began making inroads to smartphone processor market.