TSMC on Monday kicked off a virtual tech symposium, where it announced its new 12 nm N12e node for IoT edge devices, announced the new 3DFabric Technology, and detailed progress on its upcoming 5 nm N5 and 3 nm N3 silicon fabrication nodes. The company maintains that the N5 (5 nm) node offers the benefits of a full node uplift over its current-gen N7 (7 nm), which recently clocked over 1 billion chips shipped. The N5 node incorporates EUV lithography more extensively than N6/N7+, and in comparison to N7 offers 30% better power at the same performance, 15% more performance at the same power, and an 80% increase in logic density. The company has commenced high-volume manufacturing on this node.

2021 will see the introduction and ramp-up of the N5P node, an enhancement of the 5 nm N5 node, offering a 10% improvement in power at the same performance, or 5% increase in performance at the same power. A nodelet of the N5 family of nodes, called N4, could see risk production in Q4 2021. The N4 node is advertised as "4 nm," although the company didn't get into its iso-power/iso-performance specifics over the N5 node. The next major node for TSMC will be the 3 nm N3 node, with massive 25%-30% improvement in power at the same performance, or 10%-15% improvement in performance at same power, compared to N5. It also offers a 70% logic density gain over N5. 3DFabric technology is a new umbrella term for TSMC's CoWoS (chip on wafer on substrate), CoW (chip on wafer), and WoW (wafer on wafer) 3-D packaging innovations, with which it plans to offer packaging innovations that compete with Intel's various new 3D chip packaging technologies on the anvil.

In a bid to show off its volume production prowess and technological edge (but mostly to rub it in to rival fabs), TSMC on Thursday announced that it shipped its 1 billionth chip fabricated on its 7 nm process. If these dies were combined into one big rectangular wafer, they would cover 13 New York City blocks. TSMC's 7 nm process debuted with its N7 node, which went into volume production in April 2018, over two years ago. The fab has since mass-produced 7 nm chips for the likes of Qualcomm, Apple, and AMD, among dozens of other clients. The company now looks to monetize refinements of N7, namely the N7e and N7P (DUV refinements), while executing its crucial EUV-based N7+ node, leading up to future nodelets such as N6. Much of TSMC's growth will be propelled by 5G modems, application processors, and its pivotal role in the growth of companies such as AMD.

With its own 7 nm-class silicon fabrication node nowhere in sight for its processors, at least not until 2022-23, Intel is seeking out third-party semiconductor foundries to support its ambitious discrete GPU and scalar compute processor lineup under the Xe brand. A Taiwanese newspaper article interpreted by Chiakokhua provides a fascinating insight to the the new precious resource in the high-technology industry - allocation.

TSMC is one of these foundries, and will give Intel access to a refined 7 nm-class node, either the N7P or N7+, for some of its Xe scalar compute processors. The company could also seek out nodelets such as the N6. Trouble is, Intel will be locking horns with the likes of AMD for precious foundry allocation. NVIDIA too has secured a certain allocation of TSMC 7 nm for some of its upcoming "Ampere" GPUs. Sources tell China Times that TSMC will commence mass-production of Intel silicon as early as 2021, on either N7P, N7+, or N6. Business from Intel is timely for TSMC as it is losing orders from HiSilicon (Huawei) in wake of the prevailing geopolitical climate.

TSMC is reportedly planning a stopgap between its 5 nm-class silicon fabrication nodes, and the 3 nm-class, called N4. According to the foundry's CEO, Liu Deyin, speaking at a shareholders meeting, N4 will be a 4 nm node, and an enhancement of N5P, the company's most advanced 5 nm-class node. N4 is slated for mass-production of contracted products in 2023, and could help TSMC's customers execute their product roadmaps of the time. From the looks of it, N4 is a repeat of the N6 story: a nodelet that's an enhancement of N7+, the company's most advanced 7 nm-class node that leverages EUV lithography.

AMD's RDNA2 graphics architecture, which sees real-time ray-tracing among other DirectX 12 Ultimate features, could see the company double the amount of stream processors generation-over-generation, according to a specs leak by _rogame. The increase in stream processors would fall in line with AMD's effort to increase performance/Watt by 50%. It may appear like the resulting SKUs finally measure up to the likes of the RTX 2080 Ti, but AMD has GeForce "Ampere" in its competitive calculus, and should the recent specs reveal hold up, the new "Navi 21" could end up being a performance-segment competitor to GeForce graphics cards based on the "GA104" ("TU104" successor), rather than a flagship-killer.

The RDNA2-based "Navi 21" GPU allegedly features 80 RDNA2 compute units amounting to 5,120 stream processors. AMD might tap into a refined 7 nm-class silicon fabrication node by TSMC to build these chips, either N7P or N7+. The die-size could measure up to 505 mm², and AMD could aim for a 50% performance/Watt gain over the "Navi 10." AMD could carve out as many as 10 SKUs out of the "Navi 21," but only three are relevant to the gamers. The SKU with the PCI device ID "0x731F: D1" succeeds the RX 5700 XT. The one bearing "0x731F: D3" succeeds the RX 5700, with a variant name "Navi 21 XL." The "Navi 21 XE" variant has a PCI ID of "0x731F: DF," and succeeds the RX 5600 XT.

The bulk of AMD's 4th generation Ryzen desktop processors will comprise of "Vermeer," a high core-count socket AM4 processor and successor to the current-generation "Matisse." These chips combine up to two "Zen 3" CCDs with a cIOD (client I/O controller die). While the maximum core count of each chiplet isn't known, they will implement the "Zen 3" microarchitecture, which reportedly does away with CCX to get all cores on the CCD to share a single large L3 cache, this is expected to bring about improved inter-core latencies. AMD's generational IPC uplifting efforts could also include improving bandwidth between the various on-die components (something we saw signs of in the "Zen 2" based "Renoir"). The company is also expected to leverage a newer 7 nm-class silicon fabrication node at TSMC (either N7P or N7+), to increase clock speeds - or so we thought.

An Igor's Lab report points to the possibility of AMD gunning for efficiency, by letting the IPC gains handle the bulk of Vermeer's competitiveness against Intel's offerings, not clock-speeds. The report decodes OPNs (ordering part numbers) of two upcoming Vermeer parts, one 8-core and the other 16-core. While the 8-core part has some generational clock speed increases (by around 200 MHz on the base clock), the 16-core part has lower max boost clock speeds than the 3950X. Then again, the OPNs reference A0 revision, which could mean that these are engineering samples that will help AMD's ecosystem partners to build their products around these processors (think motherboard- or memory vendors), and that the retail product could come with higher clock speeds after all. We'll find out in September, when AMD is expected to debut its 4th generation Ryzen desktop processor family, around the same time NVIDIA launches GeForce "Ampere."

A DigiTimes premium report, interpreted by Chiakokhua, aka Retired Engineer, chronicling NVIDIA's move to contract TSMC for 7 nm and 5 nm EUV nodes for GPU manufacturing, made a startling revelation about NVIDIA's recent foundry diversification moves. Back in July 2019, a leading Korean publication confirmed NVIDIA's decision to contract Samsung for its next-generation GPU manufacturing. This was a week before AMD announced its first new-generation 7 nm products built for the TSMC N7 node, "Navi" and "Zen 2." The DigiTimes report reveals that NVIDIA underestimated the efficiency gains AMD would yield from TSMC N7.

With NVIDIA's bonhomie with Samsung underway, and Apple transitioning to TSMC N5, AMD moved in to quickly grab 7 nm-class foundry allocation and gained prominence with the Taiwanese foundry. The report also calls out a possible strategic error on NVIDIA's part. Upon realizing the efficiency gains AMD managed, NVIDIA decided to bet on TSMC again (apparently without withdrawing from its partnership with Samsung), only to find that AMD had secured a big chunk of its nodal allocation needed to support its growth in the x86 processor and discrete GPU markets. NVIDIA has hence decided to leapfrog AMD by adapting its next-generation graphics architectures to TSMC's EUV nodes, namely the N7+ and N5. The report also speaks of NVIDIA using its Samsung foundry allocation as a bargaining chip in price negotiations with TSMC, but with limited success as TSMC established its 7 nm-class industry leadership. As it stands now, NVIDIA may manufacture its 7 nm-class and 5 nm-class GPUs on both TSMC and Samsung.

TSMC vice chairman and CEO C.C. Wei announced the company's plans for 5 nm are on track, which means High Volume manufacturing (HVM) on the node is expected to be achieved by 2Q 2020. The company has increased expenditures in ramping up its various nodes from an initially projected $10 billion to something along the lines of $14 billion - 15 billion; the company is really banking on quick uptake and design wins on its most modern process technologies - and the increased demand that follows.

TSMC's 5 nm process (N5) will use extreme ultraviolet lithography (EUVL) in many more layers than its N7+ and N6 processes, with up to 14 layers being etched in the N5 silicon compared to five and six, respectively, for its "older" N7+ and N6 processes. As the company increases capital expenditure in acquiring EUVL-capable equipment that sets up its production nodes for the market they foresee will just gobble up the chips in 2020, the company is optimistic they can achieve growth in the 5-10% number.

TSMC today announced that its seven-nanometer plus (N7+), the industry's first commercially available Extreme Ultraviolet (EUV) lithography technology, is delivering customer products to market in high volume. The N7+ process with EUV technology is built on TSMC's successful 7 nm node and paves the way for 6 nm and more advanced technologies.

The N7+ volume production is one of the fastest on record. N7+, which began volume production in the second quarter of 2019, is matching yields similar to the original N7 process that has been in volume production for more than one year.

TSMC is on the vanguard of chipset fabrication technology at this exact point in time - its 7 nm technology is the leading-edge of all large volume processes, and is being tapped by a number of companies for 7 nm silicon. One of its most relevant clients for our purposes, of course, is AMD - the company now enjoys a fabrication process lead over arch-rival Intel much due to its strategy of fabrication spin-off and becoming a fabless designer of chips. AMD's current product stack has made waves in the market by taking advantage of 7 nm's benefits, but it seems this may actually become a slight problem in the not so distant future.

TSMC has announced a threefold increase in its delivery lead times for 7 nm orders, from two months to nearly six months, which means that orders will now have to wait three times longer to be fulfilled than they once did. This means that current channel supplies and orders made after the decision from TSMC will take longer to materialize in actual silicon, which may lead to availability slumps should demand increase or maintain. AMD has its entire modern product stack built under the 7 nm process, so this could potentially affect both CPUs and GPUs from the company - and let's not forget AMD's Zen 3 and next-gen RDNA GPUs which are all being designed for the 7 nm+ process node. TSMC is expected to set aside further budget to expand capacity of its most advanced nodes, whilst accelerating investment on their N7+, N6, N5, and N3 nodes.

TSMC in its quarterly earnings call expressed confidence in that most of its 7 nm (N7) process production node customers would be looking to make the transition to their 6 nm (N6) process. In fact, the company expects that node to become the biggest target for volume ordering (and thus production) amongst its customers, since the new N6 fabrication technology will bring about a sort of "backwards compatibility" with design tools and semiconductor designs that manufacturers have already invested in for its N7 node, thus allowing for cost savings for its clients.

This is despite TSMC's N6 process being able to take advantage of extreme ultraviolet lithography (EUVL) to lower manufacturing complexity. This lowering is achieved by the fact that less exposures of the silicon are required for multi-patterning - which is needed today as TSMC's N7 uses solely deep ultraviolet (DUV) lithography. Interestingly, TSMC expects other clients to pick up its N7+ manufacturing node that aren't already using their 7nm node - the need to develop new tools and lesser design compatibility between its N7 and N7+ nodes compared no N7 and N6 being the justification. TSMC's N7+ will be the first node to leverage EUV, using up to four EUVL layers, while N6 expands it up to five layers, and the upcoming N5 cranks EUVL up to fourteen (allowing for 14 layers.)