Global Unichip Corp. (GUC), the Advanced ASIC Leader, today announced the successful launch of industry's first Universal Chiplet Interconnect Express (UCIe) PHY silicon, achieving a data rate of 32 Gbps per lane, the highest speed defined in the UCIe specification. The 32G UCIe IP, supporting UCIe 2.0, delivers an impressive bandwidth density of 10 Tbps per 1 mm of die edge (5 Tbps/mm full-duplex). This milestone was achieved using TSMC's advanced N3P process and CoWoS packaging technologies, targeting AI, high-performance computing (HPC), xPU, and networking applications.

In this test chip, several dies with North-South and East-West IP orientations are interconnected through CoWoS interposer. The silicon measurements show robust 32 Gbps operation with wide horizontal and vertical eye openings. GUC is working aggressively on the full-corner qualification, and the complete silicon report is expected to be available in the coming quarter.

Blue Cheetah Analog Design today announced the successful tape-outs of its next generation BlueLynx die-to-die (D2D) PHY on Samsung Foundry's SF4X 4 nm advanced manufacturing process. The latest PHY supports both advanced and standard chiplet packaging with an aggregate throughput exceeding 100 Tbps while achieving industry-leading silicon area footprint and power consumption. BlueLynx D2D subsystem IP enables chip architects to meet the bandwidth density and environmental robustness necessary to ensure production deployment success while preserving use case flexibility.

Using Samsung Foundry's SF4X 4 nm advanced process, the latest BlueLynx PHY supports both standard 2D and advanced 2.5D packages and enables system designers to seamlessly change packaging technologies in current and future implementations. Customer deliveries started in 2024 with silicon characterization in both advanced and standard packaging applications expected in early Q2 2025.

Alphawave Semi (LSE: AWE), a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, proudly introduces the industry's first 64 Gbps Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP Subsystem to deliver unprecedented chiplet interconnect data rates, setting a new standard for ultra-high-performance D2D connectivity solutions in the industry. The third generation, 64 Gbps IP Subsystem builds on the successes of the most recent Gen 2 36 Gbps IP subsystem and silicon-proven Gen 1 24 Gbps and is available in TSMC's 3 nm Technology for both Standard and Advanced packaging. The silicon proven success and tapeout milestones pave the way for Alphawave Semi's Gen 3 UCIe IP subsystem offering.

Alphawave Semi is set to revolutionize connectivity with its Gen 3 64 Gbps UCIe IP, delivering a bandwidth density of over 20 Tbps/mm, with ultra-low power and latency. This solution is highly configurable supporting multiple protocols, including AXI-4, AXI-S, CXS, CHI and CHI-C2C to address the growing demands for high-performance connectivity across disaggregated systems in High-Performance Computing (HPC), Data Centers, and Artificial Intelligence (AI) applications.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today revealed the successful delivery of first silicon for its NuLink -2.0 PHY, manufactured in a 3 nm process. The device achieves 64 Gbps/bump, the industry's highest performance for a die-to-die PHY solution for multi-die architectures. While compatible with UCIe standard, the milestone further confirms Eliyan's ability to extend die-to-die connectivity by 2x higher bandwidth, on standard as well as advanced packaging, at unprecedented power, area, and latency.

The NuLink-2.0 is a multi-mode PHY solution that also supports UMI (Universal Memory Interconnect), a novel chiplet interconnect technology that improves Die-to-Memory bandwidth efficiency by more than 2x. UMI leverages a dynamic bidirectional PHY whose specifications are currently being finalized with the Open Compute Project (OCP) as BoW 2.1.

OPENEDGES Technology, Inc., the leading provider of memory subsystem intellectual property (IP), today announced the launch of the Universal Chiplet Interconnect Express (UCIe) Controller IP, named OUC. UCIe is an open industry standard for a die-to-die interconnect, and co-developed by industry giants including AMD, Arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, Qualcomm, and Samsung. UCIe is becoming a new trend in the semiconductor industry due to its advantages, such as increased semiconductor circuit integration, reduced production costs, and higher yields. OPENEDGES is contributing to UCIe consortium as a contributing member.

The OUC, deriving its name from OPENEDGES UCIe Controller, is tailored for highly customizable, package-level integration, facilitating die-to-die interconnect and protocol connections. It creates an interoperable, multi-vendor ecosystem set to revolutionize chip integration methodologies across the industry.

Today the Universal Chiplet Interconnect Express (UCIe) Consortium announced the release of its 2.0 Specification. The UCIe 2.0 Specification adds support for a standardized system architecture for manageability and holistically addresses the design challenges for testability, manageability, and debug (DFx) for the SIP lifecycle across multiple chiplets - from sort to management in the field. The introduction of optional manageability features and a UCIe DFx Architecture (UDA), which includes a management fabric within each chiplet for testing, telemetry, and debug functions, allows vendor agnostic chiplet interoperability across a flexible and a unified approach to SIP management and DFx operations.

Additionally, the 2.0 Specification supports 3D packaging - offering higher bandwidth density and improved power efficiency compared to 2D and 2.5D architectures. UCIe-3D is optimized for hybrid bonding with a bump pitch functional for bump pitches as big as 10-25 microns to as small as 1 micron or less to provide flexibility and scalability.

Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world's technology infrastructure, has launched the industry's first 3 nm successful silicon bring-up of Universal Chiplet Interconnect Express (UCIe) Die-to-Die (D2D) IP with TSMC's Chip-on-Wafer-on-Substrate (CoWoS) advanced packaging technology.

The complete PHY and Controller subsystem was developed in collaboration with TSMC and targets applications such as hyperscaler, high-performance computing (HPC) and artificial intelligence (AI).

Synopsys, Inc. today announced it is extending its collaboration with TSMC to advance multi-die system designs with a comprehensive solution supporting the latest 3Dblox 2.0 standard and TSMC's 3DFabric technologies. The Synopsys Multi-Die System solution includes 3DIC Compiler, a unified exploration-to-signoff platform that delivers the highest levels of design efficiency for capacity and performance. In addition, Synopsys has achieved first-pass silicon success of its Universal Chiplet Interconnect Express (UCIe) IP on TSMC's leading N3E process for seamless die-to-die connectivity.

"TSMC has been working closely with Synopsys to deliver differentiated solutions that address designers' most complex challenges from early architecture to manufacturing," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our long history of collaboration with Synopsys benefits our mutual customers with optimized solutions for performance and power efficiency to help them address multi-die system design requirements for high-performance computing, data center, and automotive applications."

Today, the UCIe Consortium announced the public release of UCIe (Universal Chiplet Interconnect Express ) 1.1 Specification to deliver valuable improvements in the chiplet ecosystem, extending reliability mechanisms to more protocols and supporting broader usage models. Additional enhancements are included for automotive usages - such as predictive failure analysis and health monitoring - and enabling lower-cost packaging implementations. The specification also details architectural specification attributes to define system setups and registers that will be used in test plans and compliance testing to ensure device interoperability. The UCIe 1.1 Specification is fully backward compatible with the UCIe 1.0 Specification.

"UCIe Consortium is living up to its mission and establishing a vibrant chiplet ecosystem as the industry musters around UCIe technology," said Dr. Debendra Das Sharma, chairman, UCIe Consortium. "The UCIe 1.1 Specification was developed by leaders in the industry to advance the chiplet ecosystem and address significant demand for full stack streaming protocol enhancements. We're proud of the progress this release represents toward realizing our vision and our underlying efforts to establish a chiplet ecosystem by developing a robust compliance program."

Accelerating the integration of heterogeneous dies to enable the next level of system scalability and functionality, Synopsys, Inc. (Nasdaq: SNPS) has strengthened its collaboration with TSMC and Ansys for multi-die system design and manufacturing. Synopsys provides the industry's most comprehensive EDA and IP solutions for multi-die systems on TSMC's advanced 7 nm, 5 nm and 3 nm process technologies with support for TSMC 3DFabric technologies and 3Dblox standard. The integration of Synopsys implementation and signoff solutions and Ansys multi-physics analysis technology on TSMC processes allows designers to tackle the biggest challenges of multi-die systems, from early exploration to architecture design with signoff power, signal and thermal integrity analysis.

"Multi-die systems provide a way forward to achieve reduced power and area and higher performance, opening the door to a new era of innovation at the system-level," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "Our long-standing collaboration with Open Innovation Platform (OIP) ecosystem partners like Synopsys and Ansys gives mutual customers a faster path to multi-die system success through a full spectrum of best-in-class EDA and IP solutions optimized for our most advanced technologies."

Tachyum announced today it has strengthened its presence in the Universal Chiplet Interconnect Express (UCIe) organization that develops and supports the chiplet ecosystem and in-package innovations. The UCIe community fosters collaboration among leaders in semiconductors, packaging, IP suppliers, foundries, and cloud services.

UCIe 1.0 is an open specification guiding the interconnection between chiplets within a package to ensure communication and functionality. Chiplet-based design increases density and capability compared to standard printed circuit-boards (PCBs), and enables much smaller, lower-cost solutions that consume less power. UCIe specification addresses the die-to-die I/O physical layer, die-to-die protocols, and software stack currently served by PCI Express (PCIe) and Compute Express Link (CXL) industry standards. UCIe ultimately extends the PCIe standard to in-package interconnects and allows the potential to bring CXL into in-package integration.

Winbond has joined the UCIe (Universal Chiplet Interconnect Express) Consortium, the industry Consortium dedicated to advancing UCIe technology. This open industry standard defines interconnect between chiplets within a package, enabling an open chiplet ecosystem and facilitating the development of advanced 2.5D/3D devices.

A leader in high-performance memory ICs, Winbond is an established supplier of known good die (KGD) needed to assure end-of-line yield in 2.5D/3D assembly. 2.5D/3D multichip devices are needed to realize the exponential improvements in performance, power efficiency, and miniaturization, demanded by the explosion of technologies such as 5G, Automotive, and Artificial Intelligence (AI).

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.

Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.

Enabling a new generation of system-level integration in data centers, NVIDIA today announced NVIDIA NVLink -C2C, an ultra-fast chip-to-chip and die-to-die interconnect that will allow custom dies to coherently interconnect to the company's GPUs, CPUs, DPUs, NICs and SOCs. With advanced packaging, NVIDIA NVLink-C2C interconnect would deliver up to 25x more energy efficiency and be 90x more area-efficient than PCIe Gen 5 on NVIDIA chips and enable coherent interconnect bandwidth of 900 gigabytes per second or higher.

"Chiplets and heterogeneous computing are necessary to counter the slowing of Moore's law," said Ian Buck, vice president of Hyperscale Computing at NVIDIA. "We've used our world-class expertise in high-speed interconnects to build uniform, open technology that will help our GPUs, DPUs, NICs, CPUs and SoCs create a new class of integrated products built via chiplets."

Intel, along with Advanced Semiconductor Engineering Inc. (ASE), AMD, Arm, Google Cloud, Meta, Microsoft Corp., Qualcomm Inc., Samsung and Taiwan Semiconductor Manufacturing Co., have announced the establishment of an industry consortium to promote an open die-to-die interconnect standard called Universal Chiplet Interconnect Express (UCIe). Building on its work on the open Advanced Interface Bus (AIB), Intel developed the UCIe standard and donated it to the group of founding members as an open specification that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level.

"Integrating multiple chiplets in a package to deliver product innovation across market segments is the future of the semiconductor industry and a pillar of Intel's IDM 2.0 strategy," said Sandra Rivera, executive vice president and general manager of the Datacenter and Artificial Intelligence Group at Intel. "Critical to this future is an open chiplet ecosystem with key industry partners working together under the UCIe Consortium toward a common goal of transforming the way the industry delivers new products and continues to deliver on the promise of Moore's Law."