The desktop version of AMD's next-generation "Zen 6" microarchitecture will retain Socket AM5, Kepler_L2, a reliable source with hardware leaks, revealed. What's more interesting is the rumor that the current "Zen 5" will remain AMD's mainstay for the entirety of 2025, and possibly even most of 2026, at least for the desktop platform. AMD will be banking heavily on the recently announced Ryzen 7 9800X3D, and its high core-count siblings, the Ryzen 9 9950X3D and possible 9900X3D, to see the company through for 2025 against Intel. The 9800X3D posted significantly higher gaming performance than Intel, and the 9950X3D is expected to be at least faster than the 7950X3D at gaming, which means its gaming performance, coupled with multithreaded application performance from its 16-core/32-thread count should be the face of AMD's desktop processor lineup for at least the next year.

It wouldn't be off-character for AMD to launch "Zen 6" on AM5, and not refresh the platform. The company had launched three microarchitectures (Zen thru Zen 3) on Socket AM4. With "Zen 6," AMD has the opportunity to not just increase IPC, but also core-counts per CCD, cache sizes, a new foundry node such as 3 nm, and probably even introduce features such as hybrid architecture and an NPU to the desktop platform, which means it could at least update the current 6 nm client I/O die (cIOD) while retaining AM5. A new cIOD could give AMD the much-needed opportunity to update the DDR5 memory controllers to support higher memory frequencies. The Kepler_L2 leak predicts a "late-2026 or early-2027" launch for desktop "Zen 6" processors. In the meantime, Intel is expected to ramp "Arrow Lake-S" on Socket LGA1851, and debut the "Panther Lake" microarchitecture on LGA1851 in 2025-26.

OpenSIL is an open-source CPU initialization framework project that seeks to replace on-chip initialization microcode, such as AGESA, across both client- and server processors. AMD looks to implement OpenSIL as it makes its AMD EPYC processors more friendly to large customers that want to take control of this aspect of the processor. Since its open-sourcing in June 2023, AMD has come up with reference motherboards implementing OpenSIL, as well as modifying a Supermicro server motherboard to the architecture, to demo at conferences. AMD firmware engineer Paul Grimes presented the company's progress with implementing OpenSIL, at the OSFC conference, in Germany. It's been known that AMD is targeting a 2025-26 timeline for OpenSIL to hit product, but AMD put out specifics, such as its next-generation "Venice" server processor supporting OpenSIL.

"Venice" is codename for an AMD EPYC server processor generation succeeding "Turin." It is built on the future "Zen 6" microarchitecture, and AMD could at least unveil the processor some time in 2025, if not mass-produce it. late-2024 thru 2025 could see the company ramp up "Turin" and other server processors implementing "Zen 5." That's not all, AMD plans to being OpenSIL even to client processors, with the generation of Ryzen processors based on "Zen 6." This will see the AGESA microcode replaced by a first-party firmware from AMD based on OpenSIL, which PC OEMs will be able to customize. The biggest impact of this change will be felt in the commercial notebook and commercial desktop segments, where large organizations can take greater control over the chip initialization firmware.

AMD's future "Zen 6" CPU microarchitecture is rumored to cram up to 32 cores per CCD (CPU complex die), or the common client/server chiplet with the CPU cores, according to Kepler_L2, a reliable source with hardware leaks. At this point it's not clear if they are referring to the regular "Zen 6" CPU core, or the physically compacted "Zen 6c" core meant for high core-count cloud server processors. The current pure "Zen 4c" CCD found in EPYC "Bergamo" processor packs 16 cores across two 8-core CCX (CPU core complexes) that share a 16 MB L3 cache among the 8 cores within the CCX. The upcoming "Zen 5c" CCD will pack 16 cores, but in a single 16-core CCX that shares 32 MB of L3 cache among the 16 cores for improved per-core cache access. "Zen 6" is expected to double this to 32 cores per CCD.

The 32-core CCD powered by "Zen 6" (likely Zen 6c), might take advantage of process improvements to double the core-count. At this point, it's not clear if this jumbo CCD features a single large CCX with all 32 cores sharing a large L3 cache; or if it's using two 16-core CCX that shares, say, 32 MB of L3 cache among the 16 cores. What's clear with this leak, though, is that AMD is looking to continue ramping up CPU core counts per socket. Data-centers and cloud customers seem to love this, and AMD is the only x86 processor maker in a serious competition with Arm-based server processor manufacturers such as Ampere, to increase significantly increase core counts per socket with each generation.

Some of the earliest signs are emerging that AMD's mobile processor or desktop APU silicon that succeeds "Strix Point" being codenamed "Sound Wave." AMD tends to come up with quirky internal codenames for upcoming projects, mostly to zero in on the source of leaks, so "Sound Wave" as a codename is subject to change with time. While the upcoming 4 nm "Strix Point" and "Strix Halo" chips implement the "Zen 5" CPU microarchitecture and RDNA 3+ graphics architecture, besides XDNA 2 based NPU with a generational tripling in AI TOPS; Wccftech believes that "Sound Wave" could be an AMD processor of comparable class to "Strix Point," which implements the "Zen 6" CPU microarchitecture, which AMD has planned for a 2025-26 timeframe.

Perhaps the most interesting aspect of this leak is the foundry node, with the original source over at Korean tech blog Gamma0burst referencing 3 nm. This is the final node family from TSMC to implement FinFET transistors before the foundry transitions to nanosheets with N2. It's likely that AMD chooses one of the more advanced variants of TSMC's 3 nm nodes, such as the N3P or N3X, because 2025-26 will see rival Intel get close to introducing the Intel 20A foundry node for mass-production. Not much else is known about "Sound Wave" besides the "Zen 6" CPU cores at this point.

The mysterious Zen 6 "Morpheus" processor architecture was leaked accidentally by an AMD engineer's LinkedIn profile—news outlets picked up on this information last April. Naturally, Team Red's next priority is Zen 5—the latest reports suggest that two different chiplet designs are penciled in for mass production within the second quarter of 2024. Last September, insiders claimed that a proposed EPYC 9006 "Venice" CPU series was based on the sixth-gen microarchitecture. Everest/Olrak_29 has revealed various bits of speculative material regarding futuristic "Ryzen Client" processor designs since the start of 2024.

The latest postings to social media posit that AMD has selected an RDNA 5-based integrated graphics solution (possibly occupying a tile), thus "skipping RDNA 4" on their "Medusa" lineup of Ryzen Client processors. Leaked Microsoft documents revealed that its Xbox hardware design division was considering RDNA 5 for next-gen console specs. Medusa's CPU aspect is allegedly populated by Zen 6 "Morpheus" cores—as claimed in a January tweet. A new package design was also riffed on at the time: "Yes, I have teased this before...Medusa will use 2.5D interconnect with a much higher bandwidth," instead of a "traditional" multi-die design. Industry speculation has AMD's Zen 6 client architecture linked to a loose 2025/2026 launch window.

AMD continues to release new Ryzen 5000 series processor models for the Socket AM4 platform to this day, with new processors expected to launch next month. That's over 6 years of longevity for the platform, considering that AMD has extended official Ryzen 5000 series support all the way back to its first line of AM4 motherboards based on the 300-series chipset. The company plans a similar longevity for Socket AM5. In an interview with Overclockers UK, AMD's client channel business head David McAfee said "I think that we certainly recognized that the longevity of the AM4 platforms was one of the biggest reasons that led to the success of Ryzen and as we think and as we think about the future, 2025 and beyond, that decision to move to a next-generation of socket is one that's going to be really thought through really really carefully. We know the impact that moving to a new socket brings and we want to stay on AM5 for as long as we possibly can. We are firmly committed to 2025 and beyond and we will see how long that promise lasts beyond 2025."

AMD Socket AM5 is designed to deliver up to 230 W of package power, and has a contemporary I/O that includes a dual-channel DDR5 memory interface (4x 40-bit sub-channels); and 28 PCIe Gen 5 lanes (x16 PEG, two x4 NVMe, and x4 chipset bus), besides the usual SoC connectivity. With the upcoming Ryzen 8000G "Phoenix" APUs, we could expect to see that the socket even wires out modern display I/O such as DisplayPort 2.1 with USB type-C, and the bandwidth for 12-bit HDR up to 68 billion colors. AMD debuted Socket AM5 with the "Zen 4" microarchitecture, with "Zen 5" expected to launch in 2024. It's conceivable that the company's 2025 client architecture, "Zen 6," could also see its desktop presence on AM5, given that DDR5 memory and PCIe Gen 5 will remain relevant till at least that time.

Microsoft Xbox Series X/S, their hardware refreshes, and variants, will reportedly be the company's mainstay all the way up until 2028, the company disclosed in its documents filed as part of its anti-trust lawsuit with the FTC. In a presentation slide titled "From "Zero Microsoft" to "Full Microsoft," the company explains how its next gen Xbox, scheduled for calendar year (CY) 2028, will see a full convergence of Microsoft co-developed hardware, software, and cloud compute services, into a powerful entertainment system. It elaborates on this in another slide, titled "Cohesive Hybrid Compute," where it states the company's vision to be the development of "a next generation hybrid game platform capable of leveraging the combined power of the client and cloud to deliver deeper immersion and entirely new classes of game experiences."

From the looks of it, Microsoft fully understands the creator economy that has been built over the gaming industry, and wants to develop its next-gen console to target exactly this—a single device from which people can play, stream, and create content from—something that's traditionally reserved for gaming desktop PCs. Game streamers playing on consoles usually have an entire creator PC setup handling the production and streaming side of things. Keeping this exact use-case in mind, Microsoft plans to "enable new levels of performance beyond the capabilities of the client hardware alone," by which it means that not only will the console rely on its own hardware—which could be jaw-dropping powerful as you'll see—but also leverage cloud compute services from Microsoft.

A couple of slides from AMD's internal presentation were leaked to the web by Moore's Law is Dead, referencing what's allegedly the next-generation "Zen 5" microarchitecture. Internally, the performance variant of the "Zen 5" core is referred to as "Nirvana," and the CCD chiplet (CPU core die) based on "Nirvana" cores, is codenamed "Eldora." These CCDs will make up either the company's Ryzen "Granite Ridge" desktop processors, or EPYC "Turin" server processors. The cores themselves could also be part of the company's next-generation mobile processors, as part of heterogenous CCXs (CPU core complex), next to "Zen 5c" low-power cores.

In broad strokes, AMD describes "Zen 5" as introducing a 10% to 15% IPC increase over the current "Zen 4." The core will feature a larger 48 KB L1D cache, compared to the current 32 KB. As for the core itself, it features an 8-wide dispatch from the micro-op queue, compared to the 6-wide dispatch of "Zen 4." The integer execution stage gets 6 ALUs, compared to the current 4. The floating point unit gets FP-512 capabilities. Perhaps the biggest announcement is that AMD has increased the maximum cores per CCX from 8 to 16. At this point we don't know if it means that "Eldora" CCD will have 16 cores, or whether it means that the cloud-specific CCD with 16 "Zen 5c" cores will have 16 cores within a single CCX, rather than spread across two CCXs with smaller L3 caches. AMD is leveraging the TSMC 4 nm EUV node for "Eldora," the mobile processor based on "Zen 5" could be based on the more advanced TSMC 3 nm EUV node.

A comprehensive leak of documents—from a FTC versus Microsoft case—has exposed short and long-term plans in the world of Xbox. It seems that a relatively mild refresh of current generation Xbox Series X and S is lined up for the second half of 2024, but presentation material (dated April 2022) also reaches far into the future with strategies for next-gen gaming hardware. The bigwigs at Xbox were projecting a "full convergence" of their proprietary "xCloud" gaming platform and physical console hardware to deliver "cloud hybrid games" for 2028—schemes and priorities could have shifted in the interim, given various legal challenges and takeover bids.

One of the slides points to Microsoft getting the technical nitty-gritty sorted by CY2023—with two main options presented for consideration: a licensed ARM 64 design or a "Zen 6-based" AMD 64 processor. The next-gen Xbox's GPU aspect could incorporate a Navi 5 design (RDNA 5)—weighing up either a co-operation with AMD, or an IP license of said graphics architecture. VideoCardz theorizes that: "the latter option seems more likely if the ARM 64 chip is chosen over the Zen 6 APU." A key goal in this area seems to be an implementation of "Next-Gen DirectX Ray tracing" and "ML-based Super Resolutions" features. A Neural Processing Unit (NPU) is marked as a key provision for the 2028 console—granting some nice-to-have perks including: latency compensation, frame rate interpolation and various enrichments of the user experience.

Hardware leaker, YuuKi_AnS, has briefly turned their attention away from all things Team Blue—their latest leak points to upcoming server-grade processors chez AMD. A Zen 6 core-based 9006 EPYC CPU series, codenamed "Venice," is expected to arrive within two to three years along with an all-new SP7 socket—this information seems to have been sourced from an unnamed server manufacturer's product roadmap. A partial view of said slide also reveals forthcoming equipment powered by Intel "Falcon Shore" and NVIDIA "Blackwell" GPU technologies.

As reported a couple of months ago, older insider info has AMD using "Weisshorn" as an in-house moniker for Zen 6 "Morpheus" architecture, destined for Venice CPUs—alleged to form part of a 2025/2026 EPYC lineup. YuuKi_AnS proposes that these will utilize either 12-channel or 16-channel DDR5 memory configurations—thus providing plenty of bandwidth across hundreds of Zen cores. Altogether very handy for cloud, enterprise, and HPC workloads—industry experts reckon that 384-core counts are feasible on single packages. Naturally, a Team Red timeline dictates that Zen 5 "Nirvana" is due before Zen 6 "Morpheus," so EPYC 9005 "Turin(-X)" and 8005 "Turin-Dense" lineups are (allegedly) up for a 2024-ish launch window on SP5 (LGA-6096) and SP6 (LGA 4094) socket types.

An AMD engineer inadvertently leaked the core codenames of the company's upcoming "Zen 5" and "Zen 6" microarchitectures. It's important to understand here what has been leaked. "Zen 5" and "Zen 6" are microarchitecture names, just like the current "Zen 4" and past "Zen 3" or older. AMD uses codenames for the CCD (CPU complex dies) based on these microarchitectures, which it shares between Ryzen client and EPYC enterprise processors. For example, the CCD codename for "Zen 3" is "Brekenridge," and for "Zen 4" it is "Durango." AMD also uses codenames for the CPU cores themselves. "Zen 3" CPU cores are codenamed "Cerebrus," and "Zen 4" CPU cores "Persphone." And now, the leak:

The CCD based on the upcoming "Zen 5" microarchitecture is codenamed "Eldora," and the "Zen 5" CPU core itself is codenamed "Nirvana." There's no codename for the CCD based on "Zen 6," but its CPU cores are codenamed "Morpheus." The "Zen 5" microarchitecture will be based on the 3 nm EUV foundry node; while "Zen 6" will be 2 nm EUV. The engineer in the screenshot is contributing to the power-management technology behind "Zen 5" and "Zen 6," and states that their work on "Zen 5" spanned January-December of 2022, which means the development phase of the next "Zen" architecture is probably complete, and the architecture is undergoing testing and refinement. It's also claimed that work on at least the power-management aspect of "Zen 6" has started from January 2023.