# Memory Timings Explained



## djbbenn (Dec 1, 2005)

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## Dynamic (Dec 8, 2005)

Great job, great article! I'm surprised nobody came in and said anything, weird? Don't you hate it when you put something up on the net and nobody really pays any attention to it? I know how you feel and that's why i came here to let you know how impressed i am with your work.
Now i've heard there is a way timings are calculated. So for example is you have 222 you should have the Tras as "6" instead of "5". I don't get that and i don't really go by that rule since that rule is for certain memory chips and not all. I got a pair of BH5 sticks and i'm just fine using 2225-1T timings with my booster @ 3.4v. Getting around 6400/6400 on Sandra SR3 memory test anyway, so go figure. Take care...


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## djbbenn (Dec 8, 2005)

Thanks... When setting timings, it depends on the speed of the memory and the voltage. When you buy a module, it's rated for a specfic speed, timings and voltage. At those settings you can run the ram, but if you change any, like the frequency, you will get to a point where you will either have to up the voltage or loosen the timings. A lot of baords don't have the "other timings", just the "rated timings". But if you do, there is sweet spots in them that will work better for you. BH-5 is good at high speeds with tight timings if the proper voltage is there which you look to have.

-Dan


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## XeoNoX (Dec 10, 2005)

I came across a couple months back on this Article that i found a tad bit better, althought the one above is good, the one from cooltech explains it all to a n00b like me!

Article from cooltechzone: Direct URL is

http://www.cooltechzone.com/index.php?option=content&task=view&id=377&Itemid=0


Nowadays it seems like everybody is tweaking their system. Something that is of importance in your system's performance is memory bandwidth, which is directly related to the bus speed. This is a rather confusing thing, sometimes a lower bus speed with faster memory timings is considerably better than just increasing your bus speed. When you are buying memory you want to get the highest bandwidth required by your system with the lowest CAS/tRCD/tRPD/tRAS. If you are operating your system at a 400MHz bus rate then you need at least PC3200 memory and perferably with a CAS specification of 2. If you are overclocking your system to 500MHz, for example, bus rate then you need on the order of PC4000, but as you start shopping for the higher bandwith memory, which will run at higher bus frequencies you will find that in order to get memory modules to run at the higher bandwidth - the manufactures have to numerically raise the CAS latency, typically to 2.5 and 3 in order to produce the modules with bandwidth at an affordable price. As you can see the bandwidth to CAS relationship does not play in your favor unless you want to pay high prices for memory. As you can see the performance hit you take from CAS 2 to CAS 3 is 33 percent, but on the other hand if you can run a front side bus of 500MHz then you have gained a complete system performance increase of 25 percent, so with the complete system operating 25 percent faster it makes up for the 33 percent loss in the CAS latency for most applications. 

*Memory Specifications:*

Memory specifications for timings are usualy stated such as 2/2/2/6-11/1T which relate to the values of the CAS/tRCD/tRP/tRAS/CMD.

The last two specifications in 2/2/2/6-11/1T, tRAS and CMD (short for Command) rate, are somewhat complicated and more difficult to understand than simple access and precharge latencies (the first three specifications). The level of misinformation on tRAS and CMD rate are rampant because some memory manufacturers use it for a concept of performance.

*CMD Rate and its Misconceptions:*

CMD rate is generally used to describe the time from a chip select until a Row Activate Command can be given. The chip select defines the physical bank in which the row is located. In a system running a single, single-sided memory module, there is never a question which bank will be selected since there is only one. 

More generally, the CMD Rate is a chipset latency that is not determined by the memory but by the time it takes the chipset to translate the virtual address space into physical memory addresses. Needless to say that higher density system memory with its more addresses will take longer to decode than a single low density module, even if it is double-sided. 

Intel has taken care of this problem by simply limiting the number of banks supported per memory channel to four. This, in turn allows them to run all their chipsets on a fixed CMD rate of 1T, regardless of how much memory is installed. 

Rating a module as 1T is actually somewhat misleading advertising because all unbuffered modules are capable of a 1T CMD rate up to four banks per channel, beyond which chipset limitations become a factor.
tRAS and its Importance:

Also known as Active to Precharge Delay, this is the time between receiving a request for data electronically on the pins of a memory module and then initiating RAS to start the actual retrieval of data. This command seems important, but really it isn't. Memory access is a very dynamic thing. Sometimes memory is being hit hard, and other times very sporadically. Though at all times, memory access is at constant, therefore, it is rare that the tRAS command is received to access new data (such as a substantial change, like opening a new program). 

The first number is the CAS latency, the second number is the tRCD, and the third number is the tRP. What are these things and why do they affect system performance? 

*CAS:*

CAS is Column Address Strobe or Column Address Select. CAS controls the amount of time (in cycles (2, 2.5,& 3) between receiving a command and acting on that command. Since CAS primarily controls the location of HEX addresses, or memory columns, within the memory matrix, this is the most important timing to set as low as your system will stably accept it. There are both rows and columns inside a memory matrix. When the request is first electronically set on the memory pins, the first triggered response is tRAS (Active to Precharge Delay). Data requested electronically is precharge, and the memory actually going to initiate RAS is activation. Once tRAS is active, RAS, or Row Address Strobe begins to find one half of the address for the required data. Once the row is located, tRCD is initiated, cycles out, and then the exact HEX location of the data required is accessed via CAS. The time between CAS start and CAS end is the CAS latency. Since CAS is the last stage in actually finding the proper data, it's the most important step of memory timing. 

*tRCD:*

Also known as RAS to CAS Delay, in addition to Column Address Strobe, there is Row Address Strobe. CAS and RAS combined allow for the exact location of memory blocks. There is an interval between RAS (activated when data is first requested) and CAS (activated when RAS is complete), as memory can't locate a block precisely in a single stage. tRCD is the cycle time between the first stage in memory access, the row strobe, and the second stage. However, the performance impact of this setting is often neglible, as memory tries to store data from programs in sequential order. It tries to keep the same row for a single program, and ordered columns to reduce the time for tRCD.
*
tRP:*

Also known as RAS Precharge, this is the amount of time it takes for memory to terminate the access in one row and begin another. To put it simply, after data is set to the pins and activates tRAS, then RAS, tRCD, and CAS; the memory needs to terminate its current row and start all over at tRAS. This is the very basic function of how memory works. This is only an important setting when you're doing massive shifting in data, for example - working with large virtual buffers or video rendering. At that point, several rows are being consumed by a single program, and its advantageous for the program to be able to switch quickly between these rows.

*Final Statements...*

If you have read all the above and are still somewhat confused you do not have to know all of it to make a decision on what memory is best for your system and what the typical memory timings in the BIOS of your computer should be. Basically, you need memory that provides at least as much bandwidth as your processor and has the lowest CAS you can find or afford (2).

Since the cost of memory modules does not vary drastically between speed grades, we recommend that you purchase the highest speed you think you may need in the long term. You will save some money if you decide to upgrade you microprocessor later, all memory is backward compatabile as far as bus speeds are concerned. Also if you purchase PC3200 400MHz modules with a CAS specification of 2.5 and you run it at a reduced frequency of 333MHz it will, in almost all cases, operate at CAS 2 at the reduced frequency.

Most DIMMs that operate at tight timings, such as PC3200 and PC3500 modules, have to run the memory at lower MHz than the system bus to maintain the tight timings. However, when overclocking the microprocessor to extreme speeds these DIMMs are bandwidth limiting the processor unless you loosen the timings so that the memory can run in sync with the front side bus or CPU external frequency. The signifigance of this is that when the processor requires a great deal of bandwidth, the CPU will have to wait for another clock cycle before being filled, as the memory is just not fast enough to keep up at the same pace. Having a large pool of bandwidth is great when you're working with applications that process a lot of raw data such as Photoshop or databases.

The other point is that CAS2-rated PC3200 and PC3500 memory can make up for the lack of bandwidth because the memory has a lower latency that in effect moves data between the CPU and the memory much faster. Programs that do not require a large amount of bandwidth tend to benefit more from quicker data transfers between the memory and the rest of the computer such as games and 3D applications.

With all things equal, a stick of DDR memory capable of running 2-2-2-5 memory timings will make the computer operating experience seem faster than a DIMM which can only operate at 3-4-4-8. This is because the delay from when the memory receives an instruction, retrieves the data, and sends it back out is less time.


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## Desodorante (Sep 22, 2008)

Thank you very much djbbenn!


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## P4-630 (Sep 23, 2008)

djbbenn said:


> tRAS = tCL + tRCD + tRP (+/- 1) so that it gives everything enought time before closing the bank.



Now how is it possible that some people seem to be able to run their ddr2 at 4-4-4-4 or 5-5-5-5 ?


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