# Bulldozer Core-Count Debate Comes Back to Haunt AMD



## btarunr (Jan 23, 2019)

AMD in 2012 launched the FX-8150, the "world's first 8-core desktop processor," or so it says on the literal tin. AMD achieved its core-count of 8 with an unconventional CPU core design. Its 8 cores are arranged in four sets of two cores each, called "modules." Each core has its own independent integer unit and L1 data cache, while the two cores share a majority of their components - the core's front-end, a branch-predictor, a 64 KB L1 code cache, a 2 MB L2 cache, but most importantly, an FPU. There was much debate across tech forums on what constitutes a CPU core. 

Multiprocessor-aware operating systems had to be tweaked on how to properly address a "Bulldozer" processor. Their schedulers would initially treat "Bulldozer" cores as fully independent (as conventional logic would dictate), until AMD noticed multi-threaded application performance bottlenecks. Eventually, Windows and various *nix kernels received updates to their schedulers to treat each module as a core, and each core as an SMT unit (a logical processor). The FX-8350 is a 4-core/8-thread processor in the eyes of Windows 10, for example. These updates improved the processors' performance but not before consumers started noticing that their operating systems weren't reporting the correct core-count. In 2015, a class-action lawsuit was filed against AMD for false marketing of FX-series processors. The wheels of that lawsuit are finally moving, after a 12-member Jury is set up to examine what constitutes a CPU core, and whether an AMD FX-8000 or FX-9000 series processor can qualify as an 8-core chip.



 




US District Judge Haywood Gilliam of the District Court for the Northern District of California rejected AMD's claim that "a significant majority of" consumers understood what constitutes a CPU core, and that they had a fair idea of what they were buying when they bought AMD FX processors. AMD has two main options before it. The company can reach an agreement with the plaintiffs that could cost the company millions of Dollars in compensation; or fight it out in the Jury trial, by trying to prove to 12 members of the public (not necessarily from an IT background) what constitutes a CPU core and why "Bulldozer" qualifies as an 8-core silicon. 

The plaintiffs and defendants each have a key technical argument. The plaintiffs could point out operating systems treating 8-core "Bulldozer" parts as 4-core/8-thread (i.e. each module as a core and each "core" as a logical processor); while the AMD could run multi-threaded floating-point benchmark tests to prove that a module cannot be simplified to the definition of a core. AMD's 2017 release of the "Zen" architecture sees a return to the conventional definition of a core, with each "Zen" core being as independent as an Intel "Skylake" core. We will keep an eye on this case.

*View at TechPowerUp Main Site*


----------



## Midland Dog (Jan 23, 2019)

8 alu from memory, for integer ops its an 8 core for floating point its a 4 core, simples, i personally would have called it an 8 thread cpu, not and 8 core. at the same time its up to the customer to do some research, as a quad core its decent perf but for an 8 core its kind of pathetic


----------



## the54thvoid (Jan 23, 2019)

Regardless of the merits of the case, these class action lawsuits are a sham. The lawyer fees are disproportionately high, so any payout initially goes to the firms representing the plaintiff. All these tech suits are carried out in spite of consumer demand, not because of it. I hope AMD win, not because they were right but because the consumers won't win this, the lawyers will.


----------



## qubit (Jan 23, 2019)

Hopefully this lawsuit will discourage AMD from using such a cludgy, low performance compromised design in the future.


----------



## londiste (Jan 23, 2019)

As far as lawsuit goes this seems a bit too litigation-happy approach to things. But it is their right.

Defining a CPU is not as straightforward and probably gets pretty technical in court.

I suppose the single frontend-dispatch should technically be damning to AMD here. For a long while there have been multiple/many execution units in a modern CPU. How they are organized, segmented or grouped varied but there have been multiple for a long time. What sets up the core is frontend and perhaps more directly - dispatch.

Just take a look at the core diagrams:
Bulldozer: https://en.wikipedia.org/wiki/File:AMD_Bulldozer_block_diagram_(CPU_core_bloack).PNG
Zen: https://en.wikichip.org/wiki/amd/microarchitectures/zen#Individual_Core
Skylake: https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Individual_Core


----------



## Zubasa (Jan 23, 2019)

qubit said:


> Hopefully this lawsuit will discourage AMD from using such a cludgy, low performance compromised design in the future.


I am pretty sure the lack of interest in their past products are more than enough discouragement.
AMD almost went under because of it.


----------



## DeathtoGnomes (Jan 23, 2019)

qubit said:


> Hopefully this lawsuit will discourage AMD from using such a cludgy, low performance compromised design in the future.


wishful thinking, we all know both side will do this to save a buck.


----------



## Arumio (Jan 23, 2019)

Well, I on my AMD A10-5800k see the same thing (i.e. windows 10 says: "cores:2, logical processors: 4") and it drive me nuts annoying


----------



## DeathtoGnomes (Jan 23, 2019)

Zubasa said:


> I am pretty sure the lack of interest in their past products are more than enough discouragement.
> AMD almost went under because of it.


dont mix shit design and poor management, each contributed to that period of time.


----------



## Flaky (Jan 23, 2019)

Last time I checked, bristol ridge apu (excavator architecture - so bulldozer based-core) displayed 4 cores in task manager, so it's not really that consistent.


----------



## Zubasa (Jan 23, 2019)

DeathtoGnomes said:


> dont mix shit design and poor management, each contributed to that period of time.


Poor management lead to shit designs and shit products.
If AMD management knew what they were doing back then, they would have 86 that junk before they sink more money making and even trying to sell it.
They might even be better off trying to die-shrink and clock the Phenoms higher.


----------



## cucker tarlson (Jan 23, 2019)

it has 8 physical cores,so despite people were scammed into thinking this is a full 8 core CPU AMD will probably remain unharmed cause of this.To be frank people who bought have themselves to blame,they should've read a review or two,these CPU were absolute crap.


----------



## Easo (Jan 23, 2019)

It physically has 8 cores/modules/whatever, which might give them the win. But nontechnical jury is a recipe for disaster, in my eyes. 
And really, stop suing for everything... No one has been hurt, this is to get money, not to punish the company.


----------



## silentbogo (Jan 23, 2019)

What bit them in the ass using words "real cores" in their marketing campaigns. Even if each module acts and performs as a "real" core, it does not matter in this situation.
This is very similar to GTX970 fiasco: 3.5GB fast memory + 0.5GB slower memory technically adds up to 4GB, but they still lost the class action lawsuit.
Same here: you have a shared fetch/decode, you have a shared FP scheduler, and if you run AVX256 workload - your FP pipes become one. This opens up the gate for litigation, and since AMD failed to convey that to the customer (and figure out the scheduling problems in Windows/Linux before launch) - I'm sure they'll be fined and every poor soul that bought an FX processor or A-series APU will get their $5-10 or whatever, the world will move on and both will be fine.



Arumio said:


> Well, I on my AMD A10-5800k see the same thing (i.e. windos 10 says: "cores:2, logical processors: 4") and it drive me nuts annoying


Hah. Try explaining a customer why his A4-5300 shows up as a single core.


----------



## londiste (Jan 23, 2019)

Easo said:


> It physically has 8 cores/modules/whatever, which might give them the win. But nontechnical jury is a recipe for disaster, in my eyes.


It definitely has 4 modules. Whether half a module is a core is up for debate but technically - more likely the answer is no.


----------



## Camm (Jan 23, 2019)

Eh, if you look at an FX-3850 die shot, its pretty apparent there are 8 cores there compared to say, a 7700k with SMT.

Don't think AMD really has anything to worry about.


----------



## londiste (Jan 23, 2019)

Camm said:


> Eh, if you look at an FX-3850 die shot, its pretty apparent there are 8 cores there compared to say, a 7700k with SMT.


Bullshit.
This is far from apparent. Both dies contain duplicate parts in the core/module. Whether that constitutes a core is arguable.

Would you like to elaborate?
https://en.wikichip.org/wiki/intel/core_i7/i7-7700k#Die_Shot
https://www.extremetech.com/wp-content/uploads/2012/10/Piledriver-Die.jpg


----------



## Basard (Jan 23, 2019)

YESS!!!! Can't wait to get my $3.72 in the mail!!!!  Who want's to attend my crack party?!

@londiste Well, to be fair, you need to draw eight squares on it to see it.


----------



## Camm (Jan 23, 2019)

londiste said:


> bullshit.



Not to scale, but rough side by side between the two shoes that each core is disparate.


----------



## londiste (Jan 23, 2019)

Camm said:


> Not to scale, but rough side by side between the two shoes that each core is disparate.


Sorry, but your image is incorrect. The parts numbered on the Bulldozer die shot are L2 cache.
Bulldozer modules are the colorful things in the corners right next to L2 cache.

Basically this:


----------



## seronx (Jan 23, 2019)

Here you guys go;






A, B, C, D, E, F, G, H => 8-cores

---
Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS
Hugh McIntyre, Member, IEEE, Srikanth Arekapudi, Member, IEEE, Eric Busta, Member, IEEE,
Timothy Fischer, Member, IEEE, Michael Golden, Member, IEEE, Aaron Horiuchi, Member, IEEE,
Tom Meneghini, Member, IEEE, Samuel Naffziger, Senior Member, IEEE, and James Vinh, Senior Member, IEEE

This new micro-architecture contains two processor cores that implement chip-level multi-threading (CMT).

Bulldozer’s CMT provides dedicated compute resources to each CPU to maximize single-threaded performance and multi-threaded throughput while significantly improving power and area efficiency compared to fully replicated CPU cores.  The result is improved performance and frequency and reduced area and power compared to a previous AMD x86-64 CPU built in the same 32 nm process [4]. Frequency at constant voltage is improved by more than 20% (Fig. 4) while the dual-core switching capacitance is reduced to 84% of two previous cores.

Physically, the two-core Bulldozer module contains 213 million transistors and is designed to operate from 0.8–1.3 V.

As shown in Fig. 1, the Bulldozer module includes two cores with shared L2 cache and occupies 30.9mm^2 .  Each core is dedicated to a thread and contains a four-wide integer execution unit, issue/retire logic, 16-KB four-way set associative L1 data cache, and a load/store unit. A separate dual-threaded floating-point unit is shared between the integer cores. Of the total module floorplan area, the two cores occupy approximately 21% and the floating-point unit occupies another 9%.
---

IEEE has to review the above to even allow it.


----------



## londiste (Jan 23, 2019)

The Register has pretty good pictures of the module with identified sub-parts to couple different levels:
https://www.theregister.co.uk/2015/11/06/amd_sued_cores/
Pictures are 90° rotated from previous images, L2 cache at the right instead of up or down.

The question is if BP, Decode and Fetch (and to smaller extent FPU) are part of the core or not.
They are definitely a functional and required part of a CPU core, architecturally speaking. This is also the reason logical core/thread distinction for operating systems was moved from 8-core to SMT-like 4-core/8-thread for these processors as that is much more correct match to what the module is.


----------



## DeathtoGnomes (Jan 23, 2019)

Zubasa said:


> Poor management lead to shit designs and shit products.
> If AMD management knew what they were doing back then, they would have 86 that junk before they sink more money making and even trying to sell it.
> They might even be better off trying to die-shrink and clock the Phenoms higher.


LOL, the problems started long before Phenoms. Management didnt lead anything, chip design team got hung out to dry, and the PR dept. was doing more harm than good, then came Phenoms...


----------



## Joss (Jan 23, 2019)

the54thvoid said:


> Regardless of the merits of the case, these class action lawsuits are a sham. The lawyer fees are disproportionately high, so any payout initially goes to the firms representing the plaintiff. All these tech suits are carried out in spite of consumer demand, not because of it. I hope AMD win, not because they were right but because the consumers won't win this, the lawyers will.


Nuff said.


----------



## rvalencia (Jan 23, 2019)

CPU like FX-8150 has 8 CPU cores since a thread couldn't exceed two integer units when there's four integer units in a module and it's IPC is like Jaguar CPUs.


----------



## TheGuruStud (Jan 23, 2019)

DeathtoGnomes said:


> LOL, the problems started long before Phenoms. Management didnt lead anything, chip design team got hung out to dry, and the PR dept. was doing more harm than good, then came Phenoms...



Phenom II was good, just slow to arrive. 4 ghz OC from the cheapo chip waa spanking intel.


----------



## bug (Jan 23, 2019)

Meh, the design of Bulldozer was known well before its launch, I'm not sure why anyone would fret about how to count the cores.
What's next, suing because the L3 cache is shared, so overall, a "core" does not get the fully dedicated resource?


----------



## silentbogo (Jan 23, 2019)

bug said:


> Meh, the design of Bulldozer was known well before its launch, I'm not sure why anyone would fret about how to count the cores.


To tech-educated audience, not to an average consumer. 


bug said:


> What's next, suing because the L3 cache is shared, so overall, a "core" does not get the fully dedicated resource?


Some CPUs don't have L3, but this does not make them "not CPUs". The issue is not whether it "counts" or "does not count" as a CPU core, but the fact that AMD failed to convey this information to consumers. E.g. if you write "8 cores" on the box, the consumer will buy the CPU and be disappointed later when he/she finds out that it may not be 8 cores at all. If you  write 4 modules [8 cores] it won't make it significantly less appealing, but it will make the potential buyer curious about these "modules" and at least do a quick google-fu to see what this is all about.
When you have such a mess, it's always open for interpretation. Some may say "yes, it's 8 cores with shared components", some (like me) will say that this is 4 cores with extra stuffin'.
Sun did use similar approach in the past to make their CPUs more multithreading-capable, and while each core had 2 integer units and 1 floating point unit it was still being called one CPU core (capable of running 8 threads).


----------



## londiste (Jan 23, 2019)

Even Execution Unit or Integer Unit does not necessarily mean the same thing across different architectures. For example, Bulldozer Integer Unit had 2 ALUs (Arithmetic Logic Unit) and 2 AGUs (Address Generation Unit) while Zen's Integer Unit has 4 ALUs (even though with a bit more resticted set of operations if I remember correctly) and 2 AGUs. Zen core has effectively the same integer calculation capacity in its Integer Unit that Bulldozer has.


----------



## noel_fs (Jan 23, 2019)

I bet the price people paid for those "8 core" processor wasnt 800$ so im willing to say that its pretty fair. Nowdays motherboards companies call anything a phase so it is how it is.


----------



## newtekie1 (Jan 23, 2019)

btarunr said:


> The plaintiffs and defendants each have a key technical argument. The plaintiffs could point out operating systems treating 8-core "Bulldozer" parts as 4-core/8-thread (i.e. each module as a core and each "core" as a logical processor);



The problem with this argument is that even the operating systems couldn't keep it straight, and it was very clear that the OS wasn't detecting the CPU this way but instead was manually configured to show 4c/8t.  Even Windows 10 still detects some Bulldozer architecture chips as 4c/4c.


----------



## bug (Jan 23, 2019)

silentbogo said:


> To tech-educated audience, not to an average consumer.
> 
> Some CPUs don't have L3, but this does not make them "not CPUs". The issue is not whether it "counts" or "does not count" as a CPU core, but the fact that AMD failed to convey this information to consumers. E.g. if you write "8 cores" on the box, the consumer will buy the CPU and be disappointed later when he/she finds out that it may not be 8 cores at all. If you  write 4 modules [8 cores] it won't make it significantly less appealing, but it will make the potential buyer curious about these "modules" and at least do a quick google-fu to see what this is all about.
> When you have such a mess, it's always open for interpretation. Some may say "yes, it's 8 cores with shared components", some (like me) will say that this is 4 cores with extra stuffin'.
> Sun did use similar approach in the past to make their CPUs more multithreading-capable, and while each core had 2 integer units and 1 floating point unit it was still being called one CPU core (capable of running 8 threads).


That's all nice and everything, but I think it's clear to everyone this is just about lawyers noticing "core" hasn't been defined in a court of law before and grabbing their opportunity to squeeze some money out of it.


----------



## Vayra86 (Jan 23, 2019)

silentbogo said:


> To tech-educated audience, not to an average consumer.
> 
> Some CPUs don't have L3, but this does not make them "not CPUs". The issue is not whether it "counts" or "does not count" as a CPU core, but the fact that AMD failed to convey this information to consumers. E.g. if you write "8 cores" on the box, the consumer will buy the CPU and be disappointed later when he/she finds out that it may not be 8 cores at all. If you  write 4 modules [8 cores] it won't make it significantly less appealing, but it will make the potential buyer curious about these "modules" and at least do a quick google-fu to see what this is all about.
> When you have such a mess, it's always open for interpretation. Some may say "yes, it's 8 cores with shared components", some (like me) will say that this is 4 cores with extra stuffin'.
> Sun did use similar approach in the past to make their CPUs more multithreading-capable, and while each core had 2 integer units and 1 floating point unit it was still being called one CPU core (capable of running 8 threads).



I still struggle to see how an 'average consumer' DOES know that he's been ripped off with half a core count and doesn't know about other shared resources in chips. I also struggle how you would even know what core count is while not knowing AMD was always up front about this architecture and its design choices.

This is the same consumer that still buys into 'dual core' Intel chips that have i7 plastered on top, you know, that name that tends to represent a quad core in the desktop world since forever 

Baseless case is baseless, IMO. AMD should certainly win this and if they don't, faith in humanity -100



bug said:


> That's all nice and everything, but I think it's clear to everyone this is just about lawyers noticing "core" hasn't been defined in a court of law before and grabbing their opportunity to squeeze some money out of it.



Amen.


----------



## londiste (Jan 23, 2019)

Vayra86 said:


> AMD was always up front about this architecture and its design choices.


It depends. AMD was quite clear about the architecture. Unfortunately, not many people know or care about that and at the same time AMD very aggressively pushed the 8-core story.


----------



## Vayra86 (Jan 23, 2019)

londiste said:


> It depends. AMD was quite clear about the architecture. Unfortunately, not many people know or care about that and at the same time AMD very aggressively pushed the 8-core story.



Well if the information was publicly available and even *presented* publicly, isn't that just customer due diligence territory? Though I see what you're getting at, there should have been a couple of powerpoint slides with disclaimers concerning the 8 core count, along with every outing of it. 'May not provide full performance of a single core' etc.

I think the only real approach here is the direct comparison to SMT and how AMD can explain that one is a 'core' and the other is SMT. They can bring their Ryzen die shots for that.


----------



## bug (Jan 23, 2019)

Vayra86 said:


> Well if the information was publicly available and even *presented* publicly, isn't that just customer due diligence territory? Though I see what you're getting at, there should have been a couple of powerpoint slides with disclaimers concerning the 8 core count, along with every outing of it. 'May not provide full performance of a single core' etc.
> 
> I think the only real approach here is the direct comparison to SMT and how AMD can explain that one is a 'core' and the other is SMT. They can bring their Ryzen die shots for that.


The info was more than public. AMD repeatedly told us they went the way they did because in their opinion, floating point was not used enough to justify the die space a FPU per core needs. It was more like "we looked at this and here's what we think a clever solution we found". Even if almost everyone realized it was mostly a gamble.

Going even further back, people bought AMD's 5x86 and later K6 (and variants), knowing fully well they didn't measure up to Intel in FP performance. But since they were offered at a better price, they were good enough for plenty of people.


----------



## neatfeatguy (Jan 23, 2019)

If something like this can take hold in courts, then maybe people should turn their attention towards the International Astronomical Union and file a lawsuit about how they demoted Pluto.


----------



## XiGMAKiD (Jan 23, 2019)

seronx said:


> Here you guys go;
> -snip-
> IEEE has to review the above to even allow it.


I'm more intrigued by why do you label the cores counter clockwise than by the IEEE review


----------



## silentbogo (Jan 23, 2019)

bug said:


> That's all nice and everything, but I think it's clear to everyone this is just about lawyers noticing "core" hasn't been defined in a court of law before and grabbing their opportunity to squeeze some money out of it.


The reason this lawsuit went through is not "because there is no definition of the CPU core" and lawyers found this loophole, but because AMD gave consumers the reason to doubt their definition. Lawyers only pick up class action lawsuits if there is substance to it, and high chance of winning or settle.



Vayra86 said:


> This is the same consumer that still buys into 'dual core' Intel chips that have i7 plastered on top


Those i7 chips have clearly written 2c/4t in specs. AMD chips only have "core" count on the official spec sheet.
I still agree that it's missleading, but at least you get the info on your first google hit.


----------



## londiste (Jan 23, 2019)

silentbogo said:


> AMD chips only have "core" count on the official spec sheet.


They have both 8 cores and 8 threads in their specs.
FX-8150, for example: https://www.amd.com/en/products/cpu/fx-8150


----------



## bug (Jan 23, 2019)

silentbogo said:


> The reason this lawsuit went through is not "because there is no definition of the CPU core" and lawyers found this loophole, but because AMD gave consumers the reason to doubt their definition. Lawyers only pick up class action lawsuits if there is substance to it, and high chance of winning or settle.
> 
> 
> Those i7 chips have clearly written 2c/4t in specs. AMD chips only have "core" count on the official spec sheet.
> I still agree that it's missleading, but at least you get the info on your first google hit.


So, basically this about the architecture not being explained in the spec sheet? Because the net is full of block diagrams for Bulldozer (wikipedia included) that clearly show the shared FPU.


----------



## silentbogo (Jan 23, 2019)

bug said:


> So, basically this about the architecture not being explained in the spec sheet? Because the net is full of block diagrams for Bulldozer (wikipedia included) that clearly show the shared FPU.


As I said earlier, a simple "4 modules / 8 cores" or "2 modules / 4 threads" would've been enough to provide "food for thought". Link to Bulldozer architecture brief would've been nice too. 
Also, Wikipedia is not amd.com. If third-party sites have more info about your product than an official product page and it's presented in a more usable manner, it's definitely a f%$^k up on AMD's part.


----------



## bug (Jan 23, 2019)

silentbogo said:


> As I said earlier, a simple "4 modules / 8 cores" or "2 modules / 4 threads" would've been enough to provide "food for thought". Link to Bulldozer architecture brief would've been nice too.
> Also, Wikipedia is not amd.com. If third-party sites have more info about your product than an official product page and it's presented in a more usable manner, it's definitely a f%$^k up on AMD's part.


Are you seriously suggesting something that was all over the place at the time was actually missing on amd.com? I don't have time to dig up the official specs right now, but wow!


----------



## mouacyk (Jan 23, 2019)

Customer faith is shaken when an OS is reporting core count differently than what was marketed, regardless of technical details.  One would think that a business pushing (even more) core count as its primary strategy would do everything to make sure that its concept isn't misrepresented to the customer.  Either someone dropped the ball in marketing defense, Bulldozer's CPU core doesn't stack up, or all the operating systems are out to do AMD in.


----------



## silentbogo (Jan 23, 2019)

bug said:


> I don't have time to dig up the official specs right now, but wow!


You don't have time to dig up specs, now put yourself in shoes of the average Joe/Jane who wanted to build a PC between 2012 and 2015, for example.


----------



## bug (Jan 23, 2019)

silentbogo said:


> You don't have time to dig up specs, now put yourself in shoes of the average Joe/Jane who wanted to build a PC between 2012 and 2015, for example.


Wtf, I'm at work trying to debug some stuff dude. Plus, between then and now, those specs are most likely archived.


----------



## nickbaldwin86 (Jan 23, 2019)

the54thvoid said:


> Regardless of the merits of the case, these class action lawsuits are a sham. The lawyer fees are disproportionately high, so any payout initially goes to the firms representing the plaintiff. All these tech suits are carried out in spite of consumer demand, not because of it. I hope AMD win, not because they were right but because the consumers won't win this, the lawyers will.



If AMD wins then they have not learn what they did isn't ok. (If that fact be true). the money just goes to the lawyers and AMD doesn't get to keep money that they wrongfully took ie falsely sold a product.

it is a loose loose really but either way hopefully AMD has learned something from this


----------



## Vya Domus (Jan 23, 2019)

Never in the history of computing CPU cores have been equated to execution units. This is a erroneous association that sparked out of people's desire to slap a badge on things they don't understand. By the way has anyone filed a lawsuit yet on every GPU maker out there for marketing their products as having thousands of "cores" ? This will never go anywhere not because this is a grey area but rather because there is nothing to debate. That's an x86 compatible CPU and that's it's architecture, end of story. If you want to have the most purebred CPU core out there then go ahead and buy one of these :





No FPUs, no pipelining, no duplicate of nothing. But good luck because neither AMD nor Intel have made CPU cores that look like that for more than 3 decades now.



silentbogo said:


> since AMD failed to convey that to the customer



Details about the architecture that they used were made public and several publications made some pretty in depth analyses on it. Clearly that was never the case.



silentbogo said:


> Try explaining a customer why his A4-5300 shows up as a single core.



But somehow AMD was expected to spoon feed complex computer architecture concepts to them ? Try explain to a customer why CPUs from both AMD and Intel with duplicate front ends show up as having more cores in various programs. Come on.



silentbogo said:


> some (like me) will say that this is 4 cores with extra stuffin'.



Then unfortunately you don't know enough about this subject as was the case with many.


----------



## Vayra86 (Jan 23, 2019)

mouacyk said:


> Customer faith is shaken when an OS is reporting core count differently than what was marketed, regardless of technical details.  One would think that a business pushing (even more) core count as its primary strategy would do everything to make sure that its concept isn't misrepresented to the customer.  Either someone dropped the ball in marketing defense, Bulldozer's CPU core doesn't stack up, or all the operating systems are out to do AMD in.



Or its none of those things, and the core/thread count was just a way for a less conventional architecture to 'fit in' with an OS.



silentbogo said:


> You don't have time to dig up specs, now put yourself in shoes of the average Joe/Jane who wanted to build a PC between 2012YOu  and 2015, for example.



What about them? FX processors were reviewed and those reviews ALL pointed out something about its architecture being different, specifically in terms of core setup. AMD released countless powerpoint slides detailing the same thing. They also, without exception, noted the performance could be stellar or abysmal depending on workload.

You knew exactly what you were getting as a customer and if you didn't its entirely your own fault. Average Joe and Jane don't build PCs. They buy a laptop, let a shop build one, or let us build one.

Stop trying to find a good argument here because there is none. This case exists because perhaps there's some money to be had. Not because some customers were left out in the cold (which is what they should be used for).



silentbogo said:


> at least you get the info on your first google hit.



FX Bulldozer, let's try (see thumbnail below)

There is even a nice picture with schematic/die shot, clearly specifying two integer and one FP unit and shared cache.

And here comes the kicker. Let's do i7 Core as well? You tell me what's more informative for a first google hit...


----------



## HD64G (Jan 23, 2019)

Since I own a CPU of this arch for months now (FX8350) and knowing well what to expect from it for years before I got it, I can definitely say (after testing many different use cases on it) that it is an 8-thread CPU that acts some times as an 8-core one and others as a 4-core one due to the OS schedulers design. Most apps that need mutliple threading power use it completely at its 100% of its threads (i.e. browsers) and others use just the first thread per module until (or if not) more power is needed. And then, it begins using the rest of the threads. This type of behaviour shows that it is a dinstictive arch from what we knew until back then, but it doesn't make it a 4-core at all. Failing to fully understand something doesn't make it non-existent after all.


----------



## xtreemchaos (Jan 23, 2019)

ive gotta stick up for the old FX, ive been running a 8350 @4.8 in my image processing rig for about 6 years and its run lovely, i can count on one hand how many times its crashed over the years if i could remember, if its a 4 or 8 core dont mean a shit to me all that matters is how well and fast it processes my astro images and runs photoshop and staxing programs.  dont hate me im nice really in my old little way. charl.

here the ol girl if any one wonders what she looks like.


----------



## diatribe (Jan 23, 2019)

xtreemchaos said:


> ive gotta stick up for the old FX, ive been running a 8350 @4.8 in my image processing rig for about 6 years and its run lovely, i can count on one hand how many times its crashed over the years if i could remember, if its a 4 or 8 core dont mean a shit to me all that matters is how well and fast it processes my astro images and runs photoshop and staxing programs.  dont hate me im nice really in my old little way. charl.
> 
> here the ol girl if any one wonders what she looks like.
> 
> View attachment 114975



I'm not familiar with that case.  Do you have any more well lit pictures?


----------



## xtreemchaos (Jan 23, 2019)

all I can remember of the name is "Loop" it has a glass panel that gos on the front but it cuts the air flow too much so ive never used it. charl.


----------



## kapone32 (Jan 23, 2019)

I had a FX 8320 before I got Ryzen and every piece of software I used told me it was 8 cores. It was also faster than the 1090T (using 2 extra cores).


----------



## Franzen4Real (Jan 23, 2019)

Vya Domus said:


> By the way has anyone filed a lawsuit yet on every GPU maker out there for marketing their products as having thousands of "cores" ?



Vya, you just found our golden parachute... let's get this rollin'!$!$


----------



## GoldenX (Jan 23, 2019)

Is there any legal action about Intel and they stock heatsinks thermal throttling?


----------



## thebluebumblebee (Jan 23, 2019)

When Bulldozer came out, AMD expected the computing world to move in a (much) different direction.  They took a gamble and lost. From July 2006:


> Let's look at this long term, say five or so years, the design cycle of a modern CPU. As we've noted earlier, the X86 CPU is about *to take a radical turn*, and the designs you will see at the turn of the decade won't resemble anything you see now. What do we mean by that? *Mini-cores and Larrabee.*



If I understand the legal process correctly, this means that discovery will now take place, which means that AMD has to turn over their internal communications during this time.  If it's found that there was concern raised about calling it an 8 core CPU, then that could be very damaging to AMD's argument.


----------



## danbert2000 (Jan 23, 2019)

The problem is that AMD made a design that was just hyperthreading with an extra integer unit thrown in. So technically, it is more capable than just having two execution states for one execution engine (containing an FPU and IU), since two threads can technically run at the same time, but if both threads need the FPU, then it is basically back to a multithreaded single core.

I think they may have a case in that early processors didn't even have an FPU, and were still processors. So it is technically an eight core integer CPU, and a four core floating point CPU. So you technically have eight cores that could run at once. It will depend on how much a modern processor design matters, as AMD didn't include any caveats in their marketing for the FX series to indicate that it wasn't always going to run 8 threads simultaneously. And in my personal opinion it was not correct to call them 8 core processors. They should have just called them 4 module processors, or made clear it was 8 integer cores and would perform at half speed for FP math. I wouldn't be surprised if AMD loses. I don't consider them 8 core processors since they aren't 8 core all the time.

Maybe the most damning thing is that AMD now sells 8 core processors that actually do have the FPU and IU per core, and 4 core processors with SMT that are 4 core/8 thread. In a way, that's admitting that the FX core terminology was a load of shit the whole time.


----------



## FordGT90Concept (Jan 23, 2019)

Totally called it back in that old thread:


FordGT90Concept said:


> I'd argue that the word "core" explicitly means independence to the public.  To say otherwise, is to let AMD define the word in a way that is inconsistent with competitor offerings and even their own previous offerings.


Just needs to append "and current offerings" to it. 



danbert2000 said:


> The problem is that AMD made a design that was just hyperthreading with an extra integer unit thrown in. So technically, it is more capable than just having two execution states for one execution engine (containing an FPU and IU), since two threads can technically run at the same time, but if both threads need the FPU, then it is basically back to a multithreaded single core.
> 
> I think they may have a case in that early processors didn't even have an FPU, and were still processors. So it is technically an eight core integer CPU, and a four core floating point CPU. So you technically have eight cores that could run at once. It will depend on how much a modern processor design matters, as AMD didn't include any caveats in their marketing for the FX series to indicate that it wasn't always going to run 8 threads simultaneously. And in my personal opinion it was not correct to call them 8 core processors. They should have just called them 4 module processors, or made clear it was 8 integer cores and would perform at half speed for FP math. I wouldn't be surprised if AMD loses. I don't consider them 8 core processors since they aren't 8 core all the time.
> 
> Maybe the most damning thing is that AMD now sells 8 core processors that actually do have the FPU and IU per core, and 4 core processors with SMT that are 4 core/8 thread. In a way, that's admitting that the FX core terminology was a load of shit the whole time.


Exactly.  In their engineering diagrams, they always prefaced "core" with "integer" so the eight were labeled as "integer core;" however, you look at the packaging and marketing material of the Bulldozer products, they say "core" exclusively.  AMD was misleading consumers by intentionally omitting "integer."

I am in complete agreement that they should have called them 4 module processors.  The public would have to learn and understand what module meant but module versus core is a very important distinction AMD choose not to make.


----------



## Shambles1980 (Jan 23, 2019)

Just isnt 8 cores and never was lol.. 
See any of my old posts about the issue.


----------



## FordGT90Concept (Jan 23, 2019)

kapone32 said:


> I had a FX 8320 before I got Ryzen and every piece of software I used told me it was 8 cores. It was also faster than the 1090T (using 2 extra cores).


Performance doesn't really matter.  It's definition of words in the eyes of the public and whether or not AMD used words to describe their product in a way that was misleading to the public.

The public understand "core" as independent processors.  That's not the case with AMD modules.


----------



## Shambles1980 (Jan 23, 2019)

there just wasn't enough components that make a core for you to make 8 cores..
There were enough components to make 4 cores, and there were extra bits that worked at the same time.. Not all operations could work at the same time though.

If you ever tried to pull a bulldozer apart and make 8 individual cores, you would only be able to make 4 and have a bunch of left over parts.

to me that always was, and always will be why i cannot and could never call them 8 core.

and the worst thing is. AMD were the ones to try and specify what a "core" was when intel released the pentium D.  Then they totally decided they didnt want to use that definition any more, and not only did they not want to use their definition they dint want to use any logical definition either.

i always called them modules. I just couldn't call them cores.

there were many a debate on these and other forums. and i genuinely didn't and still don't understand how any one can say they have 8 cores.
but i decided years ago it was better to just agree to disagree.

but in terms of a law case. 
I think the most damning thing for amd is that they genuinely defined what they thought a core was when intel released the pentium d chips.
And because they did that, they honestly cant expect to win a court case where they say People should define it as something diferent to what they them selfs defined them to be.


----------



## seronx (Jan 23, 2019)

FordGT90Concept said:


> The public understand "core" as independent processors.  That's not the case with AMD modules.


The public and industry understands a "core" as these components;
1. A Control Bus/Control Logic.
2. An Instruction Bus.
3. An Address/Data Bus which is usually connected to a Load/Store Unit.
4. A datapath, this the ALU/AGU.

The Bulldozer module has;
2 Retire Queues -> Instruction Bus.
2 Schedulers(etc componentry) -> Control Logic.
2 clusters of 2 ALU/2 AGLUs -> Superscalar datapath
2 Address/Data buses which interconnect to a Load/Store unit. -> Address/Data Bus
Thus,
2 Cores.

The Bulldozer module by industrial and educational definition is two real/processing/physical cores.

Front-end of the module <-- not part of the core.
FPU in the module <-- not part of the core.
Shared L2 cache unit in the module <-- not part of the core.

The cores in the Bulldozer module are as independent as any fully replicated microprocessor.


----------



## Shambles1980 (Jan 23, 2019)

1st google result :
"Multi *core* CPUs *have* an *FPU* per *core* "

like i said best to just agree to disagree..


----------



## seronx (Jan 23, 2019)

Shambles1980 said:


> 1st google result :
> "Multi *core* CPUs *have* an *FPU* per *core* "
> 
> like i said best to just agree to disagree..


Lets say I buy an x86 processor.  I vouch to have the FPU co-processor removed.

Do I have no cores?
or do I have one core?

Now, if I bought an x86 processor with two-cores.  Then, also have the FPU co-processor removed.

Do I have no cores?
or do I have two cores?

Then, I bought a 128-core soft processor.  Only the first 16-cores have FPUs.

Do I only have 16-cores?
or do I have 128-cores?


----------



## Shambles1980 (Jan 23, 2019)

according to convention. its 1 fpu per core.. so that answers your question i think..
its not a matter of how you want to describe it.. as stated above earlier its about conventional naming.

i could have a house and not have a roof. sure i can call it a house and, but unless i stated that it had no roof when i sold you the thing.. guess what you could sue me.


----------



## Melvis (Jan 23, 2019)

So from what I just read Windows is the problem? not the CPU. We all know once they patched Windows the performance of the FX line went up alot! so wouldnt that make it that AMD is correct?


----------



## Sindalis (Jan 23, 2019)

If you go back to the beginning of x86. CPU's were primarily integer based. A typical CPU would offload FPU operations to a separate floating point processor. 

It wasn't till much later, that a CPU package would have both the integer scheduler as well as the FPU as part of the same package, let alone same die. 

The Bulldozer architecture was well, objectively terrible, but what _software_ has to do to interact with it has nothing to do with what is or isn't a core.

A core can be simplified to how many integer units something has, FPU's are separate in x86 world. Given this, its an 8 core CPU. it just happens to have only 4 FPU co processors rather than 8 like other designs. 

Ryzen goes back to pairing one for one because that is what found worked better, but there is nothing to say it has to be that way. It just is.


----------



## FordGT90Concept (Jan 23, 2019)

Cores share nothing other than memory subsystems (because memory is directly associated with communication).  Try to split an AMD module and you'll end up with one functional thread and one thread that's waiting for a non-existent prefetcher.  Module is therefore a core a in a traditional sense--an independent processor.

No one is saying Bulldozer doesn't have 8 "integer cores," because it does, but it only has 4 "cores" (independent processors).





The only analog to Bulldozer's design, really, is UltraSPARC T1 which has 8 execution cores and a separate floating point core.




The vital distinction is that those 8 execution cores share absolutely nothing with each other other than floating point instructions being outsourced.




Bulldozer and sons share much more than that.




In fact, each iteration of the design, AMD split more and more functions to improve performance.  Gee, I wonder why? Maybe sharing so much stuff wasn't such a great idea after all?




Melvis said:


> So from what I just read Windows is the problem? not the CPU. We all know once they patched Windows the performance of the FX line went up alot! so wouldnt that make it that AMD is correct?


No, it's AMD saying Bulldozer has "8 cores" and that declaration is misleading to the public.  It's not that simple, and people that bought these processors are saying they were damaged because AMD mislead consumers into believing they got more than they did.


----------



## Melvis (Jan 23, 2019)

FordGT90Concept said:


> No, it's AMD calling saying Bulldozer has "8 cores" and that declaration is misleading to the public.  It's not that simple, and people that bought these processors are saying they were damaged because AMD mislead consumers into believing they got more than they did.



Well it is an 8core, im pretty sure 2 cores per module times 4 = 8cores, its pretty simple maths and from what I have read they are bitching about how it shows up in Windows 8/10 that it comes up as a 4core 8 threaded CPU.  Also lets go back a few yrs when the 8350 went against the i7 2600. If the FX was indeed a "4 core 8 threaded" CPU then there is no way in hell it would beat out a i7 2600 in multi threaded work loads but it did! ( i know because I own both) you would need 8 cores to beat said CPU even if the IPC was lower over all it was more powerful.


----------



## FordGT90Concept (Jan 23, 2019)

Melvis said:


> Well it is an 8core, im pretty sure 2 cores per module times 4 = 8cores, its pretty simple maths and from what I have read they are bitching about how it shows up in Windows 8/10 that it comes up as a 4core 8 threaded CPU.  Also lets go back a few yrs when the 8350 went against the i7 2600. If the FX was indeed a "4 core 8 threaded" CPU then there is no way in hell it would beat out a i7 2600 in multi threaded work loads but it did! ( i know because I own both) you would need 8 cores to beat said CPU even if the IPC was lower over all it was more powerful.


Even on the newest iteration of Bulldozer, the module is a fetcher short of two cores.  They are not independent, they can never be independent, therefore, a module for all intents and purposes is a core.  Sure, it has extra transistors in there to allow it to simultaneous multithread but doesn't change the fact the two integer cores are not inseparable and therefore, not cores (even UltraSPARC T1 passes this test).

Again, performance is largely moot.  This is about definitions.

Judging from the OP, the court has ruled in favor of the plaintiffs and against AMD; therefore, "modules" are "cores;" "integer cores" are not "cores."  Only way that changes at this point is if AMD challenges the decision, which they really shouldn't because the disconnect between engineering ("integer core") and marketing ("core") is damning for them.  False advertising could rope FTC into the lawsuit.


----------



## Shambles1980 (Jan 23, 2019)

honestly been here done that, wore the t-shirt, you just have to agree to dissagree, you can (and i did in the past) dissect it and show all the pics and do all the back an forth, but no one ever changes their minds...
the ones who think its 8 cores will find a way to say it's 8. the ones of us who dont think its 8 cores just have to repeat the same things for years on end and never get any where..

agree to dissagree is the only way forward here.

p.s 
you dont need a fpu for a cpu to work so i do get the argument.

 I also think windows scheduling made them worse than they should be.. (it wouldnt move fpu calculations to a module that was not doing fpu calculations.) But thats not windows fault either. the cpu told it it had 8 cores, so windows sent a fpu calculation to core 1 and a diferent task to core 2, and whammo botle neck. had to wait for the fpu to finish 1st.

you can blame windows for it if you want but if windows had moved fpus to indepenant modules rather than "cores" you still end up in the situation of If you have 4 simultnious fpu calculations and 4 other tasks. You effectivly only have 4 cores able to do any processing because they are all tied up with fpu calcs, and nothing else can be done till they are finished.
And thats just 1 issue. 

so even understanding the argument and only focusing on fpu's i still end up with only 4 processes able to run at 1ce.


----------



## FordGT90Concept (Jan 23, 2019)

Indeed, lest this thread turn into another 511 post thread like the last one.


----------



## cdawall (Jan 23, 2019)

FordGT90Concept said:


> Even on the newest iteration of Bulldozer, the module is a fetcher short of two cores.  They are not independent, they can never be independent, therefore, a module for all intents and purposes is a core.  Sure, it has extra transistors in there to allow it to simultaneous multithread but doesn't change the fact the two integer cores are not inseparable and therefore, not cores (even UltraSPARC T1 passes this test).
> 
> Judging from the OP, the court has ruled in favor of the plaintiffs and against AMD; therefore, "modules" are "cores;" "integer cores" are not "cores."  Only way that changes at this point is if AMD challenges the decision, which they really shouldn't because the disconnect between engineering ("integer core") and marketing ("core") is damning for them.  False advertising could rope FTC into the lawsuit.



Which definition of a core says a core must have a fetcher per core? This is what a huge portion of the argument will live on. 

Does each GPU "core" have a fetch? (this is me asking on that one I have not looked that hard into the design). If they do not does both AMD and nvidia need to pay out for misrepresenting the thousands of "cores" they claim a GPU has?

Right now AMD is betting on the original core design was one integer core was a core. FPU came later on, if anyone makes the argument for that then Intel and Motorola produced tons of processors that had zero cores.


----------



## Shambles1980 (Jan 23, 2019)

gpu and cpu cores are VERY different. i really shouldnt have to say that here..

its like saying If all cars have to have 4 wheels, what about mtorcycles?? are they not motorized vehicles now??

p.s

i know bad annalogy but what the hell. i already used up more thinking time than i should on this discussion.


----------



## Darmok N Jalad (Jan 23, 2019)

Bulldozer was a response to Netburst, a frequency-happy, ALU-heavy architecture with a weak FPU. Problem is, Netburst failed and was taken behind the barn just as Bulldozer launched. AMD’s design was years in the making, when Intel was taking about 10GHz processors by 2011. Had we all been running Netburst-optimized architecture, there’s no telling what we’d be looking at. Instead, Intel pivoted to high-IPC Core and that made Bulldozer an unoptimized bust.

For what it’s worth, this isn’t new. The i486SX was a i486DX with the FPU disabled, and there was such a confusing thing as a Core 2 Solo. Either way, this lawsuit is pretty late to the party!


----------



## seronx (Jan 23, 2019)

FordGT90Concept said:


> Try to split an AMD module and you'll end up with one functional thread and one thread that's waiting for a non-existent prefetcher.


Split Bulldozer Module;
2x 2K L2 BTB
2x 256K L1 BTB
2x Branch Predictor
2x 32 KB L1i
2x 16B Fetcher/Prefetcher
2x IBB/Pick
2x 2-wide decode
2x 2 ALU/2AGU
2x 1 FMAC+1 FMMX(FMISC/FSTORE)
2x LSU
2x 16 KB L1d
2x 1 MB L2

You can easily split an Bulldozer module and get two functional cores.  However, those two cores would utilize more space than the two-core module.  Which in turn would provide less performance than the Bulldozer module.


Darmok N Jalad said:


> Bulldozer was a response to Netburst, a frequency-happy, ALU-heavy architecture with a weak FPU.


Bulldozer underlined threading technique is a response to Netburst&Nehalem/Hyperthreading.  Architecturally the Bulldozer module is a successor to the K7/K8 core or a response to Pentium II Xeon/Core/Core 2.


----------



## cdawall (Jan 23, 2019)

Shambles1980 said:


> gpu and cpu cores are VERY different. i really shouldnt have to say that here..
> 
> its like saying If all cars have to have 4 wheels, what about mtorcycles?? are they not motorized vehicles now??
> 
> ...



Who decides that? They are still labeled as a core. If you are going to argue one core isn't a core then the definition needs to exist across the entire industry. You do not get to pick and chose who these things apply to so as terrible as your analogy was it is about perfect because it shows the basic misunderstanding that is created by a market that freely uses the term "core" to describe whatever they want.


----------



## mouacyk (Jan 23, 2019)

in the same clock cycle, how many instructions can it execute independently?


----------



## Shambles1980 (Jan 23, 2019)

cdawall said:


> Who decides that? They are still labeled as a core. If you are going to argue one core isn't a core then the definition needs to exist across the entire industry. You do not get to pick and chose who these things apply to so as terrible as your analogy was it is about perfect because it shows the basic misunderstanding that is created by a market that freely uses the term "core" to describe whatever they want.



probably the same people who decided minute and minute were 2 different things even though they are a description of a measurment  and yet they measure diferent thing entierly..




mouacyk said:


> in the same clock cycle, how many instructions can it execute independently?


depends on what its doing. and how its scheduled.  if it has 4 floating point calcs all alocated to 1 module each and 8 other tasks .. 
then it can do 4..
if it has 4 floating points alocated to 2 modules and 8 other tasts alocated to the other 2 modules. 
then it can do 6..
if it just had 8 instructions and no fp calcs to do.. 
then it could do 8.
if 1 fp calcs and 8 instructions 
it could do 7


----------



## cdawall (Jan 23, 2019)

Shambles1980 said:


> probably the same people who decided minute and minute were 2 different things even though they are a description of a measurment and yet they measure diferent thing entierly..



Those both have written definitions widely publicizing what exactly they are. They both also describe 1/16th of something. One a measurement in time the other a measurement of a degree. So no it really doesn't have a different description regardless of what it's usage was.

The definition of core for usage in a PC came from the idea that it was the central most important part of the computer. Don't take my word for it though lets look up that definition, 



			
				merriam-webster said:
			
		

> the central or most important part of something



So by that widely used definition of a core what exactly does AMD not have 8 of?


----------



## Makaveli (Jan 23, 2019)

lol jury of 12 computer illiterate people.

Just pay the money right now and don't waste any more time.


----------



## Shambles1980 (Jan 23, 2019)

cdawall said:


> So by that widely used definition of a core what exactly does AMD not have 8 of?



umm the missing parts?

any way im walking away.. feel free to use the way back machine to find all my answers to the questions you may have. then we can agree to disagree


----------



## FordGT90Concept (Jan 23, 2019)

cdawall said:


> Which definition of a core says a core must have a fetcher per core? This is what a huge portion of the argument will live on.


Going back to Athlon 64 FX60 and Pentium D.  All processors before and after Bulldozer fit the same norm of "core" = independence.  AMD is not free to redefine what is known and understood.



cdawall said:


> Does each GPU "core" have a fetch? (this is me asking on that one I have not looked that hard into the design). If they do not does both AMD and nvidia need to pay out for misrepresenting the thousands of "cores" they claim a GPU has?


GPUs are marketed by model, not architectural details like shader count.  GPUs are also not CPUs by design so similarities and differences are moot. 



cdawall said:


> Right now AMD is betting on the original core design was one integer core was a core. FPU came later on, if anyone makes the argument for that then Intel and Motorola produced tons of processors that had zero cores.


x87 was a co-processor much like the FPU in UltraSPARC.  The CPU core in x86 was complete--it shared nothing, just outsourced floating point instructions to the coprocessor.  Bulldozer's integer cores are far from complete as the diagrams show.

Said differently...
2 8086 processors can function with or without any 8087 coprocessors and, they *can* function physically separated.
2 UltraSPARC T1 cores can function with or without its FPU and, they *can* function physically separated.
2 Bulldozer integer cores can function with or without its FPU but both *cannot* function physically separated.


----------



## cdawall (Jan 23, 2019)

Shambles1980 said:


> umm the missing parts?



Which ones by that definition is it missing? I don't remember it listing a single requirement as to what makes up a core. That is a textbook, dictionary definition. 

As it stands right now there is not a textbook answer that says a core must have the parts as follows to be sold/marketed as a core. AMD internal technical documentation written by people with multiple PHD's has labeled each integer core inside of the AMD Bulldozer design as a single core to make a total of 8. They have immensely more schooling than myself and likely the people making the claims as to what is or is not a core. Who are we to second guess what their design deems is a core when the definition is more vague as the patent apple holds for the iphone.



FordGT90Concept said:


> Going back to Athlon 64 FX60 and Pentium D.  All processors before and after Bulldozer fit the same norm of "core" = independence.  AMD is not free to redefine what is known and understood.



Under the same notion that AMD added more independence of a core by integrating the memory controller they could remove pieces. A core could not function without multiple other not attached items in multiple designs. The common ideal would be a core can fetch, decode instruction, ALU operation, access memory, update registrar, update program counter. Each integer core can do that each clock cycle with the Bulldozer design. 




FordGT90Concept said:


> GPUs are marketed by model, not architectural details like shader count.  GPUs are also not CPUs by design so similarities and differences are moot.



Every single Nvidia GPU you buy has the number of CUDA Cores printed on the side of the box in the same way AMD printed the number of cores it has in it's CPU. AMD also openly publishes the number of compute cores it's GPU's contain. The functionality of all three widely vary. 




FordGT90Concept said:


> x87 was a co-processor much like the FPU in UltraSPARC.  The CPU core in x86 was complete--it shared nothing, just outsourced floating point instructions to the coprocessor.  Bulldozer's integer cores are far from complete as the diagrams show.



That was more to point out that the single FPU unit was mute as far as being a reason why it is only a "whatever" core CPU. Hard to share with anything when you are the only CPU on a board.


----------



## Shambles1980 (Jan 23, 2019)

cdawall said:


> Which ones by that definition is it missing? I don't remember it listing a single requirement as to what makes up a core. That is a textbook, dictionary definition.
> 
> As it stands right now there is not a textbook answer that says a core must have the parts as follows to be sold/marketed as a core. AMD internal technical documentation written by people with multiple PHD's has labeled each integer core inside of the AMD Bulldozer design as a single core to make a total of 8. They have immensely more schooling than myself and likely the people making the claims as to what is or is not a core. Who are we to second guess what their design deems is a core when the definition is more vague as the patent apple holds for the iphone.




like i said, amd defined what a core was in their oppinion. when the pentium d came out.. they werent happy it beat the 64 x2 to market.. so that kind of negates your argument a little because even by amd's deffinition they arent 8 cores. but then again they said that a pentium d wasnt dual core, but the 64 x 2 was..

we can dabble back and forth forever as to what you or i think a core is..
but when you hinge your argument on amd are better than us so they should define what a core is, and they had previously done that.. but the buldoser "cores" dont qualify..
I really dont see how you have an argument.


----------



## FordGT90Concept (Jan 23, 2019)

cdawall said:


> Every single Nvidia GPU you buy has the number of CUDA Cores printed on the side of the box in the same way AMD printed the number of cores it has in it's CPU. AMD also openly publishes the number of compute cores it's GPU's contain. The functionality of all three widely vary.


Tech specs, not unlike vehicles having fuel capacity figures.  They don't brandish it as being a major selling point like AMD does with the prominent display of "8-core" on the packaging...which is common with all CPU sales because it's a defining feature in this era.  A vehicle similarity would be 2WD or 4WD.  Something prominent to look at when comparing too similar vehicles that, as a result of that change, may perform quite different depending on conditions.


----------



## Metroid (Jan 23, 2019)

Few days ago I thought I was wrong when I said the 6/8 cores cpus amd launched few years ago were just a marketing gimmick, now we see this news  and the lawsuit. I wonder which one is right and if i was really wrong about it, some people here said it was real cores, I still wonder about if is true or not. It's all a mess.


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> like i said, amd defined what a core was in their oppinion. when the pentium d came out.. they werent happy it beat the 64 x2 to market.. so that kind of negates your argument a little because even by amd's deffinition they arent 8 cores. but then again they said that a pentium d wasnt dual core, but the 64 x 2 was..
> 
> we can dabble back and forth forever as to what you or i think a core is..
> but when you hinge your argument on amd are better than us so they should define what a core is, and they had previously done that.. but the buldoser "cores" dont qualify..
> I really dont see how you have an argument.



So you are saying that AMD can redefine and has redefined what a core is a total of 2 or 3 times now, but this last time it doesn't count and they cannot do that. The other times however? Those were perfectly fine.



FordGT90Concept said:


> Tech specs, not unlike vehicles having fuel capacity figures.  They don't brandish it as being a major selling point like AMD does with the prominent display of "8-core" on the packaging...which is common with all CPU sales because it's a defining feature in this era.  A vehicle similarity would be 2WD or 4WD.  Something prominent to look at when comparing too similar vehicles that, as a result of that change, may perform quite different depending on conditions.









Nvidia quite literally has the number of CUDA cores as the highest defining item when comparing a GPU within a series. I would say the first thing listed on their companies website would be the major selling point of the product.


----------



## FordGT90Concept (Jan 24, 2019)

So everyone should buy Vega 64 because it has 4096 "cores."   You know it doesn't work that way.  Again, "specs" aka details.  Cores for CPUs aren't details, they're defining features.  When people buy a GPU, they're not looking for cores, or clockspeed, or anything in particular (well maybe VRAM amount), they're looking at the model: e.g. GTX 1080.  Just go to Amazon or Newegg and look at what is in the title.  CPUs prominently advertise their core count where GPUs do not. From Newegg:





Take a step back and look at the bigger picture.  AMD was perfectly happy using the word "modules" to define the dual integer core package.  Why did they deviate from sticking "4 module" on their FX processors?  Because "module" isn't something most people understand but core is.  AMD didn't want to stick "4 core" on their boxes because they want to advertise that it has more than Intel's "4 core" processors.  So they went with "8 core," not because of the truthfulness of the declaration, but to make people looking at processors consider AMD's product over Intel's because "more is better."  That's what false advertising is though: declaring your product having more than it really does.


----------



## Shambles1980 (Jan 24, 2019)

cdawall said:


> So you are saying that AMD can redefine and has redefined what a core is a total of 2 or 3 times now, but this last time it doesn't count and they cannot do that. The other times however? Those were perfectly fine.


the only 1 here saying amd can define what a core is is you..
Its abundantly clear amd can and has repetedly changed their definition of "core" to suit marketing, and bamboozle customers.. which is the actuall issue here. and you even nye on admit it in the above quoted post..

and this is why i say we have to agree to disagree..
you just 100% argued your case away in 2 posts and yet im to continue debating??


----------



## cdawall (Jan 24, 2019)

FordGT90Concept said:


> So everyone should buy Vega 64 because it has 4096 "cores."   You know it doesn't work that way.  Again, "specs" aka details.  Cores for CPUs aren't details, they're defining features.  The reason why one processor is $50 and another is $10,000.  When people buy a GPU, they're not looking for cores, or clockspeed, or anything in particular, they're looking at the model: e.g. GTX 1080.
> 
> 
> Take a step back and look at the bigger picture.  AMD was perfectly happy using the word "modules" to define the dual integer core package.  Why did they deviate from sticking "4 module" on their FX processors?  Because "module" isn't something most people understand but core is.  AMD didn't want to stick "4 core" on their boxes because they want to advertise that it has more than Intel's "4 core" processors.  So they went with "8 core," not because of the truthfulness of the declaration, but to make people looking at processors consider AMD's product over Intel's because "more is better."  That's what false advertising is though: declaring your product having more than it really does.



Would you say that you purchased a 3584 cuda core GPU over a 2560 cuda core GPU, let us muddy that water a little further because nvidia calls two different things core in their own product so the GPU core is a 1080ti, but it has 3584 cuda cores. Which one is a core, which one is a definition of a core. Is it because people understand what the definition of a core is and are using that branding of what a core is to further sell their product instead of the truthfulness of the declaration? Or is it different because it is not CPU?



Shambles1980 said:


> the only 1 here saying amd can define what a core is is you..
> Its abundantly clear amd can and has repetedly changed their definition of "core" to suit marketing, and bamboozle customers.. which is the actuall issue here. and you even nye on admit it in the above quoted post..
> 
> and this is why i say we have to agree to disagree..
> you just 100% argued your case away in 2 posts and yet im to continue debating??



I am going to pull your verbatim words for this.



Shambles1980 said:


> amd defined what a core was in their oppinion



The last section of what you said does not negate what you said. AMD defined what a core was is the root of *your* statement, they are *your* words own them. AMD is a leader in this industry, they were then and they still are now. Their ability to adjust a definition to fit their end needs, does not make anymore of a difference to me than when they moved the memory controller from the chipset to the CPU to form an IMC. This was a further advancement in the industry. Definitions will change as products change. This has always been true for the tech industry.


----------



## ghazi (Jan 24, 2019)

This is like demanding that NVIDIA cease using the term "CUDA Core" because the "real core" is the SMX. The CPU has 8 integer processor cores, which should suffice considering that FPUs historically are not an integral part of a CPU, and can also process eight 128-bit floating point operations simultaneously.


----------



## Shambles1980 (Jan 24, 2019)

cdawall said:


> The last section of what you said does not negate what you said. AMD defined what a core was is the root of *your* statement, they are *your* words own them. AMD is a leader in this industry, they were then and they still are now. Their ability to adjust a definition to fit their end needs, does not make anymore of a difference to me than when they moved the memory controller from the chipset to the CPU to form an IMC. This was a further advancement in the industry. Definitions will change as products change. This has always been true for the tech industry.




cant even be botherd to dissect the 1st part.. but as for "advancements" you dont advance and then change back because the "advancment" was worse.. thats called regression.
you cant just sell iron as gold because you are an industry leader, then decide iron was junk so go back to using gold and expect the people who bought the iron not to complain you advertized it in a deliberately manipulative manner.

actually..
i will simply dissect the 1st part.
if i say
"buldoser has 8 cores in your oppinion."
Guess what that still means i dont agree, and still does not mean it has 8 real cores.


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> cant even be botherd to dissect the 1st part.. but as for "advancements" you dont advance and then change back because the "advancment" was worse.. thats called regression.
> you cant just sell iron as gold because you are an industry leader, then decide iron was junk so go back to using gold and expect the people who bought the iron not to complain you advertized it in a deliberately manipulative manner.
> 
> actually..
> ...



So are you saying an attempt to improve something failed? HOLD THE PRESSES. We know FX sucked. It doesn't change that they built it as an advancement in the industry. It failed it so they went a better route. In fact if you want to call if a 4 core processor to this date I do not believe it's multicore efficiency depending on workload has ever been bested. 

Also your agreement isn't a requirement for something to be true. Facts are true, opinions are opinions. Factually there is not a true definition of a core. There are tons of opinions, but may as well make assumptions at that point.


----------



## Vya Domus (Jan 24, 2019)

FordGT90Concept said:


> AWhy did they deviate from sticking "4 module" on their FX processors?



Because a "module" doesn't mean anything and it's not a term that can be used to describe the functionality of a CPU (go ahead and find me any computer architecture literature where "CPU modules" are used in this context aka describing microprocessor architecture). You are suggesting AMD should have used a term that's even more ambiguous and devoid of meaning. They only mentioned this terminology in the context of their own internal design .These notions were never meant to reach consumers or to be turned into some sort of industry standard, they didn't deviate from anything.

I'll say it again, the traditional CPU core design has been dead for decades. No matter how much will the plaintiffs struggle to find footing in this argument there is simply no modern analogue that they can adhere to.


----------



## FordGT90Concept (Jan 24, 2019)

cdawall said:


> Would you say that you purchased a 3584 cuda core GPU over a 2560 cuda core GPU, let us muddy that water a little further because nvidia calls two different things core in their own product so the GPU core is a 1080ti, but it has 3584 cuda cores. Which one is a core, which one is a definition of a core. Is it because people understand what the definition of a core is and are using that branding of what a core is to further sell their product instead of the truthfulness of the declaration? Or is it different because it is not CPU?


May have missed the edit but the difference is core counts are prominently advertised for CPU sales but it is not for GPUs.  It's something directly linked to buying decisions so what it means becomes very important in terms of false advertising claims.  Athlon 64 X2 was advertised as 2-core, X4 as 4-core, X6 as 6-core; Ryzen 2700X as 8-core; i7 920 as 4-core, Core 2 Duo as 2-core, and so on.  Then we get to Bulldozer, Steamroller, and Piledriver: 8-core*.  The norm was established by AMD and maintained by AMD for many years then AMD marketeers decided to call something that was a whole now only a part of the whole.  How is that not false advertising?

* integer cores


----------



## Aquinus (Jan 24, 2019)

My god, ffs. This stupid debate again? This is like the "Warning: Contents Hot" warning on coffee cups. What do they demand, the ALU and FPU counts be presented on the product packaging? You know what, lets just require the packaging list out every transistor and it's usage. That will clearly clarify things and will make sense to 99% of consumers, right?

I'm sorry to say it, but when consumers, generally speaking, don't know what's even inside a CPU or how it works, they're not really giving two shits weather or not the FPU is shared, what it's width is, or if it's two FPUs slapped together with FMA. If you try to explain floating point versus fixed point math to someone and the situations in which they're used and how it impacts performance, most people's eyes will glaze over because they don't know what the hell you're talking about. AMD needs to dumb it down to language that a typical consumer can understand. This isn't false advertising. This is someone who is still butt hurt over AMD producing a garbage CPU and using it as an opportunity to make some money.

We already know the FX CPUs where garbage. We don't need to dwell over that, but when push comes to shove, you can have a CPU without floating point units, you can't have a CPU without ALUs and AGUs.

...by the way, 2012 called. It wants its CPU back.


----------



## FordGT90Concept (Jan 24, 2019)

Vya Domus said:


> Because a "module" doesn't mean anything and it's not a term that can be used to describe the functionality of a CPU (go ahead and find me any computer architecture literature where "CPU modules" are used in this context aka describing microprocessor architecture). You are suggesting AMD should have used a term that's even more ambiguous and devoid of meaning. They only mentioned this terminology in the context of their own internal design .These notions were never meant to reach consumers or to be turned into some sort of industry standard, they didn't deviate from anything.
> 
> I'll say it again, the traditional CPU core design has been dead for decades. No matter how much will the plaintiffs struggle to find footing in this argument there is simply no modern analogue that they can adhere to.


AMD created something unique and described it with a word that is suitable.  AMD talked about it extensively. If the design was successful and other manufacturers turned to it, "modules" would slowly replace "cores" as what people looking towards when making a purchasing decision.  Simply by distinguishing the name, AMD would incite people to research the difference so there wouldn't be so much confusion and misunderstanding.

AMD defined what a "core" was less than a decade before AMD debuted the "module."  If they could do it once, they could do it again.



ghazi said:


> This is like demanding that NVIDIA cease using the term "CUDA Core" because the "real core" is the SMX. The CPU has 8 integer processor cores, which should suffice considering that FPUs historically are not an integral part of a CPU, and can also process eight 128-bit floating point operations simultaneously.


If you want to get technical, CPUs should be advertised by thread count rather than core/module count.  The different ways to multithread though (there's 4 way, 2 way, and 1 way if not more), makes that a sketchy proposition.


----------



## cdawall (Jan 24, 2019)

FordGT90Concept said:


> AMD defined what a "core" was less than a decade before AMD debuted the "module." If they could do it once, they could do it again.



They did. With FX they redefined what a core was. Like you said if they did it once they can do it again.


----------



## FordGT90Concept (Jan 24, 2019)

Aquinus said:


> My god, ffs. This stupid debate again? This is like the "Warning: Contents Hot" warning on coffee cups. What do they demand, the ALU and FPU counts be presented on the product packaging? You know what, lets just require the packaging list out every transistor and it's usage. That will clearly clarify things and will make sense to 99% of consumers, right?
> 
> I'm sorry to say it, but when consumers, generally speaking, don't know what's even inside a CPU or how it works, they're not really giving two shits weather or not the FPU is shared, what it's width is, or if it's two FPUs slapped together with FMA. If you try to explain floating point versus fixed point math to someone and the situations in which they're used and how it impacts performance, most people's eyes will glaze over because they don't know what the hell you're talking about. AMD needs to dumb it down to language that a typical consumer can understand. This isn't false advertising. This is someone who is still butt hurt over AMD producing a garbage CPU and using it as an opportunity to make some money.
> 
> ...


We wouldn't be having this conversation if AMD put "4 module" or "8 integer core" on the box instead of "8 core."



cdawall said:


> They did. With FX they redefined what a core was. Like you said if they did it once they can do it again.








core = independent CPU

Always was, always will be*.

* Except Bulldozer, Steamroller, and Piledriver but AMD is about to get bitch slapped for that mistake.


AMD made Microsoft count sockets instead of processors because each socket could house more than one processor (described as a core).  It is accurate to describe 2700X as an 8 processor product.  It is inaccurate to describe FX-8350 as an 8 processor product because there's only 4 independent processors in it.


----------



## Vya Domus (Jan 24, 2019)

FordGT90Concept said:


> If the design was successful and other manufacturers turned to it, "modules" would slowly replace "cores" as what people looking towards when making a purchasing decision.



You're now speculating what could have been in an alternate future ? You're just really off the tracks with your argumentation, it's time to stop.



FordGT90Concept said:


> core = independent CPU



I could've very easily disabled 1 core from each "module" on my FX 6300 and guess what Windows would boot just fine and software ran as it should, floating point functionality still intact. How could that have worked if Piledriver didn't have independent cores ? What am I missing ? Can you still not see that your assertion that something like the 8350 didn't have 8 independent core is plain and simple wrong ?


----------



## eidairaman1 (Jan 24, 2019)

qubit said:


> Hopefully this lawsuit will discourage AMD from using such a cludgy, low performance compromised design in the future.



They already learned hence Zen


----------



## cdawall (Jan 24, 2019)

FordGT90Concept said:


> core = independent CPU
> 
> Always was, always will be*.
> 
> * Except Bulldozer, Steamroller, and Piledriver but AMD is about to get bitch slapped for that mistake.



How many clock cycles would it take for an BD module to process two single cycle cost integer math tasks.

How much is the multicore speedup for integer math tasks between a 4 module AMD is it around 3.xx or 7.xx? Now compare that to a traditional 4 core setup. 

In these specific scenarios it is quite easy to see any and all argument to say that the AMD design act as any standard 8 core unit would. Just because single threaded performance was dreadful, doesn't have anything to do with it scaling linear across all 8 cores available assuming integer calculations.


----------



## ghazi (Jan 24, 2019)

FordGT90Concept said:


> If you want to get technical, CPUs should be advertised by thread count rather than core/module count.  The different ways to multithread though (there's 4 way, 2 way, and 1 way if not more), makes that a sketchy proposition.



Core count is a more accurate predictor of performance than thread count, and also is a term that common people are familiar with. Even in the case of Bulldozer, the 8-core chips scaled around ~6.7x in multithreaded workloads -- closer to 8 than 4, unlike quad-cores with SMT that don't do much better than 5x.



cdawall said:


> How many clock cycles would it take for an BD module to process two single cycle cost integer math tasks.



Along with two 128-bit single cycle FP instructions...


----------



## Shambles1980 (Jan 24, 2019)

how many cycles would bulldozer take to do 4x 256 fp calcs and 4 single cycle tasks of any kind ? (8 total tasks)


----------



## eidairaman1 (Jan 24, 2019)

nickbaldwin86 said:


> If AMD wins then they have not learn what they did isn't ok. (If that fact be true). the money just goes to the lawyers and AMD doesn't get to keep money that they wrongfully took ie falsely sold a product.
> 
> it is a loose loose really but either way hopefully AMD has learned something from this



Amd already learned hence why the Zen Arch


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> how many cycles would bulldozer take to do 4x 256kbit fp calcs and 4 single cycle tasks of any kind ?



We aren't talking about floating point calculations. The point is mute. FP does not have to exist for a core in any sense of the word.


----------



## Shambles1980 (Jan 24, 2019)

cdawall said:


> We aren't talking about floating point calculations. The point is mute. FP does not have to exist for a core in any sense of the word.


you fail to see the issue, or why there is even a law suit.

look at it like this if amd were right and the rest of us were wrong and there was never an issue.. well this thread wouldnt even exist.

hell if we were all wrong. amd wouldnt have had to beg ms to treat 1 module as a single core and the second "core" in that module as little more than hyper threading to prevent the bottle necks because 1 module couldnt do the same workas 2 cores when 2 actuall cores could.

you cant just sell people a bycicle without a front wheel and say it works fine, then after ppl complain say well you should know we meant you need to do a wheelie all the time.


----------



## Vya Domus (Jan 24, 2019)

Shambles1980 said:


> ms to treat 1 module as a single core and the second "core" in that module as little more than hyoer threading to prevent the bottle necks because 1 module couldnt do 2 processes at the same time when 2 actuall cores could.



What ? You are seriously out of touch with the subject.


----------



## Shambles1980 (Jan 24, 2019)

Vya Domus said:


> What ? You are seriously out of touch with the subject.



they genuinly did ask ms to re work how the processor was scheduled. and the only way to do that was to treat each module as 1 core with ht. (use a module 1st and only use the second "core" of the module if all other modules were in use.

and they did that because one module cannot do the same work as 2 real cores, which is also why zen uses real cores now.


----------



## eidairaman1 (Jan 24, 2019)

Ok no more pointless arguing.










4 module, each module has 2 cores sharing resources.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> they genuinly did ask ms to re work how the processor was scheduled. and the only way to do that was to treat each module as 1 core with ht. (use a module 1st and only use the second "core" of the module if all other modules were in use.
> 
> and they did that because one module cannot do the same work as 2 real cores, which is also why zen uses real cores now.



Actually, that was only part of it and it's up to the OS to schedule tasks for the CPU, not the hardware. You do realize that the two integer cores also shared some other parts, such as the L2 cache. Switching between modules takes a performance impact because cache for the task at hand isn't going to necessarily be available at that level on another core in another module, in fact it's won't be. It's cheaper to switch to a core with a shared cache because it doesn't have to dive into L3 or memory to get the data that's already resident in the L2 of a particular module. From a performance standpoint, context switching to a core on the same module is less expensive than switching to  a core in another module. This isn't just about diving up the load between the modules, but making sure tasks stay where they'll run fastest, which means not scheduling them to just any core that's available.

Also, just because it doesn't scale perfectly doesn't mean it's not two different cores. Two lite cores are still two cores.


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> you fail to see the issue, or why people there is even a law suit.



If that is your argument that the single FPU per module, then I guess the 486SX isn't a CPU at all. It could do exactly 0 FP calculations total.

I absolutely see the issue. AMD changed what a portion of people considered to be a core. The IEEE would be pretty openly considered the subject matter experts on all things electrical correct? With its 420000 members?






Because they signed of on the verbiage of 2-core module for chip-level multithread or CMT as AMD labeled it for the Bulldozer design. If this lawsuit makes it to fruition that on its own should have it dismissed. The experts across the board approved the phrasing. 

Here are a couple of IEEE documents for you to read on the subject

https://ieeexplore.ieee.org/document/6060836

This is from all the way back in 2010, where yet again BD is referenced openly in IEEE publications as using cores. This even states how the cores are sharing resources.



> Just adding traditional cores isn’t going to be enough, says AMD’s Moore. The scheme may have saved the power-versus-performance curve for a time, but it won’t do so forever. “These days, each core is only getting 8 or 10 watts,” he says. “In some sense we’re running back into that power wall.” With its new Bulldozer architecture, AMD has managed to buy some breathing room by finding a set of components that the cores can share without seriously degrading their speed. But even so, Moore’s best guess is that 16 cores might be the practical limit for mainstream chips.



https://spectrum.ieee.org/semiconductors/processors/multicore-cpu-processor-proliferation


----------



## Shambles1980 (Jan 24, 2019)

you genuinly think that quoting the claims of the company that is in court for lying is the best way to prove they were not lying??
i cant even begin to tell you how rediculous that is.

Like i keep saying agree to disagree but if i ever want to sell something thats missing bits and does not work as intended il let you know.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> you genuinly think that quoting the claims of the company that is in court for lying is the best way to prove they were not lying??


IEEE is not AMD.


----------



## Shambles1980 (Jan 24, 2019)

Aquinus said:


> IEEE is not AMD.


1st line of the quote
"Just adding traditional cores isn’t going to be enough, says AMD’s Moore. "

which Also right there says they arent cores.  AMD said they arent cores right there in that stupid thing you just quoted.

oh and the paper is for a "module" not a "core"

All the evidence you bring just contradicts what you say.. and yet you still say it!


----------



## rvalencia (Jan 24, 2019)

londiste said:


> Even Execution Unit or Integer Unit does not necessarily mean the same thing across different architectures. For example, Bulldozer Integer Unit had 2 ALUs (Arithmetic Logic Unit) and 2 AGUs (Address Generation Unit) while Zen's Integer Unit has 4 ALUs (even though with a bit more resticted set of operations if I remember correctly) and 2 AGUs. Zen core has effectively the same integer calculation capacity in its Integer Unit that Bulldozer has.


Bulldozer module couldn't allocate most of it's four ALU and four AGU resource towards a single "uber" thread. 

For integers, typical hyper-threading CPU has strong and weak threads.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> 1st line of the quote
> "Just adding traditional cores isn’t going to be enough, says AMD’s Moore. "
> 
> which Also right there says they arent cores.  AMD said they arent cores right there in that stupid thing you just quoted.
> ...


You're the only person I quoted, bub. I'm not @cdawall. Also IEEE has members from just about every major hardware vendor.

Gimme your keys, @Shambles1980. You're drunk.


----------



## Shambles1980 (Jan 24, 2019)

Aquinus said:


> You're the only person I quoted, bub. I'm not @cdawall. Also IEEE has members from just about every major hardware vendor.



so you just gonna ignore the quote was actually from amd, and the paper is for modules not cores. and just pretend that amd didnt say they were not cores in the actuall thing being used to prove they are cores and just keep on going?

right fine i guess, not much i can do in the light of that.

although i will admit i thought you were the one that quoted it, so il confess to that.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> so you just gonna ignore the quote was actually from amd, and the paper is for modules not cores. and just pretend that amd didnt say they were not cores in the actuall thing being used to prove they are cores and just keep on going?
> 
> right fine i guess, not much i can do in the light of that.


That's right. A module isn't a core. It has a lot more than a single core would typically ever have. My point stands.


Aquinus said:


> Gimme your keys, @Shambles1980. You're drunk.


----------



## Shambles1980 (Jan 24, 2019)

Aquinus said:


> That's right. A module isn't a core. It has a lot more than a single core would typically ever have. My point stands.


and less than 2 cores would have, point is mute.

no one complained for them bing modules.. the issue is they call them 8 cores when they are demonstrably not.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> and less than 2 cores would have.


I thought I had addressed that already. Perhaps you should actually read what people have been saying to you.


Aquinus said:


> Two lite cores are still two cores.


The integer cores had fewer ALUs and AGUs than a Phenom 2 core did. They were literally two lesser cores for the price of 1, not two phenom cores. The result was less performance per core.

Edit: That means fewer instructions per clock per core compared to its predecessor.


----------



## Shambles1980 (Jan 24, 2019)

maybe they should have labled them as lite... oh wait thats the point.

I dont mind them calling them Lite cores. or integer cores or imaginary cores.. hell they could have called them anything they wanted aslong as they defined the difference to the avarage idiot on the street
but they didnt sell them like that which is the issue.
I dont see how you cannot comprehend that.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> maybe they should have labled them as lite... oh shit wait


Maybe Intel should have labeled Haswell "extra beefy" when they added some. Keep reading, you're not done.


Aquinus said:


> My god, ffs. This stupid debate again? This is like the "Warning: Contents Hot" warning on coffee cups. What do they demand, the ALU and FPU counts be presented on the product packaging? You know what, lets just require the packaging list out every transistor and it's usage. That will clearly clarify things and will make sense to 99% of consumers, right?
> 
> I'm sorry to say it, but when consumers, generally speaking, don't know what's even inside a CPU or how it works, they're not really giving two shits weather or not the FPU is shared, what it's width is, or if it's two FPUs slapped together with FMA. If you try to explain floating point versus fixed point math to someone and the situations in which they're used and how it impacts performance, most people's eyes will glaze over because they don't know what the hell you're talking about. AMD needs to dumb it down to language that a typical consumer can understand.


----------



## Shambles1980 (Jan 24, 2019)

i dont disagree...
But there is a "TRADITIONAL CORE" what people are used to. even amd admit it in the paper above.
Then there are modules And you can call whats in those anything you want to call them aslong as you make a destinction, Which amd briefly did.

the issue is they decided to just go on the "look at us 8 reall cores" marketing thing. I was always against it and spoke out at the time.
Would i try and sue them for it?? no because I knew what to expect..
Would my family have known better?? hell no.
Should people who were duped be allowed to try and get some justice?? yes..

Should this law suit continue?? Yes..
If for no other reason that for mfrs to just accept they cant just trick the uneducated.
You havd vista ready and vista capable years ago that ended up in the same situation as this. and thats even less clear cut.

i have no doubt in my mind if moduels had been super effective, then every one would have moved on to call them cores. But they werent and so we didnt and we wont.


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> and less than 2 cores would have, point is mute.
> 
> no one complained for them bing modules.. the issue is they call them 8 cores when they are demonstrably not.



Except for the time they showed identical if not better scaling than any other 8 core product on the market when placed into a multithreaded environment. 



Aquinus said:


> You're the only person I quoted, bub. I'm not @cdawall. Also IEEE has members from just about every major hardware vendor.



With 420,000 members they have more than one 



Shambles1980 said:


> 1st line of the quote
> "Just adding traditional cores isn’t going to be enough, says AMD’s Moore. "
> 
> which Also right there says they arent cores.  AMD said they arent cores right there in that stupid thing you just quoted.
> ...



I take it you actually read neither of the articles I linked. The second article speaks about the natural evolution of multicore designs as was seen in 2010. It brings up GPU cores, which apparently aren't cores, it brings up CELL cores, which apparently aren't all real cores and mentions how this is how the evolution of things is going. The article did falsely say Bulldozer would be great (paraphrasing), but a lot of what they said is absolutely holding true. We have mixed cores in so many different devices and Bulldozers design absolutely is a part of that. 

Here is another quote, since you didn't bother to read the first article linked which was written by no less than 8 PhD holding people from various companies including AMD, HP, HAL, etc. 



> The module includes two independent integer cores but shares the fetch, decode, floating-point, and L2 cache units to maximize single-threaded performance and multi-threaded throughput while significantly improving power and area efficiency compared to fully replicated CPU cores.



I want you to read that out loud to yourself. This is merely from the abstract. I would link to the actual article sections, but seeing how the conversation is going I could link a McDonald's menu and you would argue about it not being real fast food or some nonsense.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> Should this law suit continue?? Yes..
> If for no other reason that for mfrs to just accept they cant just trick the uneducated.


Except it's not a trick. You literally got 8 shitty cores instead of 4 or 6 decent ones.


----------



## Shambles1980 (Jan 24, 2019)

Aquinus said:


> Except it's not a trick. You literally got 8 shitty cores instead of 4 or 6 decent ones.


you got 4 decent cores and some other bits that could usually but not always do tasks in conjunction

@cdawall read that out loud and it says "integer cores" and "compared to fully replicated CPU cores "
like i said they can call them "integer, imaginary, lite " whatever they want as long as they define it..

But loe oand behold it didnt say "8 integer cores, not traditional" on the box.
Youd think theyd be yelling that from the roof tops if they were as good or better. Or that they wouldnt bother if they were trying to trick consumers.


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> you got 4 decent cores and some other bits that could usually but not always do tasks in conjunction



Those same bits don't even exist in multiple histories of multiple CPU's that were standalone. Per the actual IEEE tech publication for bulldozer each module consists of 2 integer cores with some shared resources.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> you got 4 decent cores and some other bits that could usually but not always do tasks in conjunction


The only SMT-esqe part about this is the FPU... and now we're going full circle.


----------



## cdawall (Jan 24, 2019)

Shambles1980 said:


> you got 4 decent cores and some other bits that could usually but not always do tasks in conjunction
> 
> @cdawall read that out loud and it says "integer cores" like i said they can call them "integer, imaginary, lite " whatever they want as long as they define it..
> 
> ...



Traditional cores do not have an FPU. I honestly don't know why that is difficult to understand, but since you cannot get that through your thick skull I guess you win.


----------



## Aquinus (Jan 24, 2019)

Shambles1980 said:


> Or that they wouldnt bother if they were trying to trick consumers.


A typical consumer doesn't even know what a FPU is or what it does, man. Marketing has to be simple.


----------



## cdawall (Jan 24, 2019)

Actually. I am fixing this for myself. Guy can't figure out that an integer calculation and floating point calculation are not the same thing. This is not worth my time. Hope you folks had a good read.


----------



## Aquinus (Jan 24, 2019)

cdawall said:


> Actually. I am fixing this for myself. Guy can't figure out that an integer calculation and floating point calculation are not the same thing. This is worth my time. Hope you folks had a good read.


You are a wise man.


----------



## Shambles1980 (Jan 24, 2019)

cdawall said:


> Traditional cores do not have an FPU. I honestly don't know why that is difficult to understand, but since you cannot get that through your thick skull I guess you win.



ok tell me what part of this you dont understand..
Bulldozers were slow. because each module did not act like 2 cores in windows.
ms had to change the sceduler to eliviate the issue.
amd call the modules Integer cores and define catagorically that they are not actuall cores.
amd later abandon the moduels thing because its just worse than using reall cores.

BUT amd advertized bulldozer as having 8 reall cores.
people were upset and so started a law suit.

all the evidence you have presented shows catagorically that amd didnt think they were traditional cores. didnt call them traditional cores, defined them as diferent to traditional cores and they cut parts out to reduce power.
And yet advertized them as cores.


----------



## FordGT90Concept (Jan 24, 2019)

Vya Domus said:


> I could've very easily disabled 1 core from each "module" on my FX 6300 and guess what Windows would boot just fine and software ran as it should, floating point functionality still intact. How could that have worked if Piledriver didn't have independent cores ? What am I missing ? Can you still not see that your assertion that something like the 8350 didn't have 8 independent core is plain and simple wrong ?


Pretty sure you can't.  Bulldozer and sons power control scope is limited to modules.  A module can soft-shutdown an idle integer core to conserve power but that's not something software has any control over.  An independent core can be completely powered off.



cdawall said:


> How many clock cycles would it take for an BD module to process two single cycle cost integer math tasks.
> 
> How much is the multicore speedup for integer math tasks between a 4 module AMD is it around 3.xx or 7.xx? Now compare that to a traditional 4 core setup.
> 
> In these specific scenarios it is quite easy to see any and all argument to say that the AMD design act as any standard 8 core unit would. Just because single threaded performance was dreadful, doesn't have anything to do with it scaling linear across all 8 cores available assuming integer calculations.


It seems ghazi brushed on the point here:


ghazi said:


> Core count is a more accurate predictor of performance than thread count, and also is a term that common people are familiar with. Even in the case of Bulldozer, the 8-core chips scaled around ~6.7x in multithreaded workloads -- closer to 8 than 4, unlike quad-cores with SMT that don't do much better than 5x.


16% slower than an independent 8-core because of shared components.  If I had a Bulldozer, I'd want my 16% back that I was promised.  On the flipside, SMT processors promise you 100% but you're getting 125%.  That's a bargain, not theft.  AMD could have marketed 4-module processors as having 34% better SMT performance than Intel's 4-core processors but, no, they didn't do the smart and honest thing.  Sad.


----------



## Darmok N Jalad (Jan 24, 2019)

Personally, I think this is going to be hard to prove. AMD can argue that each integer core was fully independent of the other, despite being part of the same module. Each had its own integer scheduler, register file and 16KB L1 data cache. Yes, they shared an FPU core, but that FPU was capable of handling 2 threads, and both integer cores could access both threads. It was certainly a unique design, but I think the only thing they could prove is that it was a bad design, but we don’t exactly need the court of law to prove that one. 

Heck, Atom was launched as an in-order execution CPU, something we hadn’t seen from Intel since before Pentium Pro. For best performance on a Silvermonte, you needed to target an x86 architecture from before 1995.


----------



## cdawall (Jan 24, 2019)

Aquinus said:


> You are a wise man.



Like you said the discussion became a circular argument. That is not worth the time of day. The documentation was provided and approved by IEEE in 2012. The processor can complete 8 simultaneous integer core problems per clock cycle and the design existed to try and reduce the foot print of a core. 



FordGT90Concept said:


> Pretty sure you can't.  Bulldozer and sons power control scope is limited to modules.  A module can soft-shutdown an idle integer core to conserve power but that's not something software has any control over.  An independent core can be completely powered off.



I still have an FX9370 and CHV. You absolutely can power off 1 core in a module. I could boot the chip 4 modules and 4 cores right now.



FordGT90Concept said:


> It seems ghazi brushed on the point here:
> 
> 16% slower than an independent 8-core because of shared components.  If I had a Bulldozer, I'd want my 16% back that I was promised.



This is a review for the 9700K and 9900K. I will use cinebench as a basis for this. Now mind you this is the absolutely latest Intel product.

https://www.techspot.com/review/1730-intel-core-i9-9900k-core-i7-9700k/

The 9700K is an 8 core 8 thread CPU. It scores 214 points for the single threaded CB test, it scores 1513 points for the multithreaded test. That is a 7.07x speed up. In 2012 AMD was able to pull off a 6.7x speed up in that same benchmark and you are going to sit there and tell me it only had 4 cores?


----------



## FordGT90Concept (Jan 24, 2019)

cdawall said:


> I still have an FX9370 and CHV. You absolutely can power off 1 core in a module. I could boot the chip 4 modules and 4 cores right now.


Fantastic! Still waiting on numbers on this thread:
https://www.techpowerup.com/forums/...ount-on-bulldozer.217327/page-21#post-3535907

Modules use less power fully powered than two independent cores fully powered; however, one independent core will use less power than a semi-powered down module.



cdawall said:


> The 9700K is an 8 core 8 thread CPU. It scores 214 points for the single threaded CB test, it scores 1513 points for the multithreaded test. That is a 7.07x speed up. In 2012 AMD was able to pull off a 6.7x speed up in that same benchmark and you are going to sit there and tell me it only had 4 cores?


It's ironic you mention the 9700K...a deliberately nerfed processor compared to one that isn't (other than having an unconventional design).  9900K is 9.48x using 8 independent cores versus allegedly "6.7x" using 8 shared cores. That's on the order of 41% improvement instead of 16% loss.  There's a reason why AMD dropped modules like it's hot and went SMT too.


----------



## ghazi (Jan 24, 2019)

FordGT90Concept said:


> It's ironic you mention the 9700K...a deliberately nerfed processor compared to one that isn't (other than having an unconventional design).  9900K is 9.48x using 8 independent cores versus allegedly "6.7x" using 8 shared cores. That's on the order of 41% improvement instead of 16% loss.  There's a reason why AMD dropped modules like it's hot and went SMT too.



To the contrary, the 9900K gets a ~19% improvement from its 8 virtual threads. If the FX were a 4-core, 8-thread CPU, its "virtual" (hardware) threads would give it a 68% improvement. That's more in-line with the performance uplift from fully independent cores than that of SMT. Let's also remember that fully independent cores don't scale totally perfectly either.


----------



## cdawall (Jan 24, 2019)

FordGT90Concept said:


> Fantastic! Still waiting on numbers on this thread:
> https://www.techpowerup.com/forums/...ount-on-bulldozer.217327/page-21#post-3535907
> 
> More like 2 modules and 4 integer cores.  The modules are going to use more power in a semi-powered down state than independent cores in a full power down state simply because a lot more transistors aren't being used.



I am curious how it will do. If I have time this weekend I will see if I can get it up and running again. I actually have been wanting to turn it into an XP box for some older games for a while. Have a pair of 7950's it is going to get stuffed into it. 




FordGT90Concept said:


> I'd rather trust my own program in the link above than Cinebench.  I know my program is extremely asynchronous, relies on ALU performance over FPU, and performance patterns fall exactly inline with expectations.
> 
> It's ironic you mention the 9700K...a deliberately nerfed processor compared to one that isn't (other than having an unconventional design).  9900K is 9.48x using 8 independent cores versus allegedly "6.7x" using 8 shared cores. That's on the order of 41% improvement instead of 16% loss.  There's a reason why AMD dropped modules like it's hot and went SMT too.



I specifically picked the 9700K, because I thought we were comparing apples to apples. That is an 8 core 8 thread CPU compared to an 8 core 8 thread CPU. If the argument is that they aren't cores, then that is absolutely A-OK, we can compare a 7700K for the 4 core 8 thread scaling vs 4 module 8 threads. 

https://techreport.com/review/31179/intel-core-i7-7700k-kaby-lake-cpu-reviewed/13

7700K pulls off 197 single threaded and 998 multithreaded for a 5.06x speed up. Again those 8 "shared" cores as you called them did 6.7x I would say if we were to purely compare HT vs CMT this particular application is showing substantial gains to CMT, almost at the same level as traditional cores. 

This trend actually got better with more cores added. The quad core dual module FX based stuff did not do as well per core, still heftily beat the intel HT offerings, but was not nearly as good as cores. 

So my personal A10-7800 ran 91 single and 308 multi 3.38x speed up (4/4)
The G4560 just a couple notches up ran 142 single and 352 multi 2.47x speed up (2/4)
Another random i3 6100 193 single and 491 multi 2.54 speed up (2/4)
and the 4/4 4690K 171 single and 646 multi 3.77 speed up (4/4)
another 6600K 193 single and 729 multi 3.77 speed up (4/4)

these are just yanked off of the CB thread

https://www.techpowerup.com/forums/threads/post-your-cinebench-score.213237/


----------



## FordGT90Concept (Jan 24, 2019)

ghazi said:


> To the contrary, the 9900K gets a ~19% improvement from its 8 virtual threads. If the FX were a 4-core, 8-thread CPU, its "virtual" (hardware) threads would give it a 68% improvement. That's more in-line with the performance uplift from fully independent cores than that of SMT. Let's also remember that fully independent cores don't scale totally perfectly either.


Hyperthreading and Zen: 19% improvement from juggling two threads per core across 8 cores.  When one thread hits a blocking state, it switches context to the other thread to maximize the usage of hardware resources.

Bulldozer, Piledriver, and Steamroller: 67% improvement from integrating two integer cores.  They should only theoretically block when either is faced with a major FPU instruction; however, there's no switching available to keep the integer cores fully tasked.  It gets more performance improvement because there's more transistors behind it but it cannot exceed 100% because it lacks integer core SMT.



cdawall said:


> I specifically picked the 9700K, because I thought we were comparing apples to apples. That is an 8 core 8 thread CPU compared to an 8 core 8 thread CPU. If the argument is that they aren't cores, then that is absolutely A-OK, we can compare a 7700K for the 4 core 8 thread scaling vs 4 module 8 threads.
> 
> https://techreport.com/review/31179/intel-core-i7-7700k-kaby-lake-cpu-reviewed/13
> 
> ...


My problem with all of this is I'm not sure how Cinebench even works.  Is it ALU heavy, FPU heavy, or a mixture of both?  Is it synchronous multithreading or asynchronous? From what I gather, it's a rendering benchmark which is FPU heavy.  Assuming that, it's good to see that Bulldozer's FPU can manage 83.75% but from your own numbers, you can clearly see that there's a significant difference between where Bulldozer performs compared to independent cores (e.g. 9700K at 88.375%), especially when considering that Bulldozer is getting 100% of possible threads, architecturally, compared to 9700K's 50% of possible threads architecturally.   Your figure of 7700K demonstrates that: 126.5% performance out of four independent cores. versus 83.75% out of eight integer cores or 167.5% out of four modules.

That's what I don't get: AMD could have owned the module argument.  167.5% per module is more attractive than 83.75% per "core."  They stabbed themselves in the back by calling them "cores" because it just doesn't stand up to the 120%+ that Hyper-Threading can do.  This is looking at it from the perspective of a customer comparing an "8-core" Intel/Zen to an "8-core" Bulldozer/Piledriver/Steam Roller.


----------



## NC37 (Jan 24, 2019)

Easy case to win. Just look at benchmarks. It beat i7s back then in multithreading. Pretty clear when you got into the heavy workloads that it wasn't a quad core. Physical cores always are better than SMT. Sure it sucked big time in single thread and everything else, but it definitely was an *8 core.


----------



## cdawall (Jan 24, 2019)

FordGT90Concept said:


> My problem with all of this is I'm not sure how Cinebench even works. Is it ALU heavy, FPU heavy, or a mixture of both? Is it synchronous multithreading or asynchronous? From what I gather, it's a rendering benchmark which is FPU heavy. Assuming that, it's good to see that Bulldozer's FPU can manage 83.75% but from your own numbers, you can clearly see that there's a significant difference between where Bulldozer performs compared to independent cores (e.g. 9700K at 88.375%), especially when considering that Bulldozer is getting 100% of possible threads, architecturally, compared to 9700K's 50% of possible threads architecturally. Your figure of 7700K demonstrates that: 126.5% performance out of four independent cores. versus 83.75% out of eight integer cores or 167.5% out of four modules.
> 
> That's what I don't get: AMD could have owned the module argument. 167.5% per module is more attractive than 83.75% per "core." They stabbed themselves in the back by calling them "cores" because it just doesn't stand up to the 120%+ that Hyper-Threading can do. This is looking at it from the perspective of a customer comparing an "8-core" Intel/Zen to an "8-core" Bulldozer/Piledriver/Steam Roller.



So you are calling a 5% difference between the 83% BD core for core and 88% coffee lake significantly more important why?

In the time frame from 2012 to to 2019 Intel was able to offer 5% better multithreading efficiency comparing core for core in what is considered a heavy workload. You are correct I don't know if it is alu or fpu heavy, but it performs very well for efficiency on both sides of the map.

Either way you cut this up either in 2012 they had nearly equaled Intel 2019 multithreading ability or in 2012 CMT so vastly outperformed both amds in replacement SMT and Intels HT it isn't even funny. Either way you chalk that up you are saying the chip performed admirably in this specific scenario. Now mind you I do get what you are saying with the 7700k holding a 126% per core efficiency, but it's per thread would be worse than bulldozer. That would be what that speed up shows. You can mix those numbers however you want, but the root of it doesn't change. Intels own 7700k when compared to a 9700k showed the same thing. 126% vs 88% when compared the same way. So why is it ok for Intels efficiency, but not ok for amd again you are comparing a 2012 product to 2018/2019 right now as well.


----------



## FordGT90Concept (Jan 24, 2019)

NC37 said:


> Easy case to win. Just look at benchmarks. It beat i7s back then in multithreading.


Because they were going against 4 cores.  AMD is still doing the same thing today but with 8 cores instead of 4 modules.



NC37 said:


> Pretty clear when you got into the heavy workloads that it wasn't a quad core.


But it's also clear it isn't an 8 core either.  AMD made a mistake not marketing them as 4 modules or 8 integer cores and they're liable to pay for it now.



NC37 said:


> Physical cores always are better than SMT.


No doubt but SMT increases efficiency of physical cores.  That's why almost all modern CISC architectures do it.



cdawall said:


> So you are calling a 5% difference between the 83% BD core for core and 88% coffee lake significantly more important why?


Because you're under tasking the Coffee Lake architecture.  100% load both, you're looking at 125% versus 83%.  That's the reason why Bulldozer/Piledriver/Steamroller didn't take mainframe marketshare by storm but Zen is.



cdawall said:


> Either way you cut this up either in 2012 they had nearly equaled Intel 2019 multithreading ability or in 2012 CMT so vastly outperformed both amds in replacement SMT and Intels HT it isn't even funny. Either way you chalk that up you are saying the chip performed admirably in this specific scenario. Now mind you I do get what you are saying with the 7700k holding a 126% per core efficiency, but it's per thread would be worse than bulldozer. That would be what that speed up shows. You can mix those numbers however you want, but the root of it doesn't change. Intels own 7700k when compared to a 9700k showed the same thing. 126% vs 88% when compared the same way. So why is it ok for Intels efficiency, but not ok for amd again you are comparing a 2012 product to 2018/2019 right now as well.


I'm not saying and never did say that CMT was a bad architecture.  AMD just went about describing it poorly to the public.  Think the Seagate lawsuit about the definition of "GB."  That's what this is fundamentally about but it's "core" instead.


Edit: Circling back to Cinebench, the fact 9700K is 12% loss in scaling, I'd say the multithreading code is either synchronous or has a lot of blocking scenarios.  Async code with little cross talk between threads should get damn close to 100%.  The fact SMT in the same test gives what is effectively a 37% uplift in performance proves it is not a good multithreading benchmark.


----------



## Athlonite (Jan 24, 2019)

I can remember years ago when first getting into PC's some motherboards for the 286 CPU had 2 sockets on them 1 for the x86 integer CPU and 1 for the x87 FPU side of things did it work without the x87 FPU yes was it slower without it yes but only in FPU intensive tasks ... So as far as I'm concerned any CPU that has 2 x86 compute units is a dual core CPU

1x Module = 2x Integer CPU cores + 1 FPU core
4x Modules = 8 Integer  CPU cores + 4 FPU cores

so technically an 8 core CPU if all you want to do is x86 integer operations


----------



## Patriot (Jan 24, 2019)

Midland Dog said:


> 8 alu from memory, for integer ops its an 8 core for floating point its a 4 core, simples, i personally would have called it an 8 thread cpu, not and 8 core. at the same time its up to the customer to do some research, as a quad core its decent perf but for an 8 core its kind of pathetic


Negative, for floating point it is an 8 core... it had a double wide floating point unit (AVX) that could operate 2x 128bit fmac at a time or 1 double wide.  The problem was the design just didn't work as designed and the shared scheduler hamstrung it.   With scheduler changes in windows it greatly improved and did fine on many multithreaded applications.  Just because it had a poor design and architectural bottleneck doesn't mean it isn't an 8 core.

" _C_-_Ray_, a simple raytracer designed to test the _floating_-point CPU _performance_ "






i7 990x 6c/12t  got 6x improvement.
fx8150 8c/8t got also 6x improvement.  No one is arguing its a failed architecture, but the lawsuit is meritless... there are in fact 8 cores both int and fp.

bulldozer lost significant IPC from Magnycours or thuban.  on the server side replacing 12c magny with 16c bulldozer yielded the same performance at the same clock.
Bulldozer was on a newer node and used less power and scaled to higher clocks.  I kept the cinebench crown with 48 Magnycours cores till bricktown (Intel 4p ivy) came out. (60c/120t), 3.8ghz 48c magny beat off 64c 4.2ghz interlagos (bulldozer take 2)... then it was gobstomped by bricktown lol.

That said FP was not half but more like 75% efficient, it was painfully bottlenecked.  you can be mad that it was a shit architecture, but you cannot claim the cores weren't there... they clearly were.
Don't mean to be rude, it is just a greatly misunderstood architecture, it went backwards from magny...and then made 5-10% gains per refresh as intel was making 20% ipc uplifts.


----------



## londiste (Jan 24, 2019)

seronx said:


> The public and industry understands a "core" as these components;
> 1. A Control Bus/Control Logic.
> 2. An Instruction Bus.
> 3. An Address/Data Bus which is usually connected to a Load/Store Unit.
> ...


Public and industry understands core as a unit that can take instructions from a set (in this case x86), execute them and get the compute results out. Front end is definitely part of the core. The gist of it is - you cannot take that integer core out and use it as a functional x86 CPU.

By the way, this lines up with how software treats a core as well as how a core logically should be treated.  Blaming Microsoft here is shortsighted, they clearly went by AMDs suggestions in showing Bulldozers as 8 core, a decision which had to be changed later. Linux changed the OS level scheduling far quicker and with less arguments.


seronx said:


> Split Bulldozer Module;
> 2x 2K L2 BTB
> 2x 256K L1 BTB
> 2x Branch Predictor
> ...


No you can't split a Bulldozer module into two functional cores. In a Bulldozer module there is one Branch Predictor, one Fetcher, one Decode, One L2 cache etc.


----------



## qubit (Jan 24, 2019)

eidairaman1 said:


> They already learned hence Zen


I know, I was just making the point if they ever have thoughts of doing it again in the future.


----------



## Flyordie (Jan 24, 2019)

danbert2000 said:


> *The problem is that AMD made a design that was just hyperthreading with an extra integer unit thrown in. So technically, it is more capable than just having two execution states for one execution engine (containing an FPU and IU), since two threads can technically run at the same time, but if both threads need the FPU, then it is basically back to a multithreaded single core*.
> 
> I think they may have a case in that early processors didn't even have an FPU, and were still processors. So it is technically an eight core integer CPU, and a four core floating point CPU. So you technically have eight cores that could run at once. It will depend on how much a modern processor design matters, as AMD didn't include any caveats in their marketing for the FX series to indicate that it wasn't always going to run 8 threads simultaneously. And in my personal opinion it was not correct to call them 8 core processors. They should have just called them 4 module processors, or made clear it was 8 integer cores and would perform at half speed for FP math. I wouldn't be surprised if AMD loses. I don't consider them 8 core processors since they aren't 8 core all the time.
> 
> Maybe the most damning thing is that AMD now sells 8 core processors that actually do have the FPU and IU per core, and 4 core processors with SMT that are 4 core/8 thread. In a way, that's admitting that the FX core terminology was a load of shit the whole time.




The code we ran was optimized with AMD's help.  We were able to get the FPUs to operate as 2 in parallel. The problem is, most programmers don't wanna do the extra few steps or just use an Intel based compiler which views the FX series as a 4-core CPU and doesn't take advantage of any of its extra resources. The FPU in each Bulldozer module is technically 2x 64bit units but merged into using just 1 scheduler. You had to know how to code for Bulldozer to get the scheduler to run things that could utilize both.


----------



## Vya Domus (Jan 24, 2019)

FordGT90Concept said:


> Pretty sure you can't.



You are making a lot of assumptions here it seems without cheeking first, cores can be turned off. You do understand what independent means I presume, so I ask you again how can you do this without breaking the functionality of the module ?


----------



## londiste (Jan 24, 2019)

Disabling in no way shows that the disabled core was independent. To show that you would need to do this the other way around - disable everything else in the module and see what that core is capable of 

Edit:
By the way did you notice how core disabling works on your screenshot - CPU core 1-2/CPU core 3-4/CPU core 5-6/CPU core 7-8. This strongly suggests that these are indeed not independent cores.


----------



## ArbitraryAffection (Jan 24, 2019)

Wow this has been argued to death but here is my 2 cents.

It's _technically _and 8-core IMO and thus AMD marketing was correct. If you look at die shot within each module you will see duplicated logic blocks for all 8 cores, in 4/8 you will not see this because the two threads share existing hardware. The processor has 8 Integer cores, and they are cores, especially with the Steamroller and Excavator chips as they have their own dedicated instruction decoders too. (BD and PD had to share a decoder IIRC). The Floating point unit is capable of running SMT with two threads and has 4x FPU pipes so it can juggle two threads (and that's where it gets the 2 thread per module). I think I read somewhere AMD stated a lot of work on desktop CPU is integer based so they opted with this design. At the end of the day, it _is _an 8-core chip, but it shares an FPU block between groups of 2 cores.

Stupid case to try and get a bit of money, when AMD really needs each penny it can get. IMO.


----------



## Vya Domus (Jan 24, 2019)

londiste said:


> This strongly suggests that these are indeed not independent cores.



Nope, it suggest some resources are shared between each pair. And that in turn does not negate the independence of each core. Just like how the L3 cache is shared among every CPU core in some processors.


----------



## londiste (Jan 24, 2019)

ArbitraryAffection said:


> If you look at die shot within each module you will see duplicated logic blocks for all 8 cores, in 4/8 you will not see this because the two threads share existing hardware.


Are you sure about that?
Lets say this is an image of a CPU module. Would you consider the parts in rectangles separate cores? 






Vya Domus said:


> Nope, it suggest some resources are shared between each pair. And that in turn does not negate the independence of each core. Just like how the L3 cache is shared among every CPU core in some processors.


Agreed. But would you like to guess (or list) what the shared resources are? Which resources would you consider defines an independent core?


----------



## AusWolf (Jan 24, 2019)

"12 members of the public (not necessarily from an IT background)"

It is stupid to have non-IT people in the jury in a case like this.


----------



## londiste (Jan 24, 2019)

ArbitraryAffection said:


> The processor has 8 Integer cores, and they are cores, especially with the Steamroller and Excavator chips as they have their own dedicated instruction decoders too. (BD and PD had to share a decoder IIRC). ... At the end of the day, it _is _an 8-core chip, but it shares an FPU block between groups of 2 cores.


Starting Steamroller AMD actually did split the Decoder. Architecture details for these are pretty scarce to come by though (Anandtech's article has some details).
At the same time, there is a lot more shared in a module other than just the FPU block. Fetch, Instruction Cache, L2 Cache and probaby some more stuff. In Bulldozer/Piledriver Decoder as well.

Actually, the same question really comes up again - What would you consider defines a core?


----------



## ArbitraryAffection (Jan 24, 2019)

londiste said:


> Are you sure about that?
> Lets say this is an image of a CPU module. Would you consider the parts in rectangles separate cores?
> View attachment 115029
> 
> Agreed. But would you like to guess (or list) what the shared resources are? Which resources would you consider defines an independent core?


No, i'm pretty sure they are the SIMD units. Bulldozer Integer cores do not have SIMD units (obviously), they are in the FPU. This really is semantics at this point. 






I can see what you're saying honestly. I think AMD was a bit misleading with what they called a "core" especially when the marketshare was highest with Intel and they were using a "traditional" monolithic core design. But the point is: there's a lot more hardware duplicated in a BD module for each "core" than a 2-way SMT design such as the one you posted. I think a compromise is in order; It's a "4-module chip with 8 clustered integer cores"  But I'm not sure where this leaves AMD and the case. I guess it will depend on a bunch of non techies looking at die shots and block diagrams lol


----------



## Vya Domus (Jan 24, 2019)

londiste said:


> Yep, would you like to guess what the shared resources are? Which resources would you consider defines an independent core?



The dependencies that exist within each pair are irrelevant , each instruction assigned to each hardware thread is fetched, decoded, executed and stored back. The fact that there is still scaling in terms of throughput way past 4x and single thread performance is never affected clearly shows that there are enough resources such that instructions can be independently executed. Which is not the case for example with SMT capable cores, where despite the fact that there are two hardware threads available the lack of resources causes both pipelines to become interlocked to the point where you can even see a regression in performance. That never happens with Bulldozer.


----------



## Shambles1980 (Jan 24, 2019)

Vya Domus said:


> The dependencies that exist within each pair are irrelevant , each instruction assigned to each hardware thread is fetched, decoded, executed and stored back. The fact that there is still scaling in terms of throughput way past 4x and single thread performance is never affected clearly shows that there are enough resources such that instructions can be independently executed. Which is not the case for example with SMT capable cores, where despite the fact that there are two hardware threads available the lack of resources causes both pipelines to become interlocked to the point where you can even see a regression in performance. That never happens with Bulldozer.



and yet you cannot disable 1 core at a time only 1 module at a time. showing that 1 of the "cores" cannot function without the other"


----------



## Vya Domus (Jan 24, 2019)

Shambles1980 said:


> and yet you cannot disable 1 core at a time only 1 module at a time.



I have even showed the option in the BIOS to shut down cores within the module and not the module itself. At this point I am going to assume that there isn't just a lack of understanding on this forum but also an unwillingness to do so.


----------



## londiste (Jan 24, 2019)

ArbitraryAffection said:


> No, i'm pretty sure they are the SIMD units. Bulldozer Integer cores do not have SIMD units (obviously), they are in the FPU. This really is semantics at this point.


You were talking about duplicated module blocks on a die shot 
That is a Skylake core and you are right, these are SIMD units. Although INT, FP or Vector was a bit secondary here, technically these should be the execution units behind ports 0 and 1.


Vya Domus said:


> The dependencies that exist within each pair are irrelevant , each instruction assigned to each hardware thread is fetched, decoded, executed and stored back.


This is where you are wrong. Dependencies are not irrelevant.
But OK. you said instructions are fetched, decoded, executed and stored back. At least fetch and stored part are very clearly happening at the module level. Decode in Bulldozer and Piledriver as well. After that, Decode is (partially) done in separate units. The stage of processing with separate hardware is only execution.


Vya Domus said:


> The fact that there is still scaling in terms of throughput way past 4x and single thread performance is never affected clearly shows that there are enough resources such that instructions can be independently executed. Which is not the case for example with SMT capable cores, where despite the fact that there are two hardware threads available the lack of resources causes both pipelines to become interlocked to the point where you can even see a regression in performance. That never happens with Bulldozer.


Available resources is very conditional and has no real requirement of execution units being separated in the way they are in Bulldozer. Execution units eventually boil down to several pipes you force instuction and data down to that compute stuff.  To look at what resources are or could be available for compute you need to look inside the execution units. How they are organized has a lot do with scheduling and managing things but little with the actual compute.


Vya Domus said:


> I have even showed the option in the BIOS to shut down cores within the module and not the module itself. At this point I am going to assume that there isn't just a lack of understanding on this forum but also an unwillingness to do so.


You showed an option 'One Core Per Compute Unit'. Right after that are the options to disable... modules, 2 cores at a time. There is no option to shut down one core in a module. This combination makes this setting you showed simply a type of SMT - in Bulldozers case officially CMT.


----------



## Vya Domus (Jan 24, 2019)

londiste said:


> At least fetch and stored part are very clearly happening at the module level.



It simply doesn't matter if it's singular hardware block or not. Look how many entries the decode stage has.







londiste said:


> You showed an option '*One Core Per Compute Unit*'. Right after that are the options to disable... modules, 2 cores at a time. *There is no option to shut down one core in a module*.



You have some serious reading issues.


----------



## eidairaman1 (Jan 24, 2019)

Vya Domus said:


> I have even showed the option in the BIOS to shut down cores within the module and not the module itself. At this point I am going to assume that there isn't just a lack of understanding on this forum but also an unwillingness to do so.



My motherboard allows cores to be turned off as well.


----------



## londiste (Jan 24, 2019)

Vya Domus said:


> You have some serious reading issues.


Really, the BIOS options are irrelevant. The setting you showed shuts down 4 "cores" not one. Depending on BIOS you may be able to shut down one "core" in a module. What you are shutting down is not a core, it is an Integer Execution Unit.


----------



## Vya Domus (Jan 24, 2019)

londiste said:


> What you are shutting down is not a core, it is an Integer Execution Unit.



You're making me laugh, making stuff up now ? How do you know it does that ?


----------



## londiste (Jan 24, 2019)

Vya Domus said:


> You're making me laugh, making stuff up now ? How do you know it does that ?


Because if it shut down the rest of the units the other core would no longer work.
For obvious reasons there is no BIOS setting to do that.


----------



## eidairaman1 (Jan 24, 2019)

londiste said:


> Really, the BIOS options are irrelevant. The setting you showed shuts down 4 "cores" not one. Depending on BIOS you may be able to shut down one "core" in a module. What you are shutting down is not a core, it is an Integer Execution Unit.



Do you have amd white papers of that happening?


----------



## londiste (Jan 24, 2019)

eidairaman1 said:


> Do you have amd white papers?


Look at the Bulldozer block diagram @Vya Domus posted a few posts up. It has been said in this thread repeatedly that AMD did provide fairly nice details about the Bulldozer Architecture. 
That block diagram is a single module. The moment you shut down any parts that are not duplicated it will no longer work. The duplicated parts are the two Integer Clusters.


----------



## Vya Domus (Jan 24, 2019)

londiste said:


> The moment you shut down any parts that are not duplicated it will no longer work.



Ever heard of power gating ?


----------



## londiste (Jan 24, 2019)

Vya Domus said:


> Ever heard of power gating ?


If we are talking functionality, power gated unit is shut down.
If you mean one of the Integer Clusters, then yes, it can be shut down both in terms of not being used and I would expect is power gated.
I don't see the relevance?


----------



## eidairaman1 (Jan 24, 2019)

londiste said:


> Look at the Bulldozer block diagram @Vya Domus posted a few posts up. It has been said in this thread repeatedly that AMD did provide fairly nice details about the Bulldozer Architecture.
> That block diagram is a single module. The moment you shut down any parts that are not duplicated it will no longer work. The duplicated parts are the two Integer Clusters.



So where's an official statement from amd, white papers?

If you have them that states any of this please do share because I believe you are pulling this from thin air.


----------



## londiste (Jan 24, 2019)

eidairaman1 said:


> So where's an official statement from amd, white papers?


What exactly do you want a statement about?
AMD will not be saying it is 4 cores, the wording they have been using everywhere are 'modules' and 'integer cores'


----------



## Vya Domus (Jan 24, 2019)

londiste said:


> What exactly do you want a statement about?



About the stuff you are making up such as the fact that only ALUs can be power gated and nothing else.


----------



## londiste (Jan 24, 2019)

Vya Domus said:


> About the stuff you are making up such as the fact that only ALUs can be power gated and nothing else.


Do you agree that power gated unit does not work? Work meaning perform the function it is supposed to?


----------



## Vya Domus (Jan 24, 2019)

You simply don't know what is power gated and what isn't, give it up.

But from the fact that there is still scaling to be gained even for floating point throughput by enabling both cores within the modules suggests there is more to it than just disabling the ALU. Clearly the fetch/decode/FPU are affected as well when disabling one core per module.


----------



## londiste (Jan 24, 2019)

You are derailing the topic with power gating. Stop putting words in my mouth. I have not said ALUs are the only thing that can be power gated and I indeed expect everything can be power gated, probably on a unit level as well as on more granular level in many cases.

Increased throughput in this case - including the floating point throughput in some cases - has not that much to do with cores. It is related to available compute pipelines as well as managing the work.
Fetch/Decode/FPU are affected positively when one Integer Cluster is disabled. They have to do less work. Especially with OS then not pushing 2 threads worth of work into the module


----------



## Particle (Jan 24, 2019)

Midland Dog said:


> 8 alu from memory, for integer ops its an 8 core for floating point its a 4 core, simples, i personally would have called it an 8 thread cpu, not and 8 core. at the same time its up to the customer to do some research, as a quad core its decent perf but for an 8 core its kind of pathetic



That is an incorrect assessment.  The FPU works as two independent units unless either core needs to execute a 256-bit FP op.  The units were designed to fuse together for (relatively rare) 256 bit operations.

Calling a module a single core because of how the FP unit works would be akin to having two 3" paint brushes and calling them a single 6" brush because you *can* hold them together to paint a thicker line.


----------



## londiste (Jan 24, 2019)

FPU consists of 4x64-bit pipes that can be fused into 2x128-bit or 1x256-bit as needed. 4x64b and 2x128b can be shared to two separate threads just fine.
FPU really is not a reason why module would be a single core. FPU has not always been a part of CPUs and that includes fairly recent stuff for example ARMv6 or v7.


----------



## Vayra86 (Jan 24, 2019)

FordGT90Concept said:


> Performance doesn't really matter.  It's definition of words in the eyes of the public and whether or not AMD used words to describe their product in a way that was misleading to the public.
> 
> The public understand "core" as independent processors.  That's not the case with AMD modules.



Interesting take on it, and yes, plausible too.


----------



## FordGT90Concept (Jan 24, 2019)

Vya Domus said:


> You are making a lot of assumptions here it seems without cheeking first, cores can be turned off. You do understand what independent means I presume, so I ask you again how can you do this without breaking the functionality of the module ?
> 
> On reason why AMD split dispatcher in future iterations of the design is that they could shutdown more transistors when there was only one thread directed at the module.  This is not an issue with independent cores at all.
> 
> View attachment 115028


That does exactly what I said It does: soft powers off one integer core per module by denying a thread to each module.  The settings below are per module which are the equivalent of powering down an independent core.  It affirms what I said about the design: you can't stop just core0, or core6 like independent cores can.  So many components being shared limit its ability to do so.



AusWolf said:


> "12 members of the public (not necessarily from an IT background)"
> 
> It is stupid to have non-IT people in the jury in a case like this.


It's the public that was damaged, not necessarily IT people that have a deeper understanding of what they're buying.

Also, juries are always randomly selected and screened for conflicts of interest.  They're always supposed to be neutral and representative of the district's population.



londiste said:


> Look at the Bulldozer block diagram @Vya Domus posted a few posts up. It has been said in this thread repeatedly that AMD did provide fairly nice details about the Bulldozer Architecture.
> That block diagram is a single module. The moment you shut down any parts that are not duplicated it will no longer work. The duplicated parts are the two Integer Clusters.


The fact that AMD never produced a diagram of a "single core" of Bulldozer is evidence that closest similarity to a "single core" in other designs is, in fact, what AMD calls a module.  Module is the smallest, complete processor (what a core is) Bulldozer has.


----------



## mouacyk (Jan 24, 2019)

Vya Domus said:


> It simply doesn't matter if it's singular hardware block or not. Look how many entries the decode stage has.
> 
> 
> 
> ...



Thanks for posting this diagram.  If I have 2 independent integer instructions to execute, is it possible for cluster 1 and cluster 2 to execute at the exact same clock cycle without delaying any of them?


----------



## FordGT90Concept (Jan 24, 2019)

Yes, assuming the dispatcher doesn't run in to any blocking scenarios (e.g. only a 256-bit FPU instruction to execute).


----------



## Shambles1980 (Jan 24, 2019)

AusWolf said:


> "12 members of the public (not necessarily from an IT background)"
> 
> It is stupid to have non-IT people in the jury in a case like this.



i dont see how that is true.. 
the case is
"normal members of the public were sold "cores" which weren't the same as a traditional core. But amd says that normal members of the public would have known the difference" 

Who better to have than normal members of the public if the argument is the public should know the difference.


----------



## Vya Domus (Jan 24, 2019)

mouacyk said:


> Thanks for posting this diagram.  If I have 2 independent integer instructions to execute, is it possible for cluster 1 and cluster 2 to execute at the exact same clock cycle without delaying any of them?



Each cluster can execute 4 instructions concurrently in total , two arithmetic and two memory operations.



FordGT90Concept said:


> Yes, assuming the dispatcher doesn't run in to any blocking scenarios (e.g. only a 256-bit FPU instruction to execute).



Floating point instructions do not block arithmetic ones as far as I know. The only limitation appears when a single 256 bit operation is issued which blocks any other floating point instruction for the respective clock cycles.


----------



## FordGT90Concept (Jan 24, 2019)

If you have two threads which have a series of 256-bit instructions queued, only one thread will proceed per clock.


----------



## Vya Domus (Jan 24, 2019)

In the case of two threads which consist of a sequence of 256 bit ops each, blocking integer ops isn't even a consideration anyway.


----------



## FordGT90Concept (Jan 24, 2019)

FX-8350 can only execute 4 256-bit FPU operations at a time.  Ryzen 2700X can execute 8 256-bit FPU operations at a time.  The duties of a core aren't exclusively integer in nature.


----------



## Vya Domus (Jan 24, 2019)

And this relevant to the discussion why ?


----------



## FordGT90Concept (Jan 24, 2019)

There are situations where a Bulldozer module behaves like a single core with SMT.


----------



## Patriot (Jan 24, 2019)

FordGT90Concept said:


> FX-8350 can only execute 4 256-bit FPU operations at a time.  Ryzen 2700X can execute 8 256-bit FPU operations at a time.  The duties of a core aren't exclusively integer in nature.



And Phenom II can do 0 256-bit FPU,  AVX support does not a core make or break.  For that matter FPU does not a core make or break.
That said... the FX 8150 and line can do 8x 128-bit FPU operations or can combine and do 4x 256-bit. 
A poorly architected design does not change the core count no matter how much you want to argue over it.
Being able to turn cores off in pairs or as singles does not change the core count... there was a time where there was no power gating, all on or all off, were they no longer cores then?

Plain and simple frivolous lawsuit.   The performance sucked, they overhyped it, the only argument they have IS performance of those 8 cores was not better than 4 quick cores and that is a bogus argument.


----------



## Vya Domus (Jan 24, 2019)

FordGT90Concept said:


> There are situations where a Bulldozer module behaves like a single core with SMT.



Are you seriously going to use AVX as an argument  for all this ?


----------



## Shambles1980 (Jan 24, 2019)

what you, i or amd want to classify as a core. is not relevant, the only thing relevant to the case is what did people think a core was due to convention of the time. and did amd provide people the thing they expected when they said 8 cores.
AMD says people should have understood it wasn't 8 fully independent cores even though they didn't label it as such.
The law suit says amd should have labeled it properly and not doing so was deliberate.

----------------

P.s

I dont think you could possibly arrive where we are today if they did have 8 real cores.
and you may want to bring up infinity fabric and how things are glued together as a Scandal that just isnt anything.. But the thing with that is.. that genuinly isnt an issue and will never end up in a thread like this 4-5 years down the road.


----------



## FordGT90Concept (Jan 24, 2019)

Shambles1980 said:


> The law suit says amd should have labeled it properly and not doing so was deliberate.


Exactly.
core == processor
integer core != core (rather integer core is a component of a core)



> Federal Trade Commission: Under the law, claims in advertisements must be truthful, cannot be deceptive or unfair, and must be evidence-based.


AMD used two phrases in describing what Bulldozer was that were not deceptive: module and integer core.  They elected not to use these phrases instead, went the deceptive, untruthful one: core.  Outside of the context of Bulldozer, references to a "core" as an "integer core" are virtually nonexistent.  Since the debut of the multicore CPU, cores meant individual processors sharing the same socket.

Evidence is found in how Bulldozer was designed differently.  A core in any other CPU is effectively an independent processor.  By the same logic, AMD's module has more similarities with a core than AMD's integer cores do.  Evidence, therefore, strongly suggests untruthfulness here too.


----------



## wiyosaya (Jan 24, 2019)

qubit said:


> Hopefully this lawsuit will discourage AMD from using such a cludgy, low performance compromised design in the future.


IMO, that went out the door with clueless Rory Reed.


----------



## qubit (Jan 24, 2019)

wiyosaya said:


> IMO, that went out the door with clueless Rory Reed.


Let’s hope it stays that way.


----------



## Patriot (Jan 24, 2019)

FordGT90Concept said:


> Exactly.
> core == processor
> integer core != core (rather integer core is a component of a core)
> 
> ...




You are basing core defn on existence of AVX support.  In that case there are 20 years of non cpu cores.
There are 8 int and 8 128bit FPU compute units.  Those are the facts.   How the cpu is composed modularly does not change the fact that there are in fact 8 cores.
Zen is composed of 4 core modules.  That doesn't mean that a 2700x has 2 cores it has 8.


----------



## Shambles1980 (Jan 24, 2019)

its not a matter of what we call a core, or what amd call a core. 
Its a matter of what the general accepted definition of a core was at the time.
AMD even in the evidence provided from other users here admit that the bulldozers did not use a conventional core.

the law suit basically says
People bought bulldozers thinking they were getting 8 conventional cores.
amd Deliberately neglected to state that they were not the cores that you were probably expecting.
People should be compensated.

you are welcome to try and say amd adequatly explained the cores in bulldozers were not the same as those in other multi core processors of the time.
But then you have to remember you are talking to other people who Also knew from the start what they were. 

The people who were "allegedly" ripped off are the people who just saw a box saying "8cores"  and bought it not knowing anything about it other than more cores = more better.

Now i can argue back and forth as to why i don't call them cores, but that does not matter, just as you can argue back and forth why you think they are cores.
the only thing that matters is people expected product A and received product B, and Product B was not adequately advertised to state that it was not the same as product A.


----------



## FordGT90Concept (Jan 24, 2019)

Patriot said:


> The lack of reading comprehension you have shown is exceptional.  You are basing core defn on existence of AVX support.  In that case there are 20 years of non cpu cores.


I'm basing it on this (Excavator versus Zen):




And this (Thuban):




Thuban -> core
Excavator -> core but let's call it a module and slap it next to a...
Zen -> core ...because they're basically one in the same, right?

This slide should be exhibit A for the plaintiff (look at that title even ):




2 integer cores != 2 cores

If you put Excavator cores or Zen cores in the Thuban diagram, you end up with six of them either way and both can handle 12 threads.  The *only* difference is that Excavator has extra ALUs and a decoder to accelerate the second thread.


----------



## Patriot (Jan 24, 2019)

What people expect is irrelevant, only that product matches advertisement, which it does.
AVX support is irrelevant, even current cpu's have unequal avx support even throughout intel's server linup.

Even assuming FPU support is now expected as part of a cpu core.  A bulldozer 8 core cpu can do 8 int or 8 independent fpu calculations at the same time.
AMD said we tried something different, we tried to make a more efficient cpu to give you 8 real cores instead of 4 cores and 4 hyperthreads.
They in fact did what they said.

Lets look at this again since you all clearly missed it.







Look at that sandybridge with Hyperthreading for a grand 4x speadup.  4cores 8 threads for 4x performance.
990x 6 cores 12 threads for 6x performance. (also 1k)
AMD 8 cores 8 threads for a little over 6x improvement.

Is their scaling bad?  IPC worse?   absolutely.
But did they deliver what they promised?   Absolutely.

BTW this is a FPU benchmark.  That is not 4 FPU cores quite clearly it is 8 poorly scaling ones.


Also for those clearly not understanding CPU core architecture history and WHY FPU does not a core make...
Here is Thuban... what's that, only 1 128-bit fpu?  So is it also not a core?


----------



## londiste (Jan 24, 2019)

Again. Public and industry understands core as a unit that can take instructions from a set (in this case x86), execute them and get the compute results out. Front end is definitely part of the core. The gist of it is - you cannot take that integer core out and use it as a functional x86 CPU.


----------



## FordGT90Concept (Jan 24, 2019)

Patriot said:


>


I waved a magic wand and turned that Thuban core into a pseudo Bulldozer core for you:




Two integer cores in one core.  Not rocket science.  Blue box aligns with the Thuban picture I posted.


----------



## Patriot (Jan 24, 2019)

londiste said:


> Again. Public and industry understands core as a unit that can take instructions from a set (in this case x86), execute them and get the compute results out. Front end is definitely part of the core. The gist of it is - you cannot take that integer core out and use it as a functional x86 CPU.



You can't take any singular cores out of any modern cpu.  They are too highly integrated.  Sharing memory controllers and caches.
Being unable to seperate highly integrated chips into individually working components is NOT the definition of a core.

Independent execution is.
If you wanted your core to work by itself you would have to add all those other components that have been optimized out.
Same way if you wanted to break a Bulldozer module apart.



FordGT90Concept said:


> I waved a magic wand and turned that Thuban core into a pseudo Bulldozer core for you:
> Two integer cores in one core.  Not rocket science.  Blue box aligns with the Thuban picture I posted.




LOL 0/10, would get sued and lose.

You missed the 2nd FPU unit.
That only has 1 128bit FPU, bulldozer has 2.


Bulldozer was AMD's first AVX supporting chip and they did something different with it.
It required 2 fpu units sharing resources that could also operate independently.

AMD's claim is 8 real cores and we did something different in the name of saving space to give you 8 cores.
It has 8 independently operating cores...... and it does multi-threaded performance Better than 4c/8t.
It is exactly as advertised.

I have tried to explain CPU architectures but you all clearly desire an argument more than the truth, Peace.


----------



## FordGT90Concept (Jan 24, 2019)

Patriot said:


> You missed the 2nd FPU unit.


Bulldozer only has one FPU but it is capable of SMT.

Seriously, this is irrelevant.  Look at AMD's "Zen" Core slide again.  The literally put it next to "Excavator" and it's devoid of any other uses of the word "core."  It's plain as day to see AMD acknowledges Excavator "modules" were in fact, Excavator "cores" or they wouldn't compare it to Zen as they did.


----------



## londiste (Jan 24, 2019)

Patriot said:


> You can't take any singular cores out of any modern cpu.  They are too highly integrated.  Sharing memory controllers and caches.
> Being unable to seperate highly integrated chips into individually working components is NOT the definition of a core.
> 
> Independent execution is.


Independent execution is effectively the same point.

Memory controllers and caches are not part of the core, no more than FPUs. In consumer space Athlon64 was the CPU moving memory controller into the CPU, it used to be in northbridge. Same with cache, there were (even x86) CPUs without cache and it was outside the CPU at first.


----------



## NdMk2o1o (Jan 24, 2019)

Just started from page 3 about 30 mins ago... an oldie but a goodie and truly fitting for this thread I think


----------



## FordGT90Concept (Jan 24, 2019)

Patriot said:


> It has 8 independently operating cores......


They are not independent.  If the fetcher fails in one module, both integer cores become unreachable.  If the same scenario played out in Zen or Thuban, it would only be down one integer core because that's not a shared component (nothing is shared except memory subsystems which are native to computer design).


----------



## Patriot (Jan 24, 2019)

Yup, confirming, done, yall cant read worth shit.

But please, go actually try and learn what makes a cpu a cpu.  And study the evolution of multiprocessor design and how the cores share resources.... it would be enlightening.


----------



## Vya Domus (Jan 24, 2019)

FordGT90Concept said:


> 2 integer cores != 2 cores



Don't you think something is awfully amiss here that you have to use the word "core" for both ?



FordGT90Concept said:


> If the fetcher fails in one module, both integer cores become unreachable.



That's just a lack of redundancy, doesn't mean anything in particular.



FordGT90Concept said:


> Bulldozer only has one FPU but it is capable of SMT.



*It has two (technically three), per module.* The diagrams have been posted to death by this point, seriously. SMT has nothing to do with any of this.


----------



## Shambles1980 (Jan 25, 2019)

Vya Domus said:


> Don't you think something is awfully amiss here that you have to use the word "core" for both ?



i have to use the word dog for a dog and a dog fish..
must be the same right.


----------



## seronx (Jan 25, 2019)

FordGT90Concept said:


> Bulldozer only has one FPU but it is capable of SMT.


It has a single floating point core.  With the capabilities of;
2x Lo 80-bit
2x Hi 64-bit
For FMACs Pipe0 and Pipe1.  Lo0+Hi0 = P0 and Lo1+Hi1 = P1
2x Mid 128-bit 
For MMXs Pipe2 and Pipe3.

To Steamroller/Excavator;
2x Lo 80-bit
2x Hi 64-bit 
For FMACs Pipe0/Pipe1.
1x Mid 128-bit
For MMX Pipe2.

The units themselves are each a FPU.  While, all of them are part of the whole floating point core.  The FP core however can also be called the Floating Point Unit.

The cores in Bulldozer can also be called Integer clusters.  The module can also be called a core.  However, most of these distinctions are marketing.

Bulldozer via Industrial+Educational standards has
2x AMD64 cores
1x AMD64 floating-point core.

The cores don't execute x86-64, they execute an internal ISA.  The cores are thus separate from the dispatch of those decoded instructions.  The core begins at the instruction bus which is the retire queue and ends at the load/store which is the load/store buffers.

Even if AMD went from 2x LSU to 1x LSU there will still be two cores.


----------



## FordGT90Concept (Jan 25, 2019)

Even if it had "2x AMD64 cores" and "2x AMD64 floating-point cores", so long as the fetcher is shared, the whole is collectively referred to as the core (aka, processor), not the individual components you enumerated.  Hell, drop it down to just "2x AMD64 cores" and forget the "AMD64 floating-point cores" as long as they share that fetcher, the whole is still considered a core.

If you look at how the word "core" is used in the context of processors, it is the lowest common denominator across all architectures.  It describes the discreet hardware that takes an instruction with operands and turns it into a result: cache to cache.  The fetcher is a critical component of that going back to at least the 80386:




Excavator "core" is therefore a singular core with two discreet ALUs handling two concurrent threads.

Jump ahead to Pentium 3 there's a fetcher per core:





If the CPU can't fetch an instruction to decode, it literally remains forever idle.


----------



## seronx (Jan 25, 2019)

FordGT90Concept said:


> as long as they share that fetcher


There is no shared fetching, and even if there was it would still be two cores.

Core 0 can't fetch Core 1's instructions.
Core 1 can't fetch Core 0's instructions.

Core 0 fetches 16B every cycle.
Core 1 fetches 16B every cycle.


----------



## FordGT90Concept (Jan 25, 2019)

The fetcher delegates threads and instructions.  In the case of Excavator with both integer cores enabled, that's two sets of instructions per cycle.  The fetcher decides which integer core gets to process it.  For example, if the power state is lowered, it can request two instructions but place them both on the integer core in a serialized fashion.  That has obvious advantages when running on one integer core because it translates to fewer cycles wasted on the memory subsystem.  It's still a shared, critical component.

If you seriously think the fetcher isn't shared then you're telling me AMD doesn't know their own product (). Refresher:





Let me get my van Gogh on again...

This is what a dual-core module would look like (mimics UltraSPARC T1):




You could eliminate the Fetcher/Decoder/FPU entirely from this schematic and it will still qualify as a dual core module because there's two discreet processors there.  Likewise, you could clone the FPU, remove the fetcher/decoder for it, and place it under the control of each core's fetcher/decoder and you'd end up with a design very similar to Core 2 Duo.  

If there was no FPU under the fetcher, the fetcher wouldn't fetch floating point operations by design.  It has to be shared in order to load balance the shared FPU.  If one thread is hammering FPU instructions, the processor is better off sending another FPU instruction heavy thread to an entirely different module.


----------



## RichF (Jan 25, 2019)

Garbage Class-Action Lawsuit Against AMD Bulldozer Is Headed to Trial
https://www.extremetech.com/computi...uit-against-amds-bulldozer-is-headed-to-trial



			
				Joel Hruska said:
			
		

> What Dickey and Parmer are actually arguing is that Bulldozer/Piledriver (the FX-9590, specifically) _did not deliver the performance they expected from an eight-core CPU_relative to Intel CPUs. They argue that the shared resources in the Bulldozer core prevented the chip from “simultaneously multi-tasking” and that because resources were shared between the CPU cores, that Bulldozer “functionally only have four cores.” Both of these claims are factually wrong.





			
				Joel Hruska said:
			
		

> A Bulldozer CPU core _was_ different than a Thuban CPU core, or an Intel CPU core from an equivalent Core chip. The problem is, they aren’t nearly different enough to justify arguing that AMD had misused the word _core_, and the claims the plaintiffs make do not withstand technical analysis.
> 
> Did Bulldozer share an FPU? Certainly. So did the Sun UltraSPARC T1 (one FPU per chip) and T2 (one FPU per core, but shared by up to eight threads). The lawsuit claims that sharing L2 caches and FPUs means that AMD violated the commonly understood definition of “core,” yet Intel chips have shared L2 caches since the Core 2 Duo days. And therein lies the problem. We could certainly define a CPU core based on the underlying capabilities of the relevant components to act as a _general purpose microprocessor without assistance_ — something Cell’s SPEs cannot do. This type of division would establish a more meaningful differentiation. Attempting to draw a line through a chip in the manner that this lawsuit does, however, is impossible. If Bulldozer’s cores aren’t cores, neither are the cores in other CPUs.


Someone posted that the way AVX-256 is processed by Bulldozer justifies this lawsuit. However, that reasoning calls into question whether any processor that lacks AVX-256 support has even one "actual core", which is clearly absurd.

Beyond how Bulldozer didn't measure up to Intel's design decisions in various ways, it exceeded Intel's performance in certain other ways — such as the number of in flight instructions the processor could handle. Does this mean Intel's processors didn't have true cores in them? After all, they didn't tell consumers that Bulldozer can handle more in flight instructions.

Even earlier processors didn't have FPUs at all. Some supported external FPU chips. Some didn't support even those. Some chips have L4 cache. Old CPUs had no cache at all. Is something that's on the die part of the CPU core, from the point of view of the consumer, like the L4 cache in Broadwell-C? If not, what is the consumer to make of it — that it doesn't exist simply because it's not part of the main chip on the die or part of what CPU architects consider a core? For something that doesn't exist, Broadwell-C's L4 did improve performance tangibly in workloads that are important to consumers — making the obsessing over what's inside cores even more suspect.

There is also the issue of in-order vs. out-of-order design. In-order, which is slower, was dropped back in 1995 with the Pentium Pro. Yet, Intel decided, many years later, to sell Atom to the masses, an in-order design. With the notion that consumers should consider it fraud when a company sells them slow cores — the Atom seems to be a great target for frivolous lawsuits. Not only was it a radical return to in-order design, it was paired with a power-inefficient supporting cast that cast very dramatic doubt on the entire point of Atom's marketing pitch: its performance-per-watt, a performance-per-watt level reached by subjecting consumers to the anemic performance of in-order processing, processing slowness not justified by the savings in power due to the horribly inefficient supporting chipset/GPU. To make matters worse in terms of consumer confusion, Atom was later changed to be out-of-order. There was a ton of pro-Atom netbook hype for quite some time. Then, a large swath of reviewers began writing as if the entire thing was the fault of silly consumers, even though so many of them hyped netbooks while it was trendy to do so.


----------



## FordGT90Concept (Jan 25, 2019)

How about we quote directly from the judge instead of a journalists' opinion?
https://regmedia.co.uk/2019/01/22/amd-core-class-action.pdf


> Plaintiffs argue in their complaint that Defendant's Bulldozer products do not contain eight
> “cores” as claimed and advertised.  Id. ¶ 8.  According to Plaintiffs, *a “core” is a processing unit
> that is able to operate (e.g., perform calculations and execute instructions) independent from other
> cores positioned on a chip.*  Id. ¶ 23–24.  *Plaintiffs allege that the Bulldozer CPUs, advertised as
> ...


Dickey purchased a FX-9590 and Parmer purchased an FX-8350 both advertised as a " native 8-core desktop processor."


> Both Named Plaintiffs allege they relied on Defendant’s advertisements as well as their
> “own understanding of the term ‘core’” in “believ[ing] that the . . . 8-Core Bulldozer processor
> would contain 8 cores, such that each ‘core’ would be independent from all others (i.e., it would
> not share resources with the other cores) and would be capable of performing independent
> ...


AMD tried to throw the case out but the judge said:


> *Defendant’s challenges are not persuasive.*  The central question raised is whether a
> reasonable consumer would have been deceived by the term “core” as used in Defendant’s
> advertising.


How does the court answer that question?


> “Whether an ordinary consumer reasonably believes [plaintiffs’ interpretation of the misleading statements] is amenable to
> common proof: reviewing the advertisements, labels, and then asking the jury how they understand the message.”





> Defendant has, in essence, repurposed its argument that different class members may hold
> different understandings of the term “core” as a challenge to class-wide exposure.  Because
> exposure to the alleged misleading statements is uniform across the class, and for the same reasons
> as discussed in Sections III(A)(ii) and III(B)(i)(a) above, these individualized issues of each class
> ...


The definition of "core" must be held by "a reasonable consumer standard."  The population ("class") cannot be divided up between experts and amateurs because that's not what false advertising is about.

At this point, the class action lawsuit is very confined in scale:


> All individuals who purchased one or more of the following AMD computer chips either (1) while residing in California or (2) after visiting the AMD.com website: FX-8120, FX-8150, FX-8320, FX8350, FX-8370, FX-9370, and FX-9590.


I think that's a mistake seeing how the alleged misrepresentation appears everywhere (retailers, on the retail packaging, on advertising material associated with machines containing the processors, etc.).  They're not reaching for the stairs like they could be.


"Plaintiffs allege that the Bulldozer CPUs, advertised as having eight cores, actually contain eight “sub-processors” which share resources..." this statement is absolutely true and where AMD is in trouble trying to redefine what a "core" is.  No doubt AMD is going to explain to the jury that sharing L2 cache is not out of the ordinary across many architectures so the plaintiffs' case is kind of weak there but sharing FPUs is something extraordinary in the consumer space.

Keep in mind that the Plaintiffs aren't "tech experts."  They'll bring in an expert to argue their case for the jury.


----------



## RichF (Jan 25, 2019)

FordGT90Concept said:


> How about we quote directly from the document instead of a journalists' opinion?


I'm not seeing where that judge's opinion rebuts the points raised by Hruska, such as the point about SMT. Perhaps you can directly rebut his rebuttal?

Hruska's article was published in response to the judge's opinion, so the order of things is to rebut Hruska's rebuttal rather than to go back in time to the point in time where the opinion was released and the rebuttal didn't exist.


----------



## FordGT90Concept (Jan 25, 2019)

RichF said:


> Someone posted that the way AVX-256 is processed by Bulldozer justifies this lawsuit. However, that reasoning calls into question whether any processor that lacks AVX-256 support has even one "actual core", which is clearly absurd.


A module can only process one AVX2 instruction at a time because it requires the full capabilities of the FPU to execute.  If two threads are both queuing a AVX2 instruction, one thread has to halt while the other executes it.  This is irregular for consumer CPU space.  Bulldozer and Piledriver can't do AVX2.



RichF said:


> I'm not seeing where that judge's opinion rebuts the points raised by Hruska, such as the point about SMT. Perhaps you can directly rebut his rebuttal?
> 
> Hruska's article was published in response to the judge's opinion, so the order of things is to rebut Hruska's rebuttal rather than to go back in time to the point in time where the opinion was released and the rebuttal didn't exist.


The judge's only job is to align the claims with the law.  The judge dismissed AMD's argument that AMD did not mislead the public.

Hruska was prattling on about technical jargon which is irrelevant to the case.  There's really only two very basic questions being asked here:
1) Is the definition of a "core" an "independent processor?" [this is going to be a resounding "yes"]
2) Does Bulldozer sharing resources conflict with the definition of an independent processor? [this can go either way depending on the strength of the arguments presented by the lawyers and witnesses]

A jury of 12 will be answering those question, not you nor I, and their decision will define the word in California and likely beyond.


----------



## lexluthermiester (Jan 25, 2019)

Late to the party once again, but here's my 2 cents;
The Bulldozer CPU was a hybrid architecture. It was neither 8 true cores *NOR* 4 true cores. Because of it's design it was somewhere inbetween. The performance bares that out. For cost, the performance was a good value. People whining about whether or not they got 8 actual cores need some cheese. Technically, it *did have* 8 instruction executing cores with an FPU unit for each pair of cores in a module. Because of that logic, which is based in factual functionality of how the CPU works, AMD should win this.


qubit said:


> Hopefully this lawsuit will discourage AMD from using such a cludgy, low performance compromised design in the future.


For it's time it performed very well for it's price point. Your conclusion is flawed.


----------



## londiste (Jan 25, 2019)

RichF said:


> I'm not seeing where that judge's opinion rebuts the points raised by Hruska, such as the point about SMT. Perhaps you can directly rebut his rebuttal?
> Hruska's article was published in response to the judge's opinion, so the order of things is to rebut Hruska's rebuttal rather than to go back in time to the point in time where the opinion was released and the rebuttal didn't exist.


Performance is not the primary concern in the court.

At the same time, look at how bulldozer was improved over time. Separate decoder was added in Steamroller and it was suspected and partially shown that with decoder being removed as a limitation, fetch became one. So, in the Fetch-Decode-Execute, Execute had more resources since the beginning, Decode had to be doubled afterwards and to extract the possible performance Fetch would have to be doubled as well. Now if they went through with that the result would have been two independent cores.

FPU claims are fairly irrelevant. In the same way, so are L2 caches. Bringing these up in the court is kind of stupid.
Memory controllers and caches are not integral or required part of the core, no more than FPUs. In consumer space Athlon64 was the CPU moving memory controller into the CPU, it used to be in northbridge. Same with cache, there were (even x86) CPUs without cache and it was outside the CPU at first.



lexluthermiester said:


> Technically, it *did have* 8 instruction executing cores with an FPU unit for each pair cores in a module.


Those 8 are pipes, not cores.
Zen has six plus pretty much the same FPU, 10 pipes total in both units in execution stage. Skylake has 8 pipes in the execution unit.
With all this, we are talking about execution units.

Bulldozer: https://en.wikipedia.org/wiki/File:AMD_Bulldozer_block_diagram_(CPU_core_bloack).PNG
Zen: https://en.wikichip.org/wiki/amd/microarchitectures/zen#Individual_Core
Skylake: https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Individual_Core

Independently executing means a core (similarly to CPU) should be capable of executing the instruction set, not specific micro-operations. At least when we are talking about x86.


----------



## FordGT90Concept (Jan 25, 2019)

londiste said:


> Bulldozer: https://en.wikipedia.org/wiki/File:AMD_Bulldozer_block_diagram_(CPU_core_bloack).PNG


"Core Interface Unit" betrays AMD here too.  Why didn't they call it "Module Interface Unit?"  Could it be that AMD internally called "modules" "cores?"  Zen slides and slides presented during the debut of Bulldozer certainly suggest that.

Context: https://www.tomshardware.com/reviews/processors-cpu-apu-features-upgrade,3569-15.html

Image (Core Interface Unit is abbreviated as "Core IF"):





There's only four and they're responsible for communication among:
-input via L1I
-output via L1D from each integer unit
-input/output via L2
-other modules

Three major components are shared across all Bulldozer iterations:
1) Fetcher (manages high level instructions)
2) Core Interface Unit (effectively a high level cache and communications controller)
3) Floating Point Unit (it's wider in an attempt to match Thuban FPU performance per thread but AVX2 will effectively shutdown access to the FPU by one thread in Excavator)


AMD officially calls them "integer cores" judging by AMD slides. Pictures above call them integer clusters.  Lawsuit calls them "subprocessors."  One can't deny that AMD has done a poor job of messaging here.


----------



## qubit (Jan 25, 2019)

lexluthermiester said:


> For it's time it performed very well for it's price point. Your conclusion is flawed.


My conclusion isn't flawed, yours is.

It was supposed to go up against Sandy Bridge, but AMD were then forced to reduce the price because performance was so rubbish.
On top of that, it's not really a true 8-core (hence my use of "dodgy" in my statement) and can't therefore be claimed as such, no matter how one spins it, hence this lawsuit. I hope the lawsuit wins and no one ever tries this again.


----------



## EsaT (Jan 25, 2019)

FordGT90Concept said:


> The definition of "core" must be held by "a reasonable consumer standard."  The population ("class") cannot be divided up between experts and amateurs because that's not what false advertising is about.


Bulldozer's design certainly had more than its share of flaws, starting from crappy IPC. (just like in Pentium 4)
But if we are talking about false advertising, where's the lawsuit about Intel's CPU generation advertising?

After all "7th" gen was nothing but carbon copy of 6th gen with just clock speed tweaks and really had no business of being anything else than new xx50  designation CPU models.
Even "9th" gen is more of same old Skylake with only some bug tweaks. Though at least extra cores would give justification for calling it as seventh gen.
Not to forget artificial CPU socket roulette to force people to buy new motherboards:
https://www.techpowerup.com/250109/...0-ghz-overclock-on-a-z170-chipset-motherboard

And then there are those compilers provided by Intel two decades ago claiming compatibility with also AMD...
While they actually disabled multimedia extensions supported by CPU, if program was run on AMD CPU, to give Intel CPUs artificial advantage.




qubit said:


> On top of that, it's not really a true 8-core (hence my use of "dodgy" in my statement) and can't therefore be claimed as such, no matter how one spins it, hence this lawsuit. I hope the lawsuit wins and no one ever tries this again.


OK, so when does Intel get judged for their advertising and sleezy tactics?
Or are we going to be picky about who gets penalized and who is given get out of jail for free card?
Intel practised literally extortion 15 years ago.

Intel isn't any white knight on white horse, not even grey knight...
http://jolt.law.harvard.edu/digest/intel-and-the-x86-architecture-a-legal-perspective


----------



## Aquinus (Jan 25, 2019)

You know, all of these block diagrams are cute and everything, but the fact of the matter is that 99% of consumers don't care about the internal parts of the CPU. You don't market block diagrams, you market simple information. Mind you, this entire argument is predicated on the idea that the FPU is essential to the operation of a CPU... it is not. Without the FPU story, none of these arguments make any sense at all. At this point, most of the arguments being made are pedantic in nature, "oh my god, look at this *one individual block*, it's shared so it can't possibly be a 'real core'*™"*. Just because there are a handful of parts that are shared like how the module interacts with the rest of the CPU doesn't mean it's not a core. If Intel had to go the MCM route, a lot of parts of each chiplet would be shared as well. This is a natural result of pulling things apart and clustering them together and looks far more like a multi-CPU design than a modern SMT implementation. That doesn't make the cores any less less of a "real core".

Performance was bad for a couple reasons but, a very big reason was that the integer cores were gimped compared to previous generations and these block diagrams everyone is showing describes that; less ALUs and AGUs means less uOPs per clock, less uOPs per clock results in lower IPC numbers, and as a result, poor performance per core. You know what it doesn't result in? Worse per-core scaling and I think @cdawall already did an excellent job of illustrating that.


cdawall said:


> The 9700K is an 8 core 8 thread CPU. It scores 214 points for the single threaded CB test, it scores 1513 points for the multithreaded test. That is a 7.07x speed up. In 2012 AMD was able to pull off a 6.7x speed up in that same benchmark and you are going to sit there and tell me it only had 4 cores?


If this doesn't inoculate us from this misconception, considering it's comparing apples to apples, then I don't know what will.

I'm sorry people, but an 8 core CPU doesn't have a requirement for those cores to not be crap. 8 crappy cores are still 8 cores and a core is still a core without the FPU. People are grasping at any straws to find substantial arguments at this point. The reality is that if you try to do that in court, they'll see what you're doing, because it means that your argument doesn't have a very strong foundation because you've changed it so many times to support a particular narrative.


----------



## londiste (Jan 25, 2019)

Aquinus said:


> Mind you, this entire argument is predicated on the idea that the FPU is essential to the operation of a CPU... it is not. Without the FPU story, none of these arguments make any sense at all. At this point, most of the arguments being made are pedantic in nature, "oh my god, look at this *one individual block*, it's shared so it can't possibly be a 'real core'*™"*. Just because there are a handful of parts that are shared like how the module interacts with the rest of the CPU doesn't mean it's not a core.


- The argument is not predicated on the idea of FPU. Or Cache or Memory Controller. Or not even performance really although the stupid court case probably will have claims on that.
- The part that is *NOT* shared is one individual block. Everything else is shared.
- Core is a CPU by definition.


----------



## Aquinus (Jan 25, 2019)

londiste said:


> - Core is a CPU by definition.


Modern cores aren't that independant. It's not like we're still rolling with Pentium Ds... but please, keep gasping at straws until you find one that's long enough.


----------



## londiste (Jan 25, 2019)

Aquinus said:


> Modern cores aren't that independant. It's not like we're still rolling with Pentium Ds... but please, keep gasping at straws until you find one that's long enough.


Could you please elaborate? What do you mean they are not that independent?
Core does not have to be a separate die, core needs to be functionally independent.


----------



## Aquinus (Jan 25, 2019)

londiste said:


> Could you please elaborate? What do you mean they are not that independant?


Modern CPUs have a lot of shared components for handling the control of cores within a CPU. There is nothing inside a CPU that's full independent from the rest of the CPU most of the time. That's just how modern super-scalar CPUs with multiple cores work. It's not like every single part of what would traditionally be considered a CPU is duplicated within a single core, unless you're doing what Intel did with the Pentium D, which is a huge waste of wafer space... it was also one of the earliest attempts to go the multi-core route. The reality though is that the Penium D was much more like multi-CPU system than a multi-core one. An argument I might make would be that a bulldozer module is more like a CPU than it is like a core because it's duplicating a lot of control logic for the cores themselves.


----------



## londiste (Jan 25, 2019)

Aquinus said:


> Modern CPUs have a lot of shared components for handling the control of cores within a CPU. There is nothing inside a CPU that's full independent from the rest of the CPU most of the time. That's just how modern super-scalar CPUs work. It's not like every single part of what would traditionally be considered a CPU is duplicated within a single core, unless you're doing what Intel did with the Pentium D, which is a huge waste of wafer space... it was also one of the earliest attempts to go the multi-core route. The reality though is that the Penium D was much more like multi-CPU system than a multi-core one.


CPU as we popularly know it, the slab of silicone under an IHS, is quite far from the actual definition of CPU. Supporting functionality has been more and more integrated into the die as time and production technology progressed but all that is still supporting functionality. CPU needs instructions and data to be sent in and a place to put the data, neither of which is inherent part of a CPU. Lately other logic has been added - Memory Controllers, Storage Controllers, Bus Controllers etc.

What CPU does is still to process instructions. Fetch-Decode-Execute. A core in a multicore processor is defined same as a CPU.
And every single part of what would traditionally be considered a CPU *IS* duplicated within a single core in a modern CPU/core.


Aquinus said:


> An argument I might make would be that a bulldozer module is more like a CPU than it is like a core because it's duplicating a lot of control logic for the cores themselves.


Core is CPU. Bulldozer module is definitely a CPU, there is absolutely no doubt about that.
The point is that the module really is not two independent CPUs. CPU control logic is Fetch and Decode units. These are shared in a Bulldozer module. There are separate Decode units in Steamroller and Excavator but Fetch remains shared.


----------



## seronx (Jan 25, 2019)

Intel made the same mistake as AMD within a couple patents.

https://patents.google.com/patent/US10140129B2/en
which cites
https://patents.google.com/patent/US20120166777A1/en

Intel's doesn't make sense.  Nor, does AMD's make sense(not related to the above patent, but the previous 2007 one.  However the 2005 one is accurate.)

"Processing core having shared front end unit"
which comes from
"The processor 100 may include a plurality of processor cores 102 and a front end 104 shared by the processor cores 102."

-> Processing cores having shared front end unit
vs
-> Processing core having shared front end unit.

//It should be noted that FIG. 1 is provided as an example, not as a limitation, and even though it is depicted that the processor 100 includes two processor cores, the embodiments disclosed herein are applicable to a processor with any number of cores or a system with multiple processors with single or multiple cores.


londiste said:


> CPU control logic is Fetch and Decode units.


Nope, it is the scheduler.  Of which there are two in a Bulldozer module.

https://computersciencewiki.org/index.php/Control_unit_(CU)
- The control unit obtains data / instructions from memory
- Interprets / decodes the instructions into commands / signals
- Controls transfer of instructions and data in the CPU
- Coordinates the parts of the CPU

All of the above is handled by the cores scheduler.

Scheduler fetches macro-ops which are decoded into micro-ops.

The cores front-end is a co-processor for implementing various performance enhancing features.  It can be swapped out for any other front-end design.  Whether, if it is slower or faster even if it is smaller or bigger.


----------



## londiste (Jan 25, 2019)

seronx said:


> Nope, it is the scheduler.  Of which there are two in a Bulldozer module.


This is incorrect.


			
				https://en.wikipedia.org/wiki/Central_processing_unit#Operation said:
			
		

> The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored instructions that is called a program. The instructions to be executed are kept in some kind of computer memory. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the instruction cycle.



Scheduler is usually a part of Execution Unit.
The problem with counting the schedulers is that scheduler placement is an implementation detail and this has been implemented in multiple ways. Not accounting for the size or exact purpose, Bulldozer module has three schedulers, Zen has 7-8, Skylake has one.

Edit:
I missed this part of your post:


seronx said:


> https://computersciencewiki.org/index.php/Control_unit_(CU)
> - (1) The control unit obtains data / instructions from memory
> - (2) Interprets / decodes the instructions into commands / signals
> - (3) Controls transfer of instructions and data in the CPU
> ...


 It is not handled by the scheduler.
1 - Fetch
2 - Decoder
The article does not elaborate but it seems 3 and 4 go a bit beyond the traditional CPU definition and goes for multi-core and other controllers.
3 - probably a combination of dispatch and schedulers
4 - This is likely at PSP/ME level.

I mean, I get why the entire frontend can be considered a scheduler, this as a broad term is what frontend does. The fact that Operating System has its own scheduler that deals with work distribution to cores-threads does not help. But as a technical term in CPU, Scheduler is a specific function in Execution Unit.


----------



## seronx (Jan 25, 2019)

londiste said:


> Scheduler is usually a part of *Execution Unit.*


*Execution core.



londiste said:


> Not accounting for the size or exact purpose, Bulldozer module has three schedulers, Zen has 7-8, Skylake has one.


Bulldozer has three, Zen has two, Skylake has one.

Zen only has a single scheduler for integer.  Of which the reservation stations of are statically divided between each execution unit.  These create the scheduler queues, which are only a part of the scheduler.


----------



## londiste (Jan 25, 2019)

Execution is called a unit, not a core.
https://en.wikipedia.org/wiki/Execution_unit


----------



## Aquinus (Jan 25, 2019)

londiste said:


> Execution is called a unit, not a core.
> https://en.wikipedia.org/wiki/Execution_unit


Execution units don't include control as describe by the second source on that wikipedia page. Executing units are fed control lines, they don't house the control logic.
https://web.archive.org/web/2013123....umass.edu/~weems/CmpSci535/Discussion10.html


----------



## londiste (Jan 25, 2019)

Slightly varying definitions of Execution Unit. 1995 was a long time ago. The one in the link is a basic execution unit, ALU plus some registers. Control logic was not necessary for something as simple as that. Now where Execution Unit includes number of pipes, control is necessary. This would primarily mean a scheduler.

The link looks like part of a CPU architecture course of some kind, meaning a simplified example.


----------



## Aquinus (Jan 25, 2019)

londiste said:


> Slightly varying definitions of Execution Unit. 1995 was a long time ago. The one in the link is a basic execution unit, ALU plus some registers. Control logic was not necessary for something as simple as that. Now where Execution Unit includes number of pipes, control is necessary. This would primarily mean a scheduler.


Actually, it was. Those lines have to be managed by some sort of control unit, otherwise it will literally do nothing. This is true for CPUs as early as the 8080.


----------



## londiste (Jan 25, 2019)

Aquinus said:


> Actually, it was. Those lines have to be managed by some sort of control unit, otherwise it will literally do nothing. This is true for CPUs as early as the 8080.


Something this simple can easily enough be fed right from dispatch. I meant no control logic in the execution unit.


----------



## Vya Domus (Jan 25, 2019)

londiste said:


> Control logic was not necessary for something as simple as that.



Control logic is always necessary.


----------



## qubit (Jan 25, 2019)

EsaT said:


> OK, so when does Intel get judged for their advertising and sleezy tactics?
> Or are we going to be picky about who gets penalized and who is given get out of jail for free card?
> Intel practised literally extortion 15 years ago.
> 
> ...


That's a very nice strawman argument there. Well done! 

The fact is, that whatever Intel has done does not justify AMD committing offences, too. Especially so when the issues aren't even related.

Therefore your argument is invalid and you're coming off as an AMD apologist.


----------



## neatfeatguy (Jan 25, 2019)

Maybe it's just me, but this whole thread has kind of burned out.






At first it was entertaining, now it's just sad to read through the same things getting said over and over and over again by different people.

Side 1 (for AMD): My dad can beat up your dad!
Side 2 (against AMD):  Na-ah! My dad can beat up your dad because your dad is slower!
Side 1: Your dad is gimped so my dad will beat up your dad!
Side 2: Your dad has glasses so he can't see well enough to defend himself. My dad will beat up your dad!
Side 1: Na-uh!
Side 2: Ya-hu!
Side 1: Na-uh!
Side 2: Ya-hu!
Side 1: Na-uh!
Side 2: Ya-hu!
Side 1: Na-uh!
Side 2: Ya-hu!
....

Maybe


----------



## Shambles1980 (Jan 25, 2019)

I said ages ago it would happen lol. 
It always does.


----------



## cdawall (Jan 25, 2019)

neatfeatguy said:


> Maybe it's just me, but this whole thread has kind of burned out.
> 
> 
> 
> ...



More of 

Side 1 here are facts signed off by people that are considered leaders and experts in the industry. 

Side 2 nope. 

Side 1 additional information further proving what was backed up by subject matter experts

Side 2 see previous lack of argument.


----------



## mouacyk (Jan 25, 2019)

Aquinus said:


> *Modern cores aren't that independent.* It's not like we're still rolling with Pentium Ds... but please, keep gasping at straws until you find one that's long enough.


That's exactly why AMD is getting the slap on the hand -- redefining market leading terminology with digressing performance (scaling).  Wouldn't have been a huge deal if they managed closer to 8x scaling on purely integer loads.  When the performance scaling falls short, we try to attribute the causes to the differences in design -- a major one of which is shared instruction fetching.


----------



## RichF (Jan 25, 2019)

For some reason, the quote from Hruska's article isn't showing up correctly on my iPhone. Part of it is and some of it isn't. The first part says: 

_What Dickey and Parmer are actually arguing is that Bulldozer/Piledriver (the FX-9590 said:_

Then it skips a lot and goes to the paragraph "A Bulldozer CPU core was different..." et cetera and the paragraph after that shows up fine.  The problem occurs both in the AdBlock browser I use and in Safari. So, here is the missing quoted text, for those who couldn't see it due to this bug:

Hruska:

What Dickey and Parmer are actually arguing is that Bulldozer/Piledriver (the FX-9590, specifically) _did not deliver the performance they expected from an eight-core CPU _relative to Intel CPUs. They argue that the shared resources in the Bulldozer core prevented the chip from “simultaneously multi-tasking” and that because resources were shared between the CPU cores, that Bulldozer “functionally only have four cores.” Both of these claims are factually wrong.

Bulldozer did not support SMT, which allows a CPU to execute more than one thread simultaneously. The fact that performance scales upwards in integer and FPU workloads on a BD/PD processor when moving from four threads to eight is proof that the CPU is not limited to a functional four-core arrangement. As these results from OpenBenchmarking.org show, BD performance improves above the four-thread mark, even in FPU workloads. Integer workloads also show improvements in scaling from four threads to eight. While the absolute degree of scaling may be less, Bulldozer is not a functional quad-core CPU as a matter of defined core count. The fact that its overall performance may have been equivalent to an Intel quad-core has nothing to do with whether the CPU factually had the advertised number of cores.


----------



## mouacyk (Jan 25, 2019)

This is what baseline core scaling efficiency looks like with the data from https://openbenchmarking.org/result/1110227-AR-AMDSCAL0184:





Even the 2384 does well, because it's got 4 fully independent cores.


----------



## FordGT90Concept (Jan 25, 2019)

Aquinus said:


> You know, all of these block diagrams are cute and everything, but the fact of the matter is that 99% of consumers don't care about the internal parts of the CPU. You don't market block diagrams, you market simple information. Mind you, this entire argument is predicated on the idea that the FPU is essential to the operation of a CPU... it is not.


NVIDIA GTX 970 4GB* * 0.5 GB runs at a fraction of the performance of the other 3.5 GB.
AMD FX-8350 8-core* * Fetcher, Core Interface Unit, and FPU are shared so performance will be less than advertised when a blocking scenario is encountered.

FPU is essential to all consumer products.  Without the FPU, performance would suffer so much that simple tasks such as web browsing (JPEG images especially rely on FPU for rendering) would be impossible without lengthy delays.  No consumer processor made in the last two decades lacked an integrated FPU.  You either have to go all the way back to when the FPU was a *new* or leave the consumer space to look at what are effectively ASIC processors like UltraSPARC which are designed specifically to handle database processing.  Neither case are relevant to the Dickey and Parmer lawsuit.



seronx said:


> https://patents.google.com/patent/US10140129B2/en


Appears to describe Hyperthreading to me.  The fetcher accepts two threads per core.



mouacyk said:


> This is what baseline core scaling efficiency looks like with the data from https://openbenchmarking.org/result/1110227-AR-AMDSCAL0184:
> 
> View attachment 115088
> 
> Even the 2384 does well, because it's got 4 fully independent cores.


Exactly why Dickey and Parmer filed suit.


----------



## Vya Domus (Jan 25, 2019)

FordGT90Concept said:


> AMD FX-8350 8-core* * Fetcher, Core Interface Unit, and *FPU are shared *so performance will be less than advertised when a blocking scenario is encountered.



* Not actually shared


----------



## FordGT90Concept (Jan 25, 2019)

Vya Domus said:


> * Not actually shared







Thread agnostic means that the execution units aren't assigned to one thread or the other, they can flip based on demand.  That's also why the FPU has a "Frontend" (manages the SMT).


----------



## Vya Domus (Jan 25, 2019)

FordGT90Concept said:


> [facepalm.jpg]
> 
> Thread agnostic means that the execution units aren't assigned to one thread or the other, they can flip based on demand.  That's also why the FPU has a "Frontend" (manages the SMT).



FPU = Floating Point *Unit* , singular , one. One unit. 





Have we really gotten to a point when we just don't care anymore ? Plural/singular matters and if the plaintiffs have any hope of winning this they better keep that in mind, we can't just keep mangling these terms forever until we get where we want. It doesn't work like that.


----------



## FordGT90Concept (Jan 25, 2019)

Thread A can end up on FMAC 1 and/or 2
Thread B can end up on FMAC 1 and/or 2

They are not explicitly assigned; they are thread agnostic. FP scheduler/frontend determines what thread ends up where.


----------



## Vya Domus (Jan 25, 2019)

FordGT90Concept said:


> FP scheduler/frontend determines what thread ends up where.



On which FPU, sure, of which there are more than one.


----------



## lexluthermiester (Jan 25, 2019)

qubit said:


> I hope the lawsuit wins and no one ever tries this again.


So what you're saying is, effectively, that no one should ever try something new or try to do things a different way for fear of being punished?  Very short sighted perspective and is not how we got where we are today.


qubit said:


> My conclusion isn't flawed, yours is.


And you've done it again.  I stand by what I said.


----------



## FordGT90Concept (Jan 25, 2019)

Vya Domus said:


> On which FPU, sure, of which there are more than one.


Still a shared resource, as the diagram explicitly says.


----------



## lexluthermiester (Jan 25, 2019)

Aquinus said:


> a core is still a core without the FPU


Correct. That is exactly how early CPU's were made. It wasn't until the 486DX that the FPU was integrated into the CPU die itself. Before then there were separate chips for floating point calculations, if CPU makers made them at all. Single core CPU's without floating point were still called CPU's back then and were considered fully functional. The terminology still applies and is still valid. All AMD has to do is point out these very simple facts, show that each of the 8 Integer Units can execute instructions as designed and that will be that. This lawsuit will fail as long as AMD's legal team are competent, which there is a very good likelihood of.


----------



## qubit (Jan 25, 2019)

lexluthermiester said:


> So what you're saying is, effectively, that no one should ever try something new or try to do things a different way for fear of being punished?  Very short sighted perspective and is not how we got where we are today.
> 
> And you done it again.  I stand by what I said.


No I'm not saying that. More straw man arguments. You're going to keep arguing, aren't you?


----------



## Vya Domus (Jan 25, 2019)

There are multiple FPUs shared by the two threads. Same thing as to how on a GPU CU/SM multiple threads use multiple FPUs but they don't count as just one FPU.


----------



## lexluthermiester (Jan 25, 2019)

qubit said:


> No I'm not saying that.


That is exactly what your statement implied. The perspective expressed is as technically flawed as it is idealistically flawed and is an example of the entitled, greedy and narrow-minded scope that inspired this lawsuit in the first place. This lawsuit should and very likely will fail on the merits alone.


----------



## londiste (Jan 25, 2019)

Could you please stop about the FPU, please? Pretty please?


----------



## FordGT90Concept (Jan 25, 2019)

Vya Domus said:


> There are multiple FPUs shared by the two threads. Same thing as to how on a GPU CU/SM multiple threads use multiple FPUs but they don't count as just one FPU.


In Zen, Core, Core 2, Core I#, Athlon 64 X2, Athlon X2, etc. Core0 cannot share FPU resources with Core1 because they're completely separate thread contexts.  The thread has to be purged from one core and transferred to the other.  In Bulldozer, Thread A and Thread B in the same module both use the same floating point cluster.


----------



## Vya Domus (Jan 25, 2019)

*Cluster*, exactly , meaning more than one. Saying that there is just one FPU that is shared is simply improper.


----------



## FordGT90Concept (Jan 25, 2019)

Doesn't matter how many FMACs there are, they're shared resources in Bulldozer, Steamroller, and Excavator not dedicated resources like they are in Zen, Thuban, Nehalem, and Conroe.  Independent processors don't share resources above the crossbar (or whatever interconnect is used) other than cache.


----------



## Aquinus (Jan 25, 2019)

I think I'm going to un-sub now, considering we have a lot of "experts" chiming in with some rather interesting opinions on the matter.



Spoiler: Not to mention that this thread is...


----------



## Patriot (Jan 26, 2019)

cdawall said:


> More of
> 
> Side 1 here are facts signed off by people that are considered leaders and experts in the industry.
> 
> ...



Yeah... Seeing lots of this...


----------



## Shambles1980 (Jan 26, 2019)

that diagram started off with "no nothing" Kind of funny to be honest.


----------



## F7GOS (Jan 26, 2019)

Shambles1980 said:


> that diagram started off with "no nothing" Kind of funny to be honest.


Maybe said with a hint of tongue in cheek?


----------



## AusWolf (Jan 26, 2019)

Shambles1980 said:


> i dont see how that is true..
> the case is
> "normal members of the public were sold "cores" which weren't the same as a traditional core. But amd says that normal members of the public would have known the difference"
> 
> Who better to have than normal members of the public if the argument is the public should know the difference.


IMO normal members of the public wouldn't tell the difference between a Celeron and a Core i7. Both of them run Facebook and Youtube just fine.


----------



## Shambles1980 (Jan 26, 2019)

in the context of this law suit that's not the best argument.. 
they are arguing that bulldozer "cores" aren't traditional cores and so you cannot count them as 8 cores, and should have called them something else which would have defined them as different so normal people didn't think they were getting 8 full traditional cores.


----------



## AusWolf (Jan 26, 2019)

Shambles1980 said:


> in the context of this law suit that's not the best argument..
> they are arguing that bulldozer "cores" aren't traditional cores and so you cannot count them as 8 cores, and should have called them something else which would have defined them as different so normal people didn't think they were getting 8 full traditional cores.


We cannot argue about cores with people who have absolutely no idea what a processor core is. What they _think _is irrelevant if they lack the knowledge necessary to even join the argument.

My point is: you need some knowledge before you can form an opinion about something.


----------



## Vya Domus (Jan 26, 2019)

I find this logic hilarious.

This relies on the presumption that "normal" people were idiots and they didn't know that this CPU didn't have 8 cores but somehow if AMD would have called it something else suddenly now they know how to make the distinction between that and "traditional cores", all this while they still don't have a clue what a core actually is.

All this is happens in the context where a "normal" consumer can't even properly define what a CPU is and most refer to it as "the brain of the computer".


----------



## AusWolf (Jan 26, 2019)

Vya Domus said:


> I find this logic hilarious.
> 
> This relies on the presumption that "normal" people were idiots and they didn't know that this CPU didn't have 8 cores but somehow if AMD would have called it something else suddenly now they know how to make the distinction between that and "traditional cores", all this while they still don't have a clue what a core is. All this is happens in the context where a "normal" consumer can't even properly define what a CPU is.


I know quite many people who really have never seen a CPU, and have no idea what is inside one. This doesn't make them idiots. They only have different interests. But I still think that they have no right to join the argument, because they don't even know what the argument is about. Just like I would never argue about the latest fashion trends, for example, because I'm a total alien to the topic.


----------



## Shambles1980 (Jan 26, 2019)

Vya Domus said:


> I find this logic hilarious.
> 
> This relies on the presumption that "normal" people were idiots and they didn't know that this CPU didn't have 8 cores but somehow if AMD would have called it something else suddenly now they know how to make the distinction between that and "traditional cores", all this while they still don't have a clue what a core actually is.
> 
> All this is happens in the context where a "normal" consumer can't even properly define what a CPU is and most refer to it as "the brain of the computer".



does not matter if they know the difference provided amd made the effort..
we had the samething over how hard drive space was advertized.. wd settled in that case..


----------



## FordGT90Concept (Jan 26, 2019)

Shambles1980 said:


> wd settled in that case..


Seagate was class action sued and lost.  That's why all hard drives and optical media now have the 1 GB = 1,000,000,000 bytes descriptor on the packaging.

If AMD still produced Excavator processors, they'll probably have to add 1 core = 1 integer core on the box.


----------



## FordGT90Concept (Jan 27, 2019)

486DX is the equivalent of 20 lifetimes old in terms of technology.  It's not relevant to processors that debuted in 2011.  Complaining that the FPUs were in a coprocessor is like complaining that power windows in vehicles shouldn't be a standard feature today.  FPUs are integral to personal computer design for decades.  Hell, the text you're looking at right now is processed by FPUs through TrueType fonts.  Back when FPUs were separate, fonts were just copied from indexed tables (especially ASCII) because they simply didn't have the resources to render flexible fonts.  Today, TrueType fonts are trivial and backpedaling on the hardware that makes it possible is poor design.

Not that it matters.  Bulldozer, Steamroller, and Excavator modules share more than just their ability to process floating point decimals--they share control logic.  A human losing half of their brain changes who they are.  This is also true of AMD modules.  The complete unit (a core) includes one of some things and two of others.  Nothing wrong with that but what is wrong is AMD advertising it as having two of everything.  The judge agreed the arguments need to be heard before a jury.


----------



## lexluthermiester (Jan 27, 2019)

FordGT90Concept said:


> 486DX is the equivalent of 20 lifetimes old in terms of technology. It's not relevant to processors that debuted in 2011.


Absolutely it is as everything currently in use today owes it's heritage to that generation of CPU's, just like all modern ARM based RISC CPU's owe their existence to the early Acorn CPU's. Just because CPU design's have improved and evolved does not make the older iterations irrelevant.


FordGT90Concept said:


> FPUs are integral to personal computer design for decades.


However, are not required. An Integer Unit can do floating point the long way, which is the way floating point was done before FPU's were designed. A CPU is still a CPU with or without an FPU. Likewise a CPU core is still an individual core whether it has it's own FPU or shares one with another core.


FordGT90Concept said:


> Not that it matters. Bulldozer, Steamroller, and Excavator modules share more than just their ability to process floating point decimals--they share control logic.


By that logic, the Core2Quads and any other CPU that has two or more dies bridged together, and shares resources, do not qualify as a single CPU. They are dual CPU packages. So should we all sue Intel and AMD for that deception?


FordGT90Concept said:


> but what is wrong is AMD advertising it as having two of everything.


AMD never said that. They called it an 8 core CPU, which by technical definition, it is.


----------



## Degenerate (Jan 27, 2019)

danbert2000 said:


> I think they may have a case in that early processors didn't even have an FPU, and were still processors.



This. The FPU argument has no weight, because it's not an essential part of a processor.

Intel 8086
Intel 80286
Intel 80386
Intel i486SX
Motorola 68000
Motorola 68020
Motorola 68030

And many more were all "zero-core processors" if you follow this nonsense logic.


----------



## Vya Domus (Jan 27, 2019)

FordGT90Concept said:


> 486DX is the equivalent of 20 lifetimes old in terms of technology. It's not relevant to processors that debuted in 2011.



But the FPUs which have been around since before that chip _are relevant_ ? Ain't gonna float (no pun intended), you either ignore all of these decades of computing because it's all in the past  or you don't. You can't pluck things out selectively.


----------



## FordGT90Concept (Jan 27, 2019)

lexluthermiester said:


> Absolutely it is as everything currently in use today owes it's heritage to that generation of CPU's, just like all modern ARM based RISC CPU's owe their existence to the early Acorn CPU's. Just because CPU design's have improved and evolved does not make the older iterations irrelevant.
> 
> However, are not required. An Integer Unit can do floating point the long way, which is the way floating point was done before FPU's were designed. A CPU is still a CPU with or without an FPU. Likewise a CPU core is still an individual core whether it has it's own FPU or shares one with another core.


486DX didn't do branch prediction like modern processors do.  It is also missing a lot of instructions and completely devoid of multithreading capability.  Additionally, 8087 was sold separately because of design limitations of technology at the time (power, heat, transistor density, etc.).  They were merged into a unified architecture as soon as it was technically viable to do so.  In other words, all of these references to processors that debuted in the 1980s are pathetic excuses to this debate.

Also, 486DX is the first processor that supported both x86 and x87 instructions.  It's processors before that which had x87 coprocessors.



lexluthermiester said:


> By that logic, the Core2Quads and any other CPU that has two or more dies bridged together, and shares resources, do not qualify as a single CPU. They are dual CPU packages. So should we all sue Intel and AMD for that deception?


Core 2 Duo only shared L2 cache between cores:





Core 2 Quad had two of those packages on the same PCB.  All four are independent, complete processors.  The only cache that is necessary to the operation of a processor is L1.

Also, by AMD's definition, Core 2 Duo module would be a quad core because there's 4 ALUs. 



lexluthermiester said:


> AMD never said that. They called it an 8 core CPU, which by technical definition, it is.


Look at any other processor on the market and there's a equal number of fetchers to cores.  Bulldozer is an exception, not the rule.


Oh look, and Athlon 64 X2 slide from AMD!




See what they did there?  Called the whole independent processor package an "execution core."  AMD didn't draw a little box in the box saying this little integer bit here is the "core." 

There's an enormous amount of hypocrisy by AMD on display here. In fact, there's really no references to the arithmetic units of a processor being called a "core" outside of Bulldozer's design.

Even Intel calls the whole independent processor a core.  Here's a slide from Haswell:





As you can see, the industry has a very clear understanding of what a core is.  AMD twisted that understanding to give the appearance of an edge against competing products.  That's "false advertising."  How is it okay for AMD to redefining the word in a way that is misleading to consumers?


For the record, one can make a CPU that has no addressable ALUs, only FPUs.  There's really nothing an FPU can't do that an ALU can do.  It is just slower and requires more transistors.



Degenerate said:


> Intel i486SX


Funny story there: disabling the FPU in the i486SX was similar as disabling a core in, for example, Zen.  The FPU by far used the most die space on the 486 so instead of pitching chips that had a defect in the FPU, they disconnected it and sold it as an i486SX.  The x87 instruction set and IEEE 754 standard was still in its infancy at the time so not much software used it.


The newest architecture that comes to my mind is IA-64. It was created from scratch long after IEEE 754.  Is ALU and FPUs intrinsic to its cores? Why yes, of course:





Mmm, MIPS is kind of an oddball mostly designed for network routing.  Does it have an FPU? R16000 does:





Doesn't matter what architecture you look at, cores are clearly defined and they are not just the arithmetic calculators like AMD claims*.
* Only when on the subject of Bulldozer, Steamroller, and Excavator.

I'm not saying a processor needs an FPU because that's completely dependent on the scenario in which it will be used. I'm saying that AMD had one definition of the word "core," changed it for Bulldozer through Excavator, and then went back to their original definition for Zen.  That bit in the middle deserves a slap on the wrist.


----------



## Shambles1980 (Jan 27, 2019)

the issue is still what perception of a core was at the time..
And we started really with a pentium d. 64 x2, core 2, i5 and so on,
AMD significantly changed the formula but did not represent the differences in the advertising.

people like us who have an interest in this sort of stuff Made our own minds up about the processors. I decided they were not 8 cores. Some others agreed with amd.
But the issue is there genuinely is a difference. Even in all the "evidence" provided by the "they are 8 cores"people in this thread, amd admit they are not 8 traditional cores.
For the most part amd do not even refer to them as cores.
By AMD's own definition of a core from only  the pentium D era they are not cores.
But amd advertised it as 8 cores to the masses who would have thought (it must be the same as a core 2, or a phenom, or other relevant multi core processor of the time, When it simply wasnt and still isnt.
Theres a reason why Phenoms and core 2 quads out performed or performed as well as a buldozer at the time, And theres a reason why i5's out perform them still to this day..

Im not going to say that its Only down to the layout of the die, because that simply isnt true.  There were coner cutting and cost saving methods taken during manufacturing. Which did lead to potential performance losses which could ammount to low double digit  performance drops compared to having designed some parts manually rather than via software.

But regardless of that the issue that the law suit is regarding remains.

people expected cores to mean the same thing as they did with phenoms and other similar cpus of the time. Sure most of them didn't know what that meant.  and probably 80% of them dont even know how  it is different.
But they are different and amd did not adequately advertise it as such..

You can say what you want..
But when people lose a law suit because they advertize 1billion bytes as a GB instead of 1.07billion, then "slight" differences do matter.

it also does not help that amd have changed back to traditional cores virtually admitting that the buldozer modules were infact worse than traditional cores.


----------



## Patriot (Jan 27, 2019)

Hate to call people out.... but ford man... you really need to stop trying to compare block diagrams of vastly different granularity and assuming they are comparable.
You are making many assumptions about how things work internally that... just aren't so.
You are also cherry picking the fuck out of the facts hoping everyone else wont notice.

Claim you can't compare old FPU but keep pulling modern AVX2 FPU to first gen AVX fpu and repeatedly ignoring just 1 gen back.
Please just stop.

FPU is the same per int as in Thuban, but by organizing a pair of int into modules along with a dual fpu with shared fetcher it enables a flexibility that Thuban did not have and enables AVX across 2 FPU units.  As per the scaling performance given (better than sandybridge) it is clear there are 8 fpu units.
Configuration is indeed different to enable AVX gen 1 support.

At the time, the shared resources was the only way to enable 8 cores on 32nm...
The FPU of zen is vastly superior because there is die room to enable it... just like moving to 7nm enables another doubling of cores...

You keep trying to look at 1 detail and declaring AMD was out to get people when it was a solid solution at the time.
1 module, 2 cores.  4mod/8 cores.  It had a unique structure, there was no smt involved, and it outperformed the intel solution on multithreading... but due to the deeeep pipeline the ipc was decreased and required higher clocks to be competitive.


----------



## FordGT90Concept (Jan 27, 2019)

Patriot said:


> At the time, the shared resources was the only way to enable 8 cores on 32nm...


You do realize that 8087 was made a coprocessor because that was the only way they could accelerate floating point operations on the 3 μm process, right?  Even then, yields were terrible which is why most computers didn't have them.  For reference, 8087 had 45,000 transistors compared to 8086's 29,000.


Processor|Architecture|Structure|Transistors (billions)
Ryzen 1800X|Zen|8c/16t|4.8
FX-9590|Vishera|4m/8t|1.2
Phenom II X6 1100T BE|Thuban|6c/6t|0.9...an 8 core Thuban would have ended up having about the same number of transistors.  There's a lot of thread management overhead in doing what AMD did with Excavator that simply did not exist in Thuban.



Patriot said:


> there was no smt involved


Floating points were calculated using SMT.



Patriot said:


> it outperformed the intel solution on multithreading


Only when you compare 1 AMD "module" with two threads compared to 1 Intel "core" with two threads.  If you compare 1 Intel "core" to 1 AMD "integer core," Intel's solution is higher performing.



Patriot said:


> ... but due to the deeeep pipeline the ipc was decreased and required higher clocks to be competitive.


AMD side graded to make their product more attractive to server and mainframe operators.  It was designed to be cost effective in those use cases, not consumer use cases.


----------



## Shambles1980 (Jan 27, 2019)

Patriot said:


> At the time, the shared resources was the only way to enable 8 cores on 32nm...
> The FPU of zen is vastly superior because there is die room to enable it... just like moving to 7nm enables another doubling of cores...



You would think theyd still be using it if its that good.


----------



## lexluthermiester (Jan 28, 2019)

FordGT90Concept said:


> AMD twisted that understanding to give the appearance of an edge against competing products.


Incorrect. AMD didn't "twist" anything. They tried a new way of building a device that could execute code in an attempt to compete. 

All the rest of your very fancy display amounts to flash/bang nitpicking. You did succeed in doing one thing though; you displayed for all to see that you understand that an execution unit does count as a full and complete core in and of it's own. It's good you're not an attorney as you would have effectively tanked your own case with that display and argument.


----------



## FordGT90Concept (Jan 28, 2019)

As previously discussed, an Execution Core does Fetch-Decode-Execute (everything required to turn inputs into outputs).  Fetch is shared in Excavator. Fetch and Decode are shared in Bulldozer.  The execution core is incomplete in Bulldozer unless you consider the execution core an entire module which is what the plaintiff is arguing in favor of.

ArbitraryAffection gave excellent proof of this earlier:





There's only one fetch, one L1 instruction cache, and one decoder.  Omit those components from either integer core and you have transistors that just look pretty in a picture.  You cannot cleave a bulldozer module in two and have two functional processors.  You can do so with virtually every other multi-core architecture out there.

What you see in that picture is a core by textbook definition.  It just happens to be able to process two threads simultaneously when circumstances are favorable to doing so.


----------



## Vya Domus (Jan 28, 2019)

FordGT90Concept said:


> What you see in that picture is a core by textbook definition.



Elaborate please, point us to a couple of books or papers in which CPU cores are described as such.


----------



## FordGT90Concept (Jan 28, 2019)

The whole die shot pictured is a self-contained processor which fits the definition of a singular core.  Have a source:

https://searchdatacenter.techtarget.com/definition/multi-core-processor
A core is synonymous with "CPU."  Initial dual core processors were two CPUs sharing the same socket on the same bus, not unlike a dual socket, single CPU machine.

1800X can rightfully be called an 8 CPU machine on a single socket.  FX-8350 can only be called a 4 CPU machine on a single socket.  Because that gets awfully confusing, AMD, Intel, ARM, MIPS, etc. have taken to calling them "cores" instead so they can distinguish multi-socketed solutions from multi-CPUs on one socket solutions.


----------



## lexluthermiester (Jan 28, 2019)

Vya Domus said:


> Elaborate please, point us to a couple of books or papers in which CPU cores are described as such.


Couldn't have said that better myself...



FordGT90Concept said:


> The whole die shot pictured is a self-contained processor which fits the definition of a singular core.


Your opinion, not supported by historical fact or any citations.


----------



## Vya Domus (Jan 28, 2019)

FordGT90Concept said:


> The whole die shot pictured is a self-contained processor which fits the definition of a singular core.



Book or paper, we had enough of looking at die shots and reading 2 paragraph explanations on the internet. You are vehemently claiming this is a _textbook example of core. _I am assuming you have stumbled across this very exact description and by that I mean cores that have multiple decode entries, multiple load/store, multiple ALUs/FPUs, etc as is the case with a Bulldozer module. Surely you can pull one example out for us from all the material you read. In everything that I have read however I see this :





*"Central Processing Unit main components"*

No mentioning of independent fetch/decode stages, no load/store units, no FPUs, nothing that you argue constitutes a "independent processor" aka core. All I see is either generic "instruction decoder" or "timing and control".

You seem to be extremely fixated on the idea that CPU cores have to be independent processor. Let's see, independent meaning it can operate on it's own and fulfill all the functionalities that it could previously do while inside it's multi-core arrangement, right ?


The only thing that I can think of that fits that description is something like this : https://www.pcper.com/reviews/Processors/Intel-Atom-330-Dual-core-Processor-Review.

In this case you can totally pluck one core/processor out of the assembly and you can use it completely on it's own. It's undoubtedly self contained and self sufficient.

Not even AMD's upcoming chiplets designs would count as being made out of independent processors because they rely on external logic, _which they share,_ to operate . Why wont you understand that independent processors *do not exist anymore in the context of modern CPUs*, they share caches, memory controllers , interconnects which, in particular are absolutely critical to their functionality. Intel even has a word for it : _Uncore _and it usually occupies a considerable portion of the die. It's also the reason why whenever Intel/AMD wants a new chip with less cores they to have redesign the whole damn thing instead of just "cleaving it in two".


----------



## FordGT90Concept (Jan 28, 2019)

lexluthermiester said:


> Your opinion, not supported by historical fact or any citations.


Have this one:
http://accel.cs.vt.edu/files/lecture2.pdf

Breaks multicore processors into homogeneous (copy-pasta) and heterogenous (CELL is named but think SoC in general where there's many components put together to make a flexible whole).

Page 11: Dies, Observations


> Core replication obvious.


Page 14: Multicore-present:


> Operating systems schedule processes out to the various cores in the same way they always have on traditional multiprocessor systems.


The fetcher is what the operating system sees.  This is why Windows 8/10 report FX-8350 as a "4 core," "8 logical processors" on 1 socket.


Have another (sourced from Intel no less):
http://www.ecs.umass.edu/ece/andras/courses/ECE668/Mylectures/Introduction_to_Multi_Core.pdf
Page 17, diagram and explanation of what it means to transition from one core to two.  Area is 2x.  Heterogenous cores by definition are copy-pasta and include all parts required to process instructions.

Page 18, Intel highlights the two heterogenous cores on Conroe.

Page 24, processor resources:
-Caches
-General Purpose Registers
-Segment Registers & TLB
-*FP registers, XMM registers*
-System Flags
-Control and Data registers, Debug registers, MSRs
-Many more

Page 25, explains differences between CMP, SMP, Hyper Threading, and Software Threading.  Particularly relevant:
"Chip Multi Processing, refers to *multiple physical core engines that have unique resources*."
Bulldozer's FP registers and XMM registers are not unique resources to the integer cores, they're unique resources to the module.  Bulldozer doesn't fit under SMP because that requires sharing all resources.

Page 26, "*Core Architecture* (Prescott)" diagram includes everything from instruction TLB to L2 cache.  This mirrors AMD's slide showing an Excavator "core" next to a Zen "core."

Page 27, "*Core Architecture* (Xeon - Dual Core)" diagram which tells the same story as Prescott.  The diagram only includes a single core but on the left most side of it, they have a label depicting "Second core" which means mirror what you see here on the other side of the L2 cache.  More confirmation that a "core" is wholistic (fetch-decode-execute), not just what AMD calls an "integer core."

Page 28, "Multi-core platform (Freescale: embedded)" diagram which depicts two clear "e500-mc cores" with "accelerators" and "connectivity" attached to it via "CoreNet fabric."

Page 29, "Multi-core platform (RMI-XLR: embedded)" diagram depicting 8 clear cores on a "Memory Distributed Interconnect."

Page 30, "Tilera - 64 core CPU" diagram depicting 64 interconnected processors.

Page 34, "Tiled Design & Mesh Network" depicts Intel's 80-core Polaris showing each "core" as a "compute element" + "router"

Page 39, "Multi-core: Design Challenges" says "replicating cores improves productivity."



Vya Domus said:


> Book or paper, we had enough of looking at die shots and reading 2 paragraph explanations on the internet. You are vehemently claiming this is a _textbook example of core. _I am assuming you have stumbled across this very exact description and by that I mean cores that have multiple decode entries, multiple load/store, multiple ALUs/FPUs, etc as is the case with a Bulldozer module. Surely you can pull one example out for us from all the material you read. In everything that I have read however I see this :
> 
> View attachment 115241


First, I'll fix the diagram so it's relevant to Bulldozer:




Then I'll point that #1 proves my point:


> 1. The next instruction to be executed, whose address is obtained from the PC, is fetched from the memory and stored in the IR.


I assume IR stands for "Instruction Register."  On all Bulldozer processors, this is part of the Fetch block which is shared for both threads.  As far as #1 is concerned, you're only looking at *one CPU*.
#2 continues to drive that point home when considering Bulldozer (not Steamroller/Excavator):


> 2. The instruction is decoded.


The Decode block is shared in Bulldozer so as far as this is concerned, there's only one CPU.
#3 is another task of Fetch block so rewind to what I said above.  Two or three steps here dictate we're only dealing with one CPU.  See how my tweaked diagram makes a whole lot of sense now?
Finally, step #4 and #5, we get to the *sole* components where the cycle deviates *but only if* the instruction doesn't include a floating point instruction otherwise it is back to shared which means #4 and #5 are part of the singular CPU.

TL;DR: At least 3 steps say Bulldozer is a single CPU and without those steps, those integer clusters know not what to do.  Pretty clear case a module is a core.



Vya Domus said:


> All I see is either generic "instruction decoder" or "timing and control".


Bulldozer shares "instruction decoder" (literally, I didn't modify the diagram at all) and "timing and control" via "Core Interface Unit" (Core IF in diagram):




This diagram has been posted at least twice now.  I believe it was sourced from Tom's Hardware which is cited in the lawsuit.


And before you retort that Bulldozer can do two threads simultaneously, remember that it hits blocking scenarios more often than dual-core (or more) processors do as mouacyk pointed out:


mouacyk said:


> This is what baseline core scaling efficiency looks like with the data from https://openbenchmarking.org/result/1110227-AR-AMDSCAL0184:
> 
> View attachment 115088
> 
> Even the 2384 does well, because it's got 4 fully independent cores.


Bulldozer underperforms independent cores/processors in c-ray, compress-7zip, npb BT.A, npb FT.B, nbp LU.A, nbp UA.A, and clomp when comparing Opteron 2384 to FX-8150. For example, in 7-zip, FX-8150 only did 48% better where Opteron 2384 did 102% better.  7zip, as far as I can tell, is very ALU and cache intensive.


----------



## londiste (Jan 28, 2019)

lexluthermiester said:


> Incorrect. AMD didn't "twist" anything. They tried a new way of building a device that could execute code in an attempt to compete.


What exactly was new in the way in how Bulldozer was built?


Vya Domus said:


> In everything that I have read however I see this :
> 
> View attachment 115241
> 
> ...


Thank you for the textbook page: Just underneath the figure, in instruction cycle:
1. Fetch
2. Decode
Both of which are shared in Bulldozer.
These are part of the control unit on Figure 5.1.


Vya Domus said:


> You seem to be extremely fixated on the idea that CPU cores have to be independent processor. Let's see, independent meaning it can operate on it's own and fulfill all the functionalities that it could previously do while inside it's multi-core arrangement, right ?
> 
> 
> The only thing that I can think of that fits that description is something like this : https://www.pcper.com/reviews/Processors/Intel-Atom-330-Dual-core-Processor-Review.
> ...


I am not sure why but you seem to have a skewed understanding of independent here. There is absolutely no need for a core to be a a separate chip. Independent core/CPU means it is able to perform its function - execute instructions - independently. No more, no less. Instructions are fetched from somewhere else and results are stored somewhere else - generally either the data bus or cache depending on how the wider system is built.


----------



## FordGT90Concept (Jan 28, 2019)

Thread TL;DR: the Bulldozer module is a different way to multi-thread but it does not represent a multi-core.





...roughly, anyway.  Take those numbers times the number of cores and you'll get an approximation of multithreading scaling.


----------



## Vya Domus (Jan 28, 2019)

FordGT90Concept said:


> First, I'll fix the diagram



Well, don't. You just can't help yourself but change every bit of information just so it can fit with your narrative.

I'll have to accept that you will never be able to use correct information to prove your points and you'll always skew facts.


----------



## lexluthermiester (Jan 28, 2019)

FordGT90Concept said:


> Have this one:
> http://accel.cs.vt.edu/files/lecture2.pdf
> 
> Breaks multicore processors into homogeneous (copy-pasta) and heterogenous (CELL is named but think SoC in general where there's many components put together to make a flexible whole).
> ...


Isn't interesting how you skipped over the comparisons involving the Itaniums and Terascale information? The Terascale CPU shows very clearly that the integer execution units(80 of them) exist without anything other than an IO connection to a separate die with other additional functionality features that operate in addition to the main die. So are those 80 cores not qualified as individual cores? Or is that all just one CPU? Using you argument, that is a single CPU, with 80 sub-cores. But that's not what Intel calls it. So should they sued? That citation does not help your argument as it demonstrates and illustrates that there many varying ways to build a functional CPU, including multiple functionally independent cores. We could also explore the other citation as it also demonstrates a variety of methodologies to build a CPU.
Those citations do not help your position. They actually work against it.


Vya Domus said:


> Well, don't. You just can't help yourself but change every bit of information just so it can fit with your narrative.


Exactly correct.


Vya Domus said:


> I'll have to accept that you will never be able to use correct information to prove your points and you'll always skew facts.


And that is clearly being demonstrated.

Ford, you have lost this debate on merit and by providing citations against your position. Let it go. AMD is going to win this case.


----------



## FordGT90Concept (Jan 28, 2019)

Vya Domus said:


> Well, don't. You just can't help yourself but change every bit of information just so it can fit with your narrative.
> 
> I'll have to accept that you will never be able to use correct information to prove your points and you'll always skew facts.


How is the image I presented not representative of Bulldozer?  I know the registers aren't right but that's because it's deliberately vague in that regard.  The rest is spot on.


----------



## lexluthermiester (Jan 28, 2019)

FordGT90Concept said:


> How is the image I presented not representative of Bulldozer?


The original image was a concept of a basic CPU. Your alteration does not change the context. Just stop.


----------



## FordGT90Concept (Jan 28, 2019)

lexluthermiester said:


> Isn't interesting how you skipped over the comparisons involving the Itaniums and Terascale information. The Terascale CPU shows very clearly that the integer execution units(80 of them) exist without anything other than an IO connection to a separate die with other additional functionality features that operate in addition to the main die. So are those 80 core not individual core? Or is that all just one CPU? Using you argument, that is a single, with 80 different sub-cores. But that's not what Intel calls it. So should they sued? That citation does not help your argument as it demonstrate and illustrates that there many varying ways to build a functional CPU, including multiple functionally independent cores. We could also explorer the other citation as it also demonstrates a variety of methodologies to build a CPU.
> Those citations do not help your position. They actually work against it.


The RIB in each tile/core is effectively the fetcher.  Tera-Scale has more in common with a GPU than a CPU; nevertheless, it still has discreet cores that function the same fetch-decode-execute routine (just software scheduled instead of hardware scheduled)...







More info: https://www.anandtech.com/show/2170/3

I get the strong impression that Tera-Scale is entirely incapable of ALU work: everything exposed is floating point.  That said, it was a prototype meant to reach 1 TFLOP of dynamic compute power and that's exactly what it did.


----------



## Vya Domus (Jan 28, 2019)

That was not for you to photoshop whatever you thought a bulldozer module would look like. It was to prove that the elements which you claim are mandatory for a CPU core to to be independent are never even stipulated as discreet distinguishable components in the overwhelmingly majority of descriptions out there of what a CPU contains.

Amazingly even the slides that you provided contradict some of your claims about shared resources :





"*Functional units*" aka execution units, which may contain there own separate logic as is the case with the FP scheduler in the Bulldozer module. And that was one of your main points on why Bullzoder wasn't an 8 core CPU. Try as you may, it seems you can never get away from these facts.


----------



## FordGT90Concept (Jan 28, 2019)

You cited the only example where "functional units" is used in that whole document.  It's not expanded on anywhere what it meant.

Edit: Looking at the whole page, pretty sure he was referring to Hyper-threading so two threads sharing the same ALUs and FPUs.  Hyper-threading impacts caches, tlb, and btb.  The line directly below it also strongly suggests Hyper-threading (tradeoff being transistors spent on improving utilization in one core versus adding another core). Fits like a glove but again, just an educated guess.



lexluthermiester said:


> The original image was a concept of a basic CPU. Your alteration does not change the context. Just stop.


Bulldozer is anything but "basic."


----------



## Vya Domus (Jan 28, 2019)

Sure thing man, anyway just keep on selectively picking up information out of everything that you are presented with and ignore the rest. Argumentation on the internet 101.


----------



## londiste (Jan 28, 2019)

lexluthermiester said:


> The Terascale CPU shows very clearly that the integer execution units(80 of them) exist without anything other than an IO connection to a separate die with other additional functionality features that operate in addition to the main die. So are those 80 cores not qualify as individual cores? Or is that all just one CPU? Using you argument, that is a single CPU, with 80 different sub-cores. But that's not what Intel calls it. So should they sued? That citation does not help your argument as it demonstrates and illustrates that there many varying ways to build a functional CPU, including multiple functionally independent cores. We could also explore the other citation as it also demonstrates a variety of methodologies to build a CPU.


Context is important. 
- You are right, Tera-Scale can be looked at both ways - calling these 80 units cores can be argued as well as whether Tera-Scale is even a general purpose CPU. Intel Tera-Scale is a specialized application processor, both the intended application as well as architecture is much closer to GPU than a CPU. It is also a much simpler VLIW architecture with very simple instruction set and execution units (couple FPUs). This has more than a few similarities to AMD's similarly named VLIW GPU architecture TeraScale - HD2000-HD4000 series 
- A simple CPU may only need instruction and data passed into it and control logic can be minimal or nonexistent, especially the decode part.
- Bulldozer on the other hand is an x86 CPU. This is effectively a RISC processor masquerading as CISC. Fetch and Decode have a large part to play in its operation.


----------



## FordGT90Concept (Jan 28, 2019)

Tera-Scale is kind of an oxymoron.  In one way, it is extremely flexible (lots of fully programmable cores) but in another, it's terribly inflexible (software programmers have tell the processor how to do almost everything).  I think it can be used as a general purpose CPU but it needs to be coupled with a tailor-made operating system that's unlike any operating system on the market today.    It's kind of in-between a lot of ideas: part GPU (tiles remind me of CELL SPEs), part CPU (can branch far deeper than GPUs), part ASIC (whatever the architecture can do, it will do well).

Intel mostly designed Tera-Scale to test the idea of high-speed interconnects.  It will never find its way into a commercial product most likely because they can't convince anyone to create and maintain the operating system for it.

For the record: Tera-Scale "tiles" are definitely cores just as Bulldozer "modules" are definitely cores.  Fetch -> decode -> execute.  Both do that, and so does every other core.  If you try to call Tera-Scale's FPMACs "cores" like you call Bulldozer's integer cluster "cores," you end up with the same incomplete understanding of what a core must do.  FPMACs and integer clusters are glorified calculators--not processors. They can tell you 1+1=2 but they can't tell you 2 is an index into an array of values and whether the referenced value is odd or even and if odd, is it prime?  That takes a processor, not a calculator.


----------



## mouacyk (Jan 28, 2019)

There's really no reason to bring in 486SX's or GPU cores ... that's not what Bulldozer was competing with. From Wikichip: "Compared to Bulldozer's immediate competitor, Sandy Bridge ..."

If only AMD had called them what they truly were, there would have been zero basis for this case: Conjoined Cores

To answer my question (which I've asked twice without clear answers) of whether a Bulldozer module can start work on two different instructions in the same clock cycle, the answer is never:


> We assume that the fetch units are designed so that, in the absence of sharing (no thread as-signed to the alternate core), one core can fetch every cycle. Thus,  each core has the ability to generate a nextPC cache index every cycle, and to consume a fetch line every cycle. In sharing mode, however, only one request is filled. Thus, in sharing mode with fetch combining, both cores can present a PC to the ICache, but only the PC associated with the core with access rights that cycle is serviced.


----------



## FordGT90Concept (Jan 28, 2019)

Source for the above quote (likely the inspiration for Bulldozer): https://www.microarch.org/micro37/papers/18_Kumar-Conjoined-Core.pdf


----------



## Vya Domus (Jan 28, 2019)

That paper is actually quite fascinating and telling of how this is about to go down , he still refers to this arrangement as being made up of "pairs of processors" and never once he implies this is anything else but a type of multiprocessor.



> _This paper proposes conjoined-core chip multiprocessing – topologically feasible resource sharing *between adjacent cores of a chip multiprocessor* to reduce die area with minimal impact on performance and hence improving the overall computational efficiency_





> _Resources could potentially be *shared among more than two processors*, but this creates more topological problems. Because *we primarily investigate sharing between pairs of processors*, we call our approach conjoined-core chip* multiprocessors*._





> _We assume that a miss can be detected and *communicated to the other core* in 3 cycles _



It's going to be an absolute nightmare for the plaintiffs if they decide to go down the path of disproving AMD's claims about core count. There seems to be absolutely no description found in academia that would contradict their claims that a Bullzoder chip has 8 cores/CPUs/processors.


----------



## FordGT90Concept (Jan 28, 2019)

Bare in mind that the paper was published in 2004.  FX-60 debuted January 9, 2006.  Kumar et. al. had no way of knowing how a dual processor chip would be marketed at the time.  That discussion is also outside of the scope of their paper.

If you take Kumar's paper in whole, it warns that performance of "conjoined core" is inferior to independent cores.  That's what the lawsuit alleges, AMD knew it when they decided to go with it, and they tried to pass it off as a better product than it is by omitting key details in marketing.  I'd argue that if AMD even put "8 conjoined core" on the box, this lawsuit wouldn't have happened but they didn't.

What mouacyk quoted may actually explain why 7zip has poor performance on Bulldozer.  Most of the instructions 7zip requires are simple array operations.  If they're hitting the fetcher faster than the fetcher can cycle between threads when each thread only requires one, maybe two cycles to complete, that's how you can end up with such a massive performance hit.  7zip benefits hugely from hyperthreading because the dual thread fetcher is queuing up two threads for the same compute resources which would otherwise be underutilized.  It stands to reason that in tests where Bulldozer does poorly, Hyperthreading will do exceptionally well.

I provided a plethora of examples of what consumers understand as a core from Intel, MIPS, AMD, and IBM.  Either Bulldozer is wrong or the rest of the industry is wrong.  My money is on Bulldozer.


----------



## Vya Domus (Jan 28, 2019)

It's irrelevant what the industry thinks, including AMD. They don't have an authority to dictate what is what and how it should be marketed, everyone does it's own thing. There is no reference. At the end of the day AMD and Intel produce x86 licensed CPUs with varying underlying architectures that have changed more times that I can count. Fundamentally their products and the concepts they rely on aren't constant through time or particularly consistent.

If the arguments will boil down to "Here, look what everyone else does" or "This product had worse performance than competing product X", well, let's just say they are going to have an exceptionally weak case.


----------



## lexluthermiester (Jan 29, 2019)

Vya Domus said:


> If the arguments will boil down to "Here, look what everyone else does" or "This product had worse performance than competing product X", well, let's just say they are going to have an *exceptionally weak case*.


So far this is what many in this thread have been doing.


----------



## FordGT90Concept (Jan 29, 2019)

Vya Domus said:


> They don't have an authority to dictate what is what and how it should be marketed, everyone does it's own thing.


The court does.  There is a dispute and the court will settle it...

I was shocked Seagate lost the lawsuit in regards to the definition of GB.  Seagate was already right in labeling their products going back decades.  When Seagate said there was 80 billion bytes (80 GB), there were 80 billion bytes usually with some surplus.  The court ruled that 80 GB actually means 80 GiB (insert Jackie Chan WTF here) so Seagate defrauded customers of the difference (5,899,345,920 bytes).  The technical argument was completely on Seagates side.  It was Microsoft that mislead people by using GiB math with GB labels, not Seagate which used GB math and GB labels.  The court didn't care and summary judgement was given to the plaintiff because Microsoft wasn't the one on trial, Seagate paid up.

The technical argument is entirely in the plaintiffs favor in this case.  Benchmarks, conceptual papers, instruction papers, schematics, diagrams, and competing products all evidence that; however, just because the technical details are in favor of one side doesn't mean the court will see it that way.  It certainly didn't in Seagate's case.  How this plays out is going to depend on whose lawyers are more convincing.


I'm still miffed that Microsoft still doesn't show appropriate units to match the math they are using.  I'm also miffed Seagate had to pony up for something they were blameless in (all they can be accused of is not being proactive in labelling). It is what it is.


----------



## hat (Jan 29, 2019)

Personally, I've always considered it quad core "plus extra stuff"... the other 4 aren't quite complete cores, they're missing something which, in their time, were important for a some operations, but not all. That's why their multithreaded performance was hit or miss. But I'm neither an engineer, nor a court... that was my take on it after reading everything I've read on it years ago when the chips were still relevant. That doesn't necessarily mean it's not 8 core though. Sometimes it is, sometimes it isn't, depending on the operation. I don't think you can say a core isn't a core just because it lacks the ability to perform some operations, or does so poorly compared to other cores. Since processors have existed, they've been tacking on additional instruction sets and hardware under the hood. I learned recently when Spectre and Meltdown was still in the news all the time that modern processors perform "speculative execution", something processors didn't always do (it began with the Pentium Pro or something). That doesn't make processors before speculative execution became a thing not processors, it just made them shitty, outdated, obsolete processors.


----------



## lexluthermiester (Jan 29, 2019)

FordGT90Concept said:


> The court does. There is a dispute and the court will settle it...


The court only has the authority to settle the dispute. It does not have the authority to dictate innovation and/or it's description.


----------



## FordGT90Concept (Jan 29, 2019)

lexluthermiester said:


> It does not have the authority to dictate...it's description.


Yes, it does, lest offenders get sued again using the previous case as ammunition against all future cases.  This is the way of "common law."  It is the reason why virtually all products that use 1 GB = 1 billion bytes math have that clearly printed on their label.

Depending on how the lawsuit goes here, we might see future processors contain a brief description of what a "core" is as defined by the court.  Clarity is good in a market, even if meanings were twisted from intent.

1 GB in legalese is 1,073,741,824 bytes.  What's on the package now? Language clearly defining 1 GB as 1 billion bytes to correct the legalese definition.  The court is under no obligation to enforce an international standard.


Most likely the court is going to rule in favor of the poor, defrauded public like how the Seagate case went.  That means AMD loses and "core" means "independent processor."  Anything that doesn't meet that test needs clarification on the packaging which isn't a bad thing.


----------



## hat (Jan 29, 2019)

lexluthermiester said:


> The court only has the authority to settle the dispute. It does not have the authority to dictate innovation and/or it's description.


Seems like they do, in Seagate's case. Now hard drive makers have to treat GB as GiB because some shmuck at Microsoft decided GB were GiB, leading to a user who bought a 250GB hard drive to read as ~232GB in Windows (even though it would also say 250,000,000,000 or whatever bytes).


----------



## lexluthermiester (Jan 29, 2019)

FordGT90Concept said:


> Yes, it does, lest offenders get sued again using the previous case as ammunition against all future cases. This is the way of "common law."


You really need to review what the term "Common Law" actually means.


FordGT90Concept said:


> It is the reason why virtually all products that use 1 GB = 1 billion bytes math have that clearly printed on their label.





hat said:


> Seems like they do, in Seagate's case. Now hard drive makers have to treat GB as GiB because some shmuck at Microsoft decided GB were GiB, leading to a user who bought a 250GB hard drive to read as ~232GB in Windows (even though it would also say 250,000,000,000 or whatever bytes).


That is a definition of measurement, something a court can rule on. This case against AMD is a matter of creative functionality of a CPU, something that has varied wildly since CPU's were created. The court does not have the authority to rule on the boundaries of creative thinking.


----------



## FordGT90Concept (Jan 29, 2019)

lexluthermiester said:


> You really need to review what the term "Common Law" actually means.


Exactly what I said: 


> Common-law courts base their decisions on prior judicial pronouncements rather than on legislative enactments. Where a statute governs the dispute, judicial interpretation of that statute determines how the law applies. Common-law judges rely on their predecessors' decisions of actual controversies, rather than on abstract codes or texts, to guide them in applying the law. Common-law judges find the grounds for their decisions in law reports, which contain decisions of past controversies. *Under the doctrine of Stare Decisis, common-law judges are obliged to adhere to previously decided cases, or precedents, where the facts are substantially the same.* A court's decision is binding authority for similar cases decided by the same court or by lower courts within the same jurisdiction. The decision is not binding on courts of higher rank within that jurisdiction or in other jurisdictions, but it may be considered as persuasive authority.


AMD said FX-8350 is an "8-core" and the plaintiff disputes that based on articles, diagrams, and performance.  "Creativity" has nothing to do with it because class-action lawsuits, by definition, require proof of damage.  The only thing litigable in terms of creativity is patents, trademarks, and copyrights which is not at play here.


Seriously, I hope ya'll are learning something from this.  I know I learned quite a bit about Intel Tera-Scale.


----------



## Vya Domus (Jan 29, 2019)

FordGT90Concept said:


> AMD said FX-8350 is an "8-core" and the plaintiff disputes that based on articles, diagrams, and performance.



Which don't actually exist, as I pointed even in the article describing exactly the type of processor that AMD used the core count is still consistent with their claim.

And how do you prove the performance wasn't what people thought it would be ? Weren't there reviews available ? Did AMD go out of their way to hide anything about their product ? Unless there are going to be clear cut answers to that, this really will be a matter of creative thinking.

Not that I actually necessarily believe AMD will win. They are 100% in the right but US courts have proven to be a wild west numerous times.


----------



## hat (Jan 29, 2019)

lexluthermiester said:


> That is a definition of measurement, something a court can rule on.



Sure, but...



lexluthermiester said:


> This case against AMD is a matter of creative functionality of a CPU, something that has varied wildly since CPU's were created. The court does not have the authority to rule on the boundaries of creative thinking.



Though I do agree that CPUs have changed considerably since CPUs have been a thing, this is a case about whether or not AMD has mislead customers with their "8 core" labeling on Bulldozer and related CPUs. It's more about false advertising than it is about "ruling on the boundaries of creative thinking" - i.e. what makes a core a core... but in order to decide whether or not AMD is to blame for false advertising, in this case, you would have to define what exactly makes a core, so you can decide whether or not AMD were selling 4 core CPUs or 8 core CPUs.


----------



## FordGT90Concept (Jan 29, 2019)

Vya Domus said:


> And how do you prove the performance wasn't what people thought it would be ? Weren't there reviews available ? Did AMD go out of their way to hide anything about their product ? Unless there are going to be clear cut answers to that, this really will be a matter of creative thinking.


The statement of both plaintiffs is that they purchased the product based on the description of "8-cores" and did not consult reviews until after the fact.  "8-core" is hiding the fact that it's very different architecturally from Thuban before it and Intel's competing product, Sandy Bridge.

...this thread has entered the looping phase.


----------



## Vya Domus (Jan 29, 2019)

A different architecture, by definition, will result in a different CPU ...

This is why we've entered a loop, no can put their finger on what exactly is wrong.


----------



## FordGT90Concept (Jan 29, 2019)

...that can't use the same words to accurately describe its design.



Vya Domus said:


> This is why we've entered a loop, no can put their finger on what exactly is wrong.


Maybe you can't, but I (and others) did, repeatedly. Have a recap:
1. Shared fetcher.
2. Depending on iteration, shared decoder.
3. Depending on iteration, shared dispatcher.
4. Shared floating point units.
5. Shared Core Interface Unit.
...we also got into why these are a problem:
1. The fetcher is incapable of saturating the ALUs in a lot of cases where it has to service both integer clusters.  Thuban was able to in the same scenarios.
2. + 3. AMD choose to split the decoder and dispatcher for reasons revolving around power efficiency and performance.
4. AMD was really fixated on the idea that GPUs would take over FPU so, per thread, Bulldozer really offers no improvement over Thuban.  Because collisions can happen, in practice it can be slower.
5. All communication with the rest of the system flows through this unit.  Windows 10 sees the Core Interface Unit and believes it is looking at a core.  It looks at the fetcher offering to take two threads and interprets that as two logical processors.

Overall, a Bulldozer module is a lot of transistors short of a dual-core.  That was their intent, after all.


----------



## Vya Domus (Jan 29, 2019)

Let's just say that if a court will make certain architectural choices mandatory or not allowed this will be the most bizarre thing I have witnessed this decade.

This is also the first I have heard of CPUs being "wrong".


----------



## londiste (Jan 29, 2019)

Vya Domus said:


> Let's just say that if a court will make certain architectural choices mandatory or not allowed this will be the most bizarre thing I have witnessed this decade.


Court will not make certain architectural choices mandatory. It will decide if marketing these as different architectural choices is allowed.


----------



## witkazy (Jan 29, 2019)




----------



## lexluthermiester (Jan 29, 2019)

londiste said:


> It will decide if marketing these as different architectural choices is allowed.


That is what I was trying to elaborate, a court does not have the authority to make such a determination.


Vya Domus said:


> This is why we've entered a loop, no can put their finger on what exactly is wrong.


I can; Entitled, whiny snowflakes(backed by greedy lawyers) bemoaning that they feel slighted for getting 8 Integer cores without a matching number of Floating Point Units. They want to force everyone else to match their views instead of just voting with their wallets and disagreeing in a civilized way.


----------



## hat (Jan 29, 2019)

lexluthermiester said:


> I can; Entitled, whiny snowflakes(backed by greedy lawyers) bemoaning that they feel slighted for getting 8 Integer cores without a matching number of Floating Point Units. They want to force everyone else to match their views instead of just voting with their wallets and disagreeing in a civilized way.



I kind of agree with this... but I kind of don't. For guys like us who frequent a tech forum, have a "basic" (to us) understanding of what we're looking at when we read a review for a product we might be interested in, it's not too hard for us to grasp the basic concept of what was going on with Bulldozer and make an informed choice. Personally, I look at the 8 "core" Bulldozer kinda funny, but I don't lose any sleep over it... in other words, it's not a big deal. We've seen the price, performance, power draw etc figures for Bulldozer and competing chips, so when we go to buy whatever, we know what we're buying.

Then you have the group of people that think an Intel i7 chip has 7 cores, the i5 has 5 cores and so on. They might know a little more about computers than your grandma, but they don't really know all that much... and when they find out that the 8 "core" Bulldozer isn't quite 8 full, complete cores, likely after buying one, they might be a little bit mad, because they thought their 8 core FX-8350 was gonna blow their buddie's much more expensive 6 core 3930k out of the water... but then, they probably didn't research their product all that well, or read very many reviews, or maybe not even understand computer hardware quite so well in general, so that's where I agree with the whiny entitled snowflakes bit. My eyes begin to glaze over a little bit when I read one of johnnyguru's PSU reviews (or, more relevant, looking at these block diagrams and reading everyone's argument on what makes a CPU a CPU), but at least I understand enough of it (maybe not the in depth technical details) to know whether or not I'm buying a turd.


----------



## londiste (Jan 29, 2019)

lexluthermiester said:


> londiste said:
> 
> 
> > It will decide if marketing these as different architectural choices is allowed.
> ...


What do you mean? If they advertise the choice they made as one they did not, court pretty clearly has authority to say something about it.

The fact that whiny snowflakes(backed by greedy lawyers) are doing the bemoaning does not make an argument automatically invalid.


----------



## lexluthermiester (Jan 29, 2019)

hat said:


> Then you have the group of people that think an Intel i7 chip has 7 cores, the i5 has 5 cores and so on. They might know a little more about computers than your grandma, but they don't really know all that much...


And we all know people like that.


hat said:


> but then, they probably didn't research their product all that well, or read very many reviews, or maybe not even understand computer hardware quite so well in general


And this is only their own responsibility. Not AMD's fault. Regardless of the number of cores, performance is always the more telling point. Reviews will always tell a potential buyer what they're getting into. There is no excuse for buying something like the CPU's in question and whining later about performance or whether or not the claimed 8 cores are actually 8 cores.


londiste said:


> What do you mean? If they advertise the choice they made as one they did not, court pretty clearly has authority to say something about it.


Only whether or not there is a claim about false advertising, which the plaintiffs will have to make a case for and they have a serious uphill battle.


----------



## FordGT90Concept (Jan 29, 2019)

How many "cores" do you see in this picture?





How many in this picture?




Remember, Feng's slides saying "core replication obvious."  The defense has the uphill battle here, not the plaintiff.  The pictures above make the plaintiff's case as plain as day.  Honestly, AMD is better off settling out of court.


----------



## seronx (Jan 29, 2019)

Orochi die = Orochi being an eight headed/eight tailed snake.





Right A/B and left G/H = L1i/BP/Fetch/Decode
Below A/B and G/H = Cache unit and L2
Left A/B and right G/H = Floating point unit
Inside A/B/G/H = Scheduler/Integer Units/Load-store/registers/etc <== Actual core

Eight actual cores.


----------



## FordGT90Concept (Jan 29, 2019)

Funny, you had to provide your own picture with boxes pre-drawn on it.  Thanks for affirming my point that they aren't obvious. 

Let's throw something not x86 into the mix.  Here's an Exynos Octa (big-LITTLE design):




Like Sandy Bridge-EP, the cores are obvious.


----------



## seronx (Jan 29, 2019)

FordGT90Concept said:


> Funny, you had to provide your own picture with boxes pre-drawn on it.


I would say it is better than what is shown in "Design of the Two-Core x86-64 AMD “Bulldozer” Module in 32 nm SOI CMOS" - 25 October 2011






The design from Core(Chip) Multiprocessing(CMP) to Cluster-based(Chip) Multi-threading(CMT) needs to be displayed.
A CMP module will always have a single core.
A CMT module within the same space as a CMP module will always have 1+x cores.


----------



## FordGT90Concept (Jan 29, 2019)

That document was written entirely by AMD employees:
https://ieeexplore.ieee.org/document/5746227/authors#authors

None of the citations appear relevant to the court case.

TL;DR: the jury would have to take AMD's word for it.


----------



## lexluthermiester (Jan 29, 2019)

FordGT90Concept said:


> TL;DR: the jury would have to take AMD's word for it.


Just like they'd have to take any other CPU maker's word for it. Your point was pointless.


----------



## Midland Dog (Jan 31, 2019)

Particle said:


> That is an incorrect assessment.  The FPU works as two independent units unless either core needs to execute a 256-bit FP op.  The units were designed to fuse together for (relatively rare) 256 bit operations.
> 
> Calling a module a single core because of how the FP unit works would be akin to having two 3" paint brushes and calling them a single 6" brush because you *can* hold them together to paint a thicker line.


this just leads back to the original arguament, the definition of a core, the best i have heard was that a core is able to do independant logic and calculations without being tied to any other sillicon, dont know how accurate it is but we need to find an actual definition. Would i not be able to call a 4 core chip with hyperthreading an "8" core because it is able to execute instructions on 8 threads?


----------



## FordGT90Concept (Jan 31, 2019)

I wouldn't be against IEEE establishing standards not unlike SAE and horsepower/torque measurement. Consumers have the right to know that the cores they are buying are independent, conjoined, or multi-threaded.  Intel did a good job with the latter via their Hyper-Threading trademark; conversely, AMD does a poor job at informing consumers about Zen's multi-threaded capabilities.  Conjoined is always going to have inferior performance (but lower cost) compared to independent which is something consumers should know about.


----------



## londiste (Jan 31, 2019)

FordGT90Concept said:


> Intel did a good job with the latter via their Hyper-Threading trademark; conversely, AMD does a poor job at informing consumers about Zen's multi-threaded capabilities.


AMD is doing perfectly good job with Zen's multi-threaded capabilities. SMT is an industry standard term and fits the situation perfectly. Intel's HyperThreading is SMT with a trademarked name slapped on it.


Midland Dog said:


> this just leads back to the original arguament, the definition of a core, the best i have heard was that a core is able to do independant logic and calculations without being tied to any other sillicon


For the definition to be effective - not any logic and calculations but specifically execute instructions of the given instruction set.


----------



## lexluthermiester (Jan 31, 2019)

Midland Dog said:


> the best i have heard was that a core is able to do independent logic and calculations without being tied to any other silicon


And that about sums it up. Actual specific components don't matter.


----------



## Shambles1980 (Jan 31, 2019)

lexluthermiester said:


> And that about sums it up. Actual specific components don't matter.


well it does or you can argue 4c8t cpus are 8cores


----------



## lexluthermiester (Jan 31, 2019)

Shambles1980 said:


> well it does or you can argue 4c8t cpus are 8cores


No you can't.


----------



## FordGT90Concept (Jan 31, 2019)

The only difference is one wide integer cluster versus two narrow ones.  The frontside and the backside is otherwise the same.


----------



## lexluthermiester (Feb 1, 2019)

FordGT90Concept said:


> The only difference is one wide integer cluster versus two narrow ones.  The frontside and the backside is otherwise the same.


Exactly. The difference is that with SMP, a single core is toggling between tasks/threads so quickly that to us it seems to be handling them at the same time, when in actuality it isn't.


----------



## FordGT90Concept (Feb 1, 2019)

Guess what the fetcher, core interface unit, and floating point cluster does in Bulldozer.

Look at it this way:


Architecture|Trans|Organization|Source
 Vishera|1.2|4m/8t|
AnandTech

Sandy Bridge|1.16|4c/8t|
AnandTech

Ivy Bridgee|1.4|4c/8t|
AnandTech

Sandy Bridge-EP|2.27|8c/16t|
OverclockOne of these things is not like the other...

You can see performance numbers on the AnandTech link.  Hint: i7-3770K 3.5 GHz almost always wins against FX-8350 4.0 GHz and often by a long mile.  Why is that?  Because Intel beats the hell out of their dual-threaded cores where AMD divided and conquered in their dual-threaded cores.  When Intel is faced with only a single thread, it pulls out all of the stops to get it done.  AMD can't.  Even when you async like a boss, AMD's shared nature comes back to haunt it often doing 10-50% worse than it should.  Can't win single, can't win dual, can't win in terms of transistor count either (whole reason why AMD pursued it).  Zen and Bulldozer proves "conjoined cores" were a bad idea.  Isolating hardware resources from threads that could use it makes little sense.


----------



## mouacyk (Feb 1, 2019)

FordGT90Concept said:


> Zen and Bulldozer proves "conjoined cores" were a bad idea.  Isolating hardware resources from threads that could use it makes little sense.



It served the purpose of a budget design, reducing transistor requirements, reducing die size, increasing yields, and presenting cheaper alternatives.   I would reserve the term innovation for designs that actually improve performance, while minimizing cost, unlike how many fans are describing Bulldozer.


----------



## FordGT90Concept (Feb 1, 2019)

Look at the transistor counts though: there's virtually no savings.  Die size is a combination of transistor count and process: no savings.  Yields are mostly the result of die size: no savings. Cheaper? Only if you want an inefficient processor that's really good at integer math on many threads.  Judging by the benchmarks, that's not the bottleneck for most software.


----------



## mouacyk (Feb 1, 2019)

Based on the white paper, AMD was supposed to accomplish the listed things.   Did they know during design that they wouldn't be able to realize those reductions but went for it anyways, to avoid completely busting?


----------



## FordGT90Concept (Feb 1, 2019)

It costs billions to design and prototype a new architecture.  Once they got so many billions in, they were committed to bringing it to the market to get some revenue off it.


----------



## Zyll Goliat (Feb 13, 2019)




----------



## londiste (Feb 13, 2019)

Zyll Goliath said:


>


He is taking the same route of blaming single FPU. And ignoring everything else on the same picture in the module that is part of a CPU core and shared


----------



## FordGT90Concept (Feb 13, 2019)

londiste said:


> He is taking the same route of blaming single FPU. And ignoring everything else on the same picture in the module that is part of a CPU core and shared


Because that's the layman's way of looking at it (stands out in diagrams).  As I pointed about before, the transistor count is a dead giveaway that Bulldozer isn't remotely close to being an 8-core CPU.  It's a 4-core, 8-thread CPU with dedicated resources for each thread (which is actually really stupid from a performance point of view because this enforces underutilization of hardware resources).

Cores are independent processors.  They don't share anything--they communicate via memory subsystems.  Each processor pulls the data it needs, executes it, and pushes it back.  At no point does one core interfere with another (unless there's some kind of intentional memory lock to prohibit thread cross references).  7zip compression proves Bulldozer "cores" are not independent.


----------



## lexluthermiester (Feb 13, 2019)

FordGT90Concept said:


> 7zip compression proves Bulldozer "cores" are not independent.


Out of curiosity, how is that conclusion reached?


----------



## mouacyk (Feb 13, 2019)

lexluthermiester said:


> Out of curiosity, how is that conclusion reached?


Might be referring to this test done at Anandtech, where conclusion is flawed.  If you normalize the 7zip scores to the same clock speed, they are identical.  The relevance to this thread is that the FX-8150 is claiming 8 cores but the 2600K is only claiming 4 cores:


----------



## lexluthermiester (Feb 13, 2019)

mouacyk said:


> Might be referring to this test done at Anandtech, where conclusion is flawed.  If you normalize the 7zip scores to the same clock speed, they are identical.  The relevance to this thread is that the FX-8150 is claiming 8 cores but the 2600K is only claiming 4 cores:


Just because a quad core CPU came close does not settle the question of how many actual cores are at play. 7Zip is heavily floating point dependent. Not all programs are. In fact, at the time these CPU's were being made/released most CPU instructions were still being done on the interger side of things, thus the design logic. It was a gamble that didn't pay off. That doesn't mean that the integer cores are not individual cores.


----------



## mouacyk (Feb 13, 2019)

Here's an integer scaling benchmark:


> Myrimatch is a database search, and I believe it's using integer datatypes.  Update: Yeah, the FASTA file format is text-based.


Source: https://techreport.com/discussion/21865/a-quick-look-at-bulldozer-thread-scheduling?post=592039






Mask 55: 4 threads on 4 modules, no resource sharing
Mask 0f: 4 threads on 2 modules, with resource sharing


----------



## FordGT90Concept (Feb 13, 2019)

mouacyk said:


> Might be referring to this test done at Anandtech, where conclusion is flawed.  If you normalize the 7zip scores to the same clock speed, they are identical.  The relevance to this thread is that the FX-8150 is claiming 8 cores but the 2600K is only claiming 4 cores:


Also this post, done on Linux, with more chips:
https://www.techpowerup.com/forums/...back-to-haunt-amd.251758/page-10#post-3981565

7-Zip on FX-8350 behaves like 5.6 cores, not 8.



lexluthermiester said:


> Just because a quad core CPU came close does not settle the question of how many actual cores are at play. 7Zip is heavily floating point dependent. Not all programs are. In fact, at the time these CPU's were being made/released most CPU instructions were still being done on the interger side of things, thus the design logic. It was a gamble that didn't pay off. That doesn't mean that the integer cores are not individual cores.


Independent 8 cores come in at 8.  Independent quad cores come in at 4.  Independent dual cores come in at 2.

Look at 7-zip code.  It uses very, very little FPU operations.  It uses lots and lots and lots of ALU/memory operations, so many that the shared fetcher gets bogged down.  There's other benchmarks that show a similar bottleneck.



mouacyk said:


> Here's an integer scaling benchmark:
> 
> Source: https://techreport.com/discussion/21865/a-quick-look-at-bulldozer-thread-scheduling?post=592039
> 
> ...


Exactly.  Bulldozer sucks if it doesn't get a mixed workload.  The scheduler is inadequate to handle two threads in real time.


----------



## bb1000 (Apr 30, 2019)

*Bulldozer was not a bad CPU. price- performance. But it's not good for gaming. Now it's better than ever*

The problem was that AMD was right, the way forward was several core. But they were not market leaders
Intel was not interested in selling cheap multiple core systems. And the software manufacturers did not change their software either, so it supported and used multiple cores.

Ryzen also have the same problems with windows at the beginning, where software could not figure out how to use the processor correctly. 
- But the solution of Ryzen problems has make the Bulldozer  a better cpu too.


Second time, with Ryzen going better, AMD corrected the mistakes they made in their first series of many cores (Bulldozer)
Most importantly, software manufacturers here also play game manufacturers. 
Have start using them, maybe because they are now also available in Playstation and Xbox

Today, where the software supports multiple CPUs, the old Bulldozer actually better than 6 years ago. So It's not that bad.
So AMD is right. More CPUs were the future They just made some mistakes, with poor choice in design, and the market was not ready.


----------



## londiste (Apr 30, 2019)

The problem was never that Bulldozer had too many cores and this is not what is being argued in the court case or the article.


bb1000 said:


> Ryzen also have the same problems with windows at the beginning, where software could not figure out how to use the processor correctly.


The solution to this was to handle Bulldozer module as a single SMT-d core. The problem with this solution - including why it took as long as it did - is that it went against AMD's wishes.


----------



## Vya Domus (Apr 30, 2019)

There is no right way to use this type of architecture, as a matter of fact that was the point. To make a CPU that had less resources which could be used transparently by software.


----------



## londiste (Apr 30, 2019)

Vya Domus said:


> There is no right way to use this type of architecture, as a matter of fact that was the point. To make a CPU that had less resources which could be used transparently by software.


There is a right way to use this type of architecture. Due to shared scheduling resources, a module can be treated as a core normally would be with 2 threads being run on it thanks to SMT (CMT in this case). This quite automatically solves most of the Windows scheduling issues. Also, this was the eventual fix. Why was it not done in the first place? Because a module would show up in Task Manager as a single core. That is the main reason.

From technical perspective, AMD really had 2 objections - two threads in a module would share L2 that could prove a speed boost (this was fairly well debunked by some site, I think it was TechReport) and AMD's power management should be able to boost higher if only one module is used (which was true but that did not help enough for performance).

Edit:
I think this was the relevant Tech Report article:
https://techreport.com/review/21865/a-quick-look-at-bulldozer-thread-scheduling


----------



## Vya Domus (Apr 30, 2019)

londiste said:


> SMT (CMT in this case).



Decide which is it, the two are not equivalent. SMT is one thing CMT is another.



londiste said:


> This quite automatically solves most of the Windows scheduling issues.



It didn't solve anything. All that the "fix" did was make it so that Windows prioritizes scheduling threads onto separate modules first. Given how many hundreds or thousands of threads are scheduled at any given time and how dependent they can be between each other you can take a guess as to how effective this would eventually become when you start loading all cores. Ideally, you would want independent threads being scheduled first on different modules and dependent ones onto the same modules. This obviously isn't feasible in practice and even if it would be, eventually, it wouldn't make much of a difference either.

There is no right way to do it. The same argument can be had for simple multi core processors where you'd want dependent threads to be scheduled onto the same core so they can share the same L1/L2 cache. But when do you stop so that it doesn't hurt performance ? Same thing, nothing out of the ordinary here. As astonishing as it may seem all processors share resources on a certain level and face the same types of limitations.


----------



## londiste (Apr 30, 2019)

Vya Domus said:


> Decide which is it, the two are not equivalent. SMT is one thing CMT is another.


CMT is effectively an SMT solution and the distinction is more marketing than a technical distinction in addition to trying to take over an existing and different acronym. Yes, there is an additional Integer Core with 2 additional ALUs and 2 additional AGUs but the problem is still in scheduling and shared resources and it is the same problem that SMT has with largely the same solution.


Vya Domus said:


> It didn't solve anything. All that the "fix" did was make it so that Windows prioritizes scheduling threads onto separate modules first. Given how many hundreds or thousands of threads are scheduled at any given time and how dependent they can be between each other you can take a guess as to how effective this would eventually become when you start loading all cores. Ideally, you would want independent threads being scheduled first on different modules and dependent ones onto the same modules. This obviously isn't feasible in practice and even if it would be, eventually, it wouldn't make much of a difference either.
> 
> There is no right way to do it. The same argument can be had for simple multi core processors where you'd want dependent threads to be scheduled onto the same core so they can share the same L1/L2 cache. Same thing, nothing out of the ordinary here. As astonishing as it may seem all processors share resources on a certain level and face the same types of limitations.


Windows prioritizes scheduling threads into separate modules first because this results in best possible performance. As you said yourself, separating threads into dependent and independent is not feasible.
What else would there be to fix?


----------



## Vya Domus (Apr 30, 2019)

londiste said:


> CMT is effectively an SMT solution



No it's not. Someone even posted on here a paper describing exactly what CMT was (not by that name since it predates AMD's implementation) and how it relates to SMT and CMP.

There you go : https://www.eecis.udel.edu/~cavazos/cisc879-spring2008/papers/conjoining_micro04.pdf


----------



## FordGT90Concept (Apr 30, 2019)

The lawsuit is about AMD not being entirely truthful in their marketing--failing to make the distinction between conjoined core and a traditional core clear to the customer.  That raised performance expectations for consumers which AMD generally did not deliver on.

I doubt the court is even interested in getting technical.


----------



## londiste (May 1, 2019)

Vya Domus said:


> No it's not. Someone even posted on here a paper describing exactly what CMT was (not by that name since it predates AMD's implementation) and how it relates to SMT and CMP.
> There you go : https://www.eecis.udel.edu/~cavazos/cisc879-spring2008/papers/conjoining_micro04.pdf


CMP is different from CMT. Technically, CMT is part-SMT, part-CMP solution. When it comes to operating system scheduling arrangements, it is sufficiently SMT-like.

The only difference is the separate Integer Core assigned to each thread. This results in 70-80% boost from using both threads in a module as opposed to 30% from Intel's HT (which is textbook SMT). This does not play a part in operating system scheduling. Bulldozer module has single frontend, architectural features like Integer Cores and separate schedulers do not play a part for what operating system and its scheduler can do.


----------



## londiste (Aug 28, 2019)

AMD Settles:





						AMD agrees to cough up $35-a-chip payout over eight-core Bulldozer advertising fiasco
					

A great deal or were consumers Bulldozed by the chip giant?




					www.theregister.co.uk


----------



## RichF (Aug 28, 2019)

The nonsensical nature of the lawsuit continues to grow.

Firstly, it's meritless — at the very least — due to the language of the claim.

Secondly, it only applies to purchases made in California, which is utterly arbitrary.

Thirdly, it only arbitrarily applies to a subset of the consumer-grade 8 core FX chips.

_According to this article__._


----------



## FordGT90Concept (Aug 28, 2019)

Why do you think they settled?  To keep fighting it could draw the ire of the FTC which hugely expands the scope of the litigation.  $12.1 million is a small price to pay for sweeping this under the rug.

This case does put anyone on notice about trying to redefine what a "core" is.  Bulldozer had two "integer cores" per "core" and this misrepresentation in advertising lead consumers to believe they got more than they really did.


----------



## Vya Domus (Aug 28, 2019)

35$ for each 8 core chip sold in one state ? 

Everything went skin deep as expected, this ended up having almost nothing to do with AMD's definition of a core and more to do with the complaints of some consumers not getting the performance they expected.

 There was simply no way the plaintiffs could come up with a coherent argument against AMD's choice of architecture that would have affected all CPUs.

AMD did well to settle with this garbage.


----------



## FordGT90Concept (Aug 28, 2019)

It was a state suit, not federal.  Federal would need plaintiffs from many states to file and a law firm approved to argue cases in federal courts.  For whatever reason, they decided to only keep it in California.


----------



## lexluthermiester (Aug 28, 2019)

FordGT90Concept said:


> It was a state suit, not federal.  Federal would need plaintiffs from many states to file and a law firm approved to argue cases in federal courts.  For whatever reason, they decided to only keep it in California.


California is the special-snowflake capital of the continent after all.


----------



## eidairaman1 (Aug 29, 2019)

lexluthermiester said:


> California is the special-snowflake capital of the continent after all.



Thats Right


----------



## Shambles1980 (Aug 31, 2019)

never did i nor will i see these chips as 8 cores.
But given AMD went back to using real cores now have decent cpu's again and this law suit is now settled..
Maybe we can get back to having AMD vs Intel And both being Really viable choices.

If nothing else comes of this we can see that even bulldozer didn't manage to take AMD down, and now they are back in the game.
Given how fast people forgot all the Good cpu's AMD made before bulldozer. lets hope people forget about the terrible cpu's they made in an equally timely manner.


----------

