# AMD Orochi ''Bulldozer'' Die Holds 16 MB Cache



## btarunr (Sep 24, 2010)

Documents related to the "Orochi" 8-core processor by AMD based on its next-generation Bulldozer architecture reveal its cache hierarchy that comes as a bit of a surprise. Earlier this month, at a GlobalFoundries hosted conference, AMD displayed the first die-shot of the Orochi die, which legibly showed key features including the four Bulldozer modules which hold two cores each, and large L2 caches. In coarse visual inspection, the L2 cache of each module seems to cover 35% of its area. L3 cache is located along the center of the die. The documents seen by X-bit Labs reveal that each Bulldozer module has its own 2 MB L2 cache shared between two cores, and an L3 cache shared between all four modules (8 cores) of 8 MB. 

This takes the total cache count of Orochi all the way up to 16 MB. This hierarchy suggests that AMD wants to give individual cores access to a large amount of faster cache (that's a whopping 2048 KB compared to 512 KB per core on Phenom, and 256 KB per core on Core i7), which facilitates faster inter-core, intra-module communication. Inter-module communication is enhanced by the 8 MB L3 cache. Compared to the current "Istanbul" six-core K10-based die, that's a 77% increase in cache amount for a 33% core count increase, 300% increase in L2 cache per core. Orochi is built on a 32 nm GlobalFoundries process, it is sure to have a very high transistor count.

*View at TechPowerUp Main Site*


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## b82rez (Sep 24, 2010)

BL GG Intel Fanboys. AMD is back!


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## bpgt64 (Sep 24, 2010)

I'll believe it's a performance gain when I see the benchmarks.  Regardless of which side you take, competition is always good for the consumer.


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## KainXS (Sep 24, 2010)

wait for benchmarks before you start that, we've been through that before with amd


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## wolf (Sep 24, 2010)

b82rez said:


> BL GG Intel Fanboys. AMD is back!



silly 

cache isn't everything, reviews pretty much are.


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## ebolamonkey3 (Sep 24, 2010)

2011 is shaping up to be quite an interesting year


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## Completely Bonkers (Sep 24, 2010)

I remember the "massive cache" Gallatin P4's over Northwood. Didn't make more than 5% difference clock for clock except in very special circumstances.

So let's wait for benchmarks.

I would have thought there would be better gains by rethinking cache and memory entirely, possibly producing a separate socket for L3 cache just like in the old days. It would be so much cheaper to do it that way, you could easily pack 256MB cache. Yes, the latency would be worse than current on-die L3 cache, but with the space, heat and transistors saved, you could bump up L1 and L2 cache and win back any performance losses.  Plus you could build your L3 cache to order.


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## DaMulta (Sep 24, 2010)

That's it????? I wait for the day with 16 cores with 64MB of Cache


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## dir_d (Sep 24, 2010)

Well it seems Bulldozer is going to be faster when communicating with memory and other cores. I think if AMD just did that to a phenom 2 chip it would speed it up significantly. I really cant wait to see bulldozer in action.


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## bear jesus (Sep 24, 2010)

I would hope more faster cache could be a good thing but the main thing im interested in is how each modual performs, i'm really thinking about getting a high end sandy bridge or bulldozer to last me a couple years or so and that means i want as many and as fast a cores as possible as i would hope over the next few years more software will use more cores.


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## Rebelstar (Sep 24, 2010)

I'm totally noob in CPU technologies but I think 16MB cache it's a freaking cool, right?


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## xaira (Sep 24, 2010)

btarunr said:


> it is sure to have a very high transistor count.



so does fermi, i hope amd has the tdp under control, otherwise sandy will kick butt


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## bear jesus (Sep 24, 2010)

Rebelstar said:


> I'm totally noob in CPU technologies but I think 16MB cache it's a freaking cool, right?



It could be if put to use well but the core's are really importaint, either way we won't know untill the reviews really.


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## devguy (Sep 24, 2010)

One design win I really commend AMD for is their use of dynamic cache allocation between the "cores" on a module.  While many assume the sharing of cache (and other items like the FPU) will hurt single threaded performance, that really isn't the case.  When only one core is active per module, it has complete control over all the resources; thus a single core will have 2mb L2 cache at its disposal!  Also, when both cores on a module are active, they can inequitably share the resources (ie one core with .5mb L2 and another with 1.5mb L2 is possible).  Very cool technology.

For Bulldozer, there will be the option to have the OS prefer loading one core per module (like cores 1, 3, 5, 7) rather than just filling them up by modules (1, 2, 3, 4).  Both have benefits and faults: the first route has higher performance, but also higher power consumption; the second would be the exact opposite.

As far as the sharing of the FPU, in servers it will make hardly any difference.  In the desktop segment, AMD argues that should you be doing something that takes up so much FPU performance to slow down our modules, then you should be doing it on the GPU instead.


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## cadaveca (Sep 24, 2010)

I like this news. I ahve been saying for a couple of years now that AMD's cache design needed to cahnge, and here, they are doing something about it. That makes me even more interested in Bulldozer tech.


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## bear jesus (Sep 24, 2010)

devguy said:


> One design win I really commend AMD for is their use of dynamic cache allocation between the "cores" on a module.  While many assume the sharing of cache (and other items like the FPU) will hurt single threaded performance, that really isn't the case.  When only one core is active per module, it has complete control over all the resources; thus a single core will have 2mb L2 cache at its disposal!  Also, when both cores on a module are active, they can inequitably share the resources (ie one core with .5mb L2 and another with 1.5mb L2 is possible).  Very cool technology.
> 
> For Bulldozer, there will be the option to have the OS prefer loading one core per module (like cores 1, 3, 5, 7) rather than just filling them up by modules (1, 2, 3, 4).  Both have benefits and faults: the first route has higher performance, but also higher power consumption; the second would be the exact opposite.
> 
> As far as the sharing of the FPU, in servers it will make hardly any difference.  In the desktop segment, AMD argues that should you be doing something that takes up so much FPU performance to slow down our modules, then you should be doing it on the GPU instead.



I never knew it would be set up like that, kind of makes me even more sure i want to wait for bulldozer for my next full upgrade so that if it is a good cpu at a good price i can go for one or if not then i can get somethign from sandy bridge a little cheaper (hoping price drops will come over the time waited and if the consumer is lucky price drops that come with/after bulldozer).


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## cheezburger (Sep 24, 2010)

no surprise. they are try to fix the single thread performance hit due to the smaller l1 data/instruction. each core "only" had 8kb l1 data while the instruction cache is *share* by module which just only 64kb "2 way" in cache(could have be less...i think...) which is roughly 40kb per core compare to core's 64kb per core. big disadvantage. so all they can do is add more l3 cache to increase the performance or hoping not drop performance without tweak too much on the exist architecture that had been tape out and going to be release in 3 months. same thing intel did when realized northwood  its poor l1 cache will drag down performance they increase l2 cache from 256kb to 512kb. however orochi is 8 module 16 core processor so featuring 16mb l3 meant each core can use up to 1mb l3. still way below nehalem's 2mb per core. also unlike intel's architecture amd's cache heavily determine by the stage pipeline. lower stage pipeline won't take advantage on bigger cache. but since bulldozer will featuring 4+ghz i doubt this will be at least 20+ stage pipeline in this processor. but despite all these feature  as long as intel decide to increase ivy bridge's l2 cache from 256k per core to 512k per core amd will experience same horror they faced when core 2 came out.


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## HTC (Sep 24, 2010)

I wonder how hot these CPUs will get ...


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## ROad86 (Sep 24, 2010)

cheezburger said:


> no surprise. they are try to fix the single thread performance hit due to the smaller l1 data/instruction. each core "only" had 8kb l1 data while the instruction cache is *share* by module which just only 64kb "2 way" in cache(could have be less...i think...) which is roughly 40kb per core compare to core's 64kb per core. big disadvantage. so all they can do is add more l3 cache to increase the performance or hoping not drop performance without tweak too much on the exist architecture that had been tape out and going to be release in 3 months. same thing intel did when realized northwood  its poor l1 cache will drag down performance they increase l2 cache from 256kb to 512kb. however orochi is 8 module 16 core processor so featuring 16mb l3 meant each core can use up to 1mb l3. still way below nehalem's 2mb per core. also unlike intel's architecture amd's cache heavily determine by the stage pipeline. lower stage pipeline won't take advantage on bigger cache. but since bulldozer will featuring 4+ghz i doubt this will be at least 20+ stage pipeline in this processor. but despite all these feature  as long as intel decide to increase ivy bridge's l2 cache from 256k per core to 512k per core amd will experience same horror they faced when core 2 came out.





First orochi is 4 module - 8 core design. Second not only the size but how fast is the cache. Third it is very important how the prediction of instructions will work, if the design is good then you dont need big L1 cache which increase cost and die size. And yes 2mb per module 1 mb per core is the amount that bulldozer will have.


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## mechtech (Sep 24, 2010)

I want one, a server version with 8 or 16 GB of ecc ram   I don't know why though since I don't even work 1 core on my 955BE


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## cadaveca (Sep 24, 2010)

HTC said:


> I wonder how hot these CPUs will get ...



Very hot...apparantly we'll see a clockspeed decrease(which I assume is due to the high levels of cache), but IPC will increase. I'm kinda expecting 2.4ghz or so...maybe lower...for launch chips.


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## bear jesus (Sep 24, 2010)

cadaveca said:


> Very hot...apparantly we'll see a clockspeed decrease(which I assume is due to the high levels of cache), but IPC will increase. I'm kinda expecting 2.4ghz or so...maybe lower...for launch chips.



Just a good reason for me to get my first real water cooling setup  (assuming i am happy with the reviews of bulldozer)


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## cadaveca (Sep 24, 2010)

I don't know anything about it, really. However, there is mention of the clockspeed decrease on the AMD blog site. NOw that we have the info on cache size...1+1=2. Of course, there's lots of time between now and launch..seems to me they are refining the process, and a few bugs, at this point.


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## ROad86 (Sep 24, 2010)

mechtech said:


> I want one, a server version with 8 or 16 GB of ecc ram   I don't know why though since I don't even work 1 core on my 955BE




Haha me too!!!


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## bear jesus (Sep 24, 2010)

cadaveca said:


> I don't know anything about it, really. However, there is mention of the clockspeed decrease on the AMD blog site. NOw that we have the info on cache size...1+1=2. Of course, there's lots of time between now and launch..seems to me they are refining the process, and a few bugs, at this point.



Hmm i wonder if they will follow intel's lead (refering to the cooler that comes with the top end i7's) by using a better cooler for the high end cpu's if they run hot, would be nice to see a better cooler than the current one's as i am not really a fan of them.


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## afw (Sep 24, 2010)

cadaveca said:


> I don't know anything about it, really. However, there is mention of the clockspeed decrease on the AMD blog site. NOw that we have the info on cache size...1+1=2. Of course, there's lots of time between now and launch..seems to me they are refining the process, and a few bugs, at this point.



Well I read that Buldozer will do more instruction per clock ... so it will be interesting to see what its capable of 



> *Bulldozer: The Turbo Diesel Engine*
> In many respects, the Bulldozer architecture is comparable to a diesel engine. Lower RPM (clock-speeds), high torque (instructions per second). When implemented, Bulldozer-based processors could outperform competing processor architectures at much lower clock speeds, due to one critical area AMD seems to have finally addressed: instructions per clock (IPC), unlike with the 65 nm "Barcelona" or 45 nm "Shanghai" architectures that upped IPC synthetically by using other means (such as backing the cores up with a level-3 cache, upping the uncore/northbridge clock speeds), the 32 nm Bulldozer actually features a broad integer unit with eight integer pipelines split into two portions, each portion having its own scheduler and L1 Data cache.



source ---> http://www.techpowerup.com/129392/AMD_Details_Bulldozer_Processor_Architecture.html


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## xrealm20 (Sep 24, 2010)

Very interesting - if these cards are much more efficient per clock cycle, a decrease in clockspeed wouldn't be a bad thing.  Only time will tell at how well these new processors will fare, but here's hoping to them being an overclocker friendly processor unlike Intel's SB...


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## bear jesus (Sep 24, 2010)

xrealm20 said:


> Very interesting - if these cards are much more efficient per clock cycle, a decrease in clockspeed wouldn't be a bad thing.  Only time will tell at how well these new processors will fare, but here's hoping to them being an overclocker friendly processor unlike Intel's SB...



I hope for some nice overclocking as well as it will be time for my first water cooling setup if buldozer overclocks well and if i go for sandy bridge i will just get one of the K (overclocking) versions.

I really think the next year is going to be very exciting for pc hardware, sandy bridge and bulldozer and of corse amd's 6xxx and 7xxx cards and nvidia's kepler


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## JF-AMD (Sep 24, 2010)

cadaveca said:


> Very hot...apparantly we'll see a clockspeed decrease(which I assume is due to the high levels of cache), but IPC will increase. I'm kinda expecting 2.4ghz or so...maybe lower...for launch chips.



Actually, power and thermals are exactly the same with our current products.  Not sure where you are getting the clock speed info though.


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## cadaveca (Sep 24, 2010)

afw said:


> Well I read that Buldozer will do more instruction per clock ... so it will be interesting to see what its capable of



Yeah, i mentioned that too. Bulldozer, with the info we have now, sounds pretty good. BUt in reality, it has some competition, and we don't know too much about that either. Seems like a mixing of words from either side, trying to keep people interested. I truly hope that they can deliver...I have far more faith in GF's process than TSMC's, so I don't think I need to hope too much, but the TLB bug of Phenom 1 still rings fresh in my head.


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## bear jesus (Sep 24, 2010)

cadaveca said:


> but the TLB bug of Phenom 1 still rings fresh in my head.



I must admit that made me hold off untill the 9850be (already had an am2 motherboard thus why i did not switch to intel) even though it was a very specfic error, i would hope amd will have learnt from that mistake as if i have to wait for bulldozer if it is not a great processor from the start then they will be pushing me over to intel for the first time in years.


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## cadaveca (Sep 24, 2010)

JF-AMD said:


> Actually, power and thermals are exactly the same with our current products.  Not sure where you are getting the clock speed info though.



That's what alot of sites are saying, as you can see by the link "afw" posted. Anyway, that's good news, John, that you seem to hint at.



> Bulldozer: The Turbo Diesel Engine
> In many respects, the Bulldozer architecture is comparable to a diesel engine. *Lower RPM (clock-speeds), high torque (instructions per second). When implemented, Bulldozer-based processors could outperform competing processor architectures at much lower clock speeds,* due to one critical area AMD seems to have finally addressed: instructions per clock (IPC), unlike with the 65 nm "Barcelona" or 45 nm "Shanghai" architectures that upped IPC synthetically by using other means (such as backing the cores up with a level-3 cache, upping the uncore/northbridge clock speeds), the 32 nm Bulldozer actually features a broad integer unit with eight integer pipelines split into two portions, each portion having its own scheduler and L1 Data cache.



 I did say I know nothing, and it's not like I work for you guys, so of course all I have is my opinion.

 I was kinda actually hoping for a reduction in both power and thermals as the process matures, as currently, my 965BE is overheating on stock cooling(65c+ load). It's a horrible sample though.

Any info you can give that, of course, is more than welcome.


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## bear jesus (Sep 24, 2010)

cadaveca said:


> I was kinda actually hoping for a reduction in both power and thermals as the process matures, as currently, my 965BE is overheating on stock cooling(65c+ load). It's a horrible sample though.



That is exactly why i dont use stock cooling with my processor, i stuck the 965's hsf on an old athlon x2 thats in my htpc. 
I really hope amd brings a new hsf with the bulldozer 

*hint, hint* JF-AMD  (although yes i admit i don't have a clue on temps or cooling needs on the new core so the current hsf may be plenty for bulldozer)


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## Jstn7477 (Sep 24, 2010)

I hope AMD gets this generation right and can fight Intel. I'm liking the looks of Zacate vs. Intel Atom, and hopefully these desktop parts will be powerful and get AMD back into the game.


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## roberto888 (Sep 24, 2010)

SSE4.1, SSE4.2, the 16MB of L3 Cache, and the very high amount of transistors will make this CPU Kick Ass!!And also will make it very expensive!


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## mechtech (Sep 24, 2010)

I have a question.  With Sandy Bridge and Bulldozer completely new architecture, will Windows 7 OS be able to take full advantage of it performance wise, or does the OS matter not??


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## cadaveca (Sep 24, 2010)

mechtech said:


> I have a question.  With Sandy Bridge and Bulldozer completely new architecture, will Windows 7 OS be able to take full advantage of it performance wise, or does the OS matter not??



I do not think OS matters too much.  The "lighter" the OS, the more power left over for apps, etc, but other than that...


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## Dave63 (Sep 24, 2010)

I think this could be a game changer for ultra high end (blue-ray editing, composing sound tracks, servers, ect....). But software needs to get more in to the game to use more cores, most still do not use 3 cores at this point some do but very few. Thay are years away from fully using 6 cores this has been showin in bencemarks. I will be fun to see what happens. This is just my own view very new at this but learning alot as i go.


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## JF-AMD (Sep 24, 2010)

roberto888 said:


> SSE4.1, SSE4.2, the 16MB of L3 Cache, and the very high amount of transistors will make this CPU Kick Ass!!And also will make it very expensive!



I would not necessarily say that.


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## WhiteLotus (Sep 24, 2010)

JF-AMD said:


> I would not necessarily say that.



Who is this JF-AMD, an actual AMD spokesperson? 


And what would you not say, the expensive bit? I hope they are not...


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## JF-AMD (Sep 24, 2010)

Director of product marketing for servers at AMD


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## theonedub (Sep 24, 2010)

JF-AMD said:


> Director of product marketing for servers at AMD



You should get in contact with a Moderator or W1z to verify that and get you a title.


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## cadaveca (Sep 24, 2010)

WhiteLotus said:


> Who is this JF-AMD, an actual AMD spokesperson?
> 
> 
> And what would you not say, the expensive bit? I hope they are not...



John Fruehe

http://blogs.amd.com/work/author/jfruehe/


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## JF-AMD (Sep 24, 2010)

theonedub said:


> You should get in contact with a Moderator or W1z to verify that and get you a title.



Yeah, can't even edit my sig at this point


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## bear jesus (Sep 24, 2010)

JF-AMD said:


> Yeah, can't even edit my sig at this point


pm w1zzard or another mod so people can see you are an offical amd rep... just because lol


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## ERazer (Sep 24, 2010)

great news no doubt but im more interested if its gonna be am3 compatible or new socket


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## JF-AMD (Sep 24, 2010)

New socket for client, same sockets for server.


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## ERazer (Sep 24, 2010)

JF-AMD said:


> New socket for client, same sockets for server.



ty sir, guess gonna wait till i switch one of my rigs to amd for wcg, been wanting amd cruncher


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## cadaveca (Sep 24, 2010)

Can you confirm that this socket change was necessary to implement the expected performance improvements? 

What I'm actually really interested in, of course, is 3D performance. What key areas are targeted to improve this?


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## bear jesus (Sep 24, 2010)

To be honest i kinda of wish the bulldozer would come in a g34 socket (1974 pin) so that it came with quad channel ram... although i doubt it would make much different apart from benchmarks and maybe virtual machines.


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## JF-AMD (Sep 24, 2010)

yes.  using AM3 would have meant performance compromises.


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## JF-AMD (Sep 24, 2010)

bear jesus said:


> To be honest i kinda of wish the bulldozer would come in a g34 socket (1974 pin) so that it came with quad channel ram... although i doubt it would make much different apart from benchmarks and maybe virtual machines.



What if you got much greater throughput without having to increase memory channels?


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## bear jesus (Sep 24, 2010)

JF-AMD said:


> What if you got much greater throughput without having to increase memory channels?



Then that would be perfect, even more so with high density moduals becoming more normal as 8gb over a dual channel with a higher bandwith/throughput would be great imo.


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## cheezburger (Sep 24, 2010)

Completely Bonkers said:


> I remember the "massive cache" Gallatin P4's over Northwood. Didn't make more than 5% difference clock for clock except in very special circumstances.
> 
> So let's wait for benchmarks.



gallatin has 2mb l3 but the l2 is cut in half which was only 256kb compare to northwood's 512kb.  the difference in performance per clock is not increase but decrease as result. but only advantage of gallatin is the clock is very high compare to northwood's 3.06ghz limit




Completely Bonkers said:


> I would have thought there would be better gains by rethinking cache and memory entirely, possibly producing a separate socket for L3 cache just like in the old days. It would be so much cheaper to do it that way, you could easily pack 256MB cache. Yes, the latency would be worse than current on-die L3 cache, but with the space, heat and transistors saved, you could bump up L1 and L2 cache and win back any performance losses.  Plus you could build your L3 cache to order.



it would be the worst scenario to do so. i still remember how terrible a 850mhz slot1 pentium iii couldn't even pace a 533mhz coppermine because of 1/3 speed cache and extremely high latency. going back to slot will be stupid just like going back from core to netburst architecture. cheap price don't mean anything when you don't even have basic performance...plus why do we need these external low performance cache if we already have high speed ram available?



ROad86 said:


> First orochi is 4 module - 8 core design. Second not only the size but how fast is the cache. Third it is very important how the prediction of instructions will work, if the design is good then you dont need big L1 cache which increase cost and die size. And yes 2mb per module 1 mb per core is the amount that bulldozer will have.



the problem is that 64kb l1 instruction cache and l2 cache are uncore. that is a huge difference. it will make each of bulldozer core have theoretically *only 8kb l1 cache* while no l2 cache built in. it makes bulldozer quitetly different from its counterpart as intel wrap everything inside each core except pcie ctrl, memory ctrl and l3 cache. they need larger l1 cache because their l1 cache is way slower than intel's cache. and now their l1 cache on each core only 8kb. it will be hard to imagine they can outperform any intel line...

instruction prediction, same thing that intel had done long time ago when back to netburst time. such feature only work when you have ridiculous number of pipeline and a trace cache. but despite everything they had done with it they still end up performing pathetic in every benches


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## 1Kurgan1 (Sep 24, 2010)

Very cool to see this, can't wait to see what the Bulldozer can really do. Loving my 6 core, hopefully they will have some lower priced ones, thats why I've always been a fan of AMD.


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## CDdude55 (Sep 25, 2010)

Shaping out to be an awesome architecture, hopefully it can actually walk above i7 while maintaining a decent price tag. If that's the case and i actually have a job by then, i definitely will be considering moving up to this.


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## cheezburger (Sep 25, 2010)

CDdude55 said:


> Shaping out to be an awesome architecture, hopefully it can actually walk above i7 while maintaining a decent price tag. If that's the case and i actually have a job by then, i definitely will be considering moving up to this.



wait until bench come up first. but i doubt 8kb l1 cache on each core can do much of shit.......


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## DigitalUK (Sep 25, 2010)

JF-AMD said:


> What if you got much greater throughput without having to increase memory channels?



is that a hint? bulldozer could be dual channel


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## CDdude55 (Sep 25, 2010)

cheezburger said:


> wait until bench come up first. but i doubt 8kb l1 cache on each core can do much of shit.......



I am waiting for the benchmarks most definitely.


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## ROad86 (Sep 25, 2010)

cheezburger said:


> wait until bench come up first. but i doubt 8kb l1 cache on each core can do much of shit.......




http://techreport.com/r.x/bulldozer-uarch/bulldozer-frontend.jpg

The module's front end includes a prediction pipeline, which predicts what instructions will be used next.  A separate fetch pipeline then populates the two instruction queues—one for each thread—with those instructions.  The decoders convert complex x86 instructions into the CPU's simpler internal instructions.  Bulldozer has four of these, like Nehalem, while Barcelona has three.

Each module has a trio of schedulers, one for each integer core and one for the FPU.

This is from techreport and explains just fine. There is no 8kb L1 cache per core. If i am making a mistake please correct me. 

And since we have JF-AMD at the forum please explain this clearly!


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## cheezburger (Sep 25, 2010)

ROad86 said:


> http://techreport.com/r.x/bulldozer-uarch/bulldozer-frontend.jpg
> 
> The module's front end includes a prediction pipeline, which predicts what instructions will be used next.  A separate fetch pipeline then populates the two instruction queues—one for each thread—with those instructions.  The decoders convert complex x86 instructions into the CPU's simpler internal instructions.  Bulldozer has four of these, like Nehalem, while Barcelona has three.
> 
> ...



 it was confirm that it would be either 8~16kb incore l1 data cache while the instruction cache is uncored. very unlikely for a typical x86 design. if we all know how slow intel's l3 cache is because it's uncored then why bulldozer put everything out of core and make each of core only has basic functions?.  correct5 me about the stage pipeline in bulldozer but it seem to be unlike typical x86 design..... for what i know each prediction pipeline controls two instruction which theoretically make it 4 pipeline per core. but is it really powerful enough just use less pipeline like this? isn't it going to cost the slower clockrate per core? and how is it possible to separate stage pipeline from core and make it uncored?


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## JF-AMD (Sep 25, 2010)

L1 cache is not 8k. Check my blog in a week or so for the answer. There is l1 instruction shared between two cores, l1 data per core and l2 shared between 2 cores. L3 is shared at the die level


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## JF-AMD (Sep 25, 2010)

DigitalUK said:


> is that a hint? bulldozer could be dual channel



If am3+ socket also supports am3 chips, what do you think?


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## wahdangun (Sep 25, 2010)

JF-AMD said:


> If am3+ socket also supports am3 chips, what do you think?



wow, if that was true and not cripple bulldozer performance than thats was great, 

do you know if AMD will be release 980G chipset ?


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## JF-AMD (Sep 25, 2010)

I am a server guy, I don't know about client stuff.


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## bear jesus (Sep 25, 2010)

JF-AMD said:


> I am a server guy, I don't know about client stuff.



I must admit that i love the fact that you are active here and on other forums i visit, the personal touch along with just the fact that a company has people wiling talking to the bottom end customers really makes the difference when it comes to answering questiong and proving the point of "marketing talk" so i just wated to thank you for taking the time to talk to us through multiple forums and even more so out of office hours.


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## JF-AMD (Sep 25, 2010)

There is no such thing as a "bottom end customer". There are either customers or people who will be customers.  And both are the people that pay my salary.


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## ERazer (Sep 25, 2010)

JF needs a title  have u contacted the mods?


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## cadaveca (Sep 25, 2010)

I think he's legit.


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## cheezburger (Sep 25, 2010)

JF-AMD said:


> L1 cache is not 8k. Check my blog in a week or so for the answer. There is l1 instruction shared between two cores, l1 data per core and l2 shared between 2 cores. L3 is shared at the die level



incorrect.....the l1 instruction share by one module(2 cores) and l2 is share by two modules and l3 is share by all modules...

and about 8k l1 data....i remember i saw the spec from anandtech three months ago...however i found wiki had 16k l1 cache.....which i'd rather believe anandtech's source...


----------



## Techtu (Sep 25, 2010)

bear jesus said:


> Hmm i wonder if they will follow intel's lead (refering to the cooler that comes with the top end i7's) by using a better cooler for the high end cpu's if they run hot, would be nice to see a better cooler than the current one's as i am not really a fan of them.



Meh... the current stock cooler/fan comes with heat pipes, 10 years ago that was unheard off... be greatfull


----------



## bear jesus (Sep 25, 2010)

JF-AMD said:


> There is no such thing as a "bottom end customer". There are either customers or people who will be customers.  And both are the people that pay my salary.



Thank you for correcting me,you are right and once again i'm just thankful amd employes people like you who are willing to put the effort in with the community.


----------



## bear jesus (Sep 25, 2010)

Tech2 said:


> Meh... the current stock cooler/fan comes with heat pipes, 10 years ago that was unheard off... be greatfull



Ok i admit i am greatful for he copper based hsf wih copper heatpipes.... even if i did just  put it on a cpu thats 2 generation old and used my corsair h50 on the cpu the original hfs came with


----------



## Techtu (Sep 25, 2010)

bear jesus said:


> Thank you for correcting me,you are right and once again i'm just thankful amd employes people like you who are willing to put the effort in with the community.





bear jesus said:


> Ok i admit i am greatful for he copper based hsf wih copper heatpipes.... even if i did just  put it on a cpu thats 2 generation old and used my corsair h50 on the cpu the original hfs came with



Tut tut... double posting, that's a no no 

I understand where your coming from though but for any enthusiast, the stock coolers are just not enough, but then again if they was we wouldn't be very good enthusiast's would we


----------



## bear jesus (Sep 25, 2010)

Tech2 said:


> Tut tut... double posting, that's a no no
> 
> I understand where your coming from though but for any enthusiast, the stock coolers just are not enough, but then again if they was we wouldn't be very good enthusiast's would we



Sorry too much vodka and it beiong past 5am made me get confused too the fact i was posting within the same thread not 2 seperate ones lol.

but i suppose i can add this, i still have the old all aluminum heatsink that came iwth the athlon x2 that i am currently readying to be chopped up for other uses so i am greatful for the heatsinks that come with amd processors and am glad they are now heatpipe coolers as even with chopping them up i cam make good use of them. 

(no more drunken double posting... at least tonight lol )


----------



## JF-AMD (Sep 25, 2010)

cheezburger said:


> incorrect.....the l1 instruction share by one module(2 cores) and l2 is share by two modules and l3 is share by all modules...
> 
> and about 8k l1 data....i remember i saw the spec from anandtech three months ago...however i found wiki had 16k l1 cache.....which i'd rather believe anandtech's source...



You have 2 opinions to choose from:

1. A  reporter who has never touched the product 

or 

2. The director of product marketing for servers at AMD


Choose carefully, there will be a test at the end of the class.


----------



## Techtu (Sep 25, 2010)

JF-AMD said:


> You have 2 opinions to choose from:
> 
> 1. A  reporter who has never touched the product
> 
> ...



Well put


----------



## enaher (Sep 25, 2010)

JF-AMD said:


> L1 cache is not 8k. Check my blog in a week or so for the answer. There is l1 instruction shared between two cores, l1 data per core and l2 shared between 2 cores. L3 is shared at the die level



wow that's some agressive increase and management of cache, I hope performance increases, AMD's succes is good for us might bring prices down, and performance up.


----------



## bear jesus (Sep 25, 2010)

enaher said:


> I hope performance increases, AMD's succes is good for us might bring prices down, and performance up.



I agree, luckly i can wait untill after bulldozer is out to make my next big upgrade so if it is a great cpu/good value i of corse will go for it and if not then i would hope intel's current gen at the time will have a price drop around that time.

Although i admit i would prefer to go with amd as i had an amd k6 back in the day and was so happy with it and was lucky enough to go through 3 amd cpu's on my current motherboard so i would love to keep supporting them and if i am lucky go through another 2/3 cpu's on my next motherboard as i hate the idea of having to change motherboard every time i upgrade my cpu.


----------



## btarunr (Sep 25, 2010)

cheezburger said:


> incorrect.....the l1 instruction share by one module(2 cores) and l2 is share by two modules and l3 is share by all modules...



L2 is shared between two cores within one module.

And yes, JF-AMD indeed is director of product marketing for servers at AMD. Waiting for W1zzard to give him his title. He may have known details about Orochi months before anyone else did.


----------



## wahdangun (Sep 25, 2010)

btarunr said:


> L2 is shared between two cores within one module.
> 
> And yes, JF-AMD indeed is director of product marketing for servers at AMD. Waiting for W1zzard to give him his title. He may have known details about Orochi months before anyone else did.



so its basically a core2duo ?


----------



## Wile E (Sep 25, 2010)

I can't wait to see the numbers. I also hope that the new architecture still overclocks well. Competition at the top end would be killer. I want my $1000 chips to either become $500 chips, or become twice as fast for the $1000.


----------



## largon (Sep 25, 2010)

Oh boy... Here we go. 


cheezburger said:


> they are try to fix the single thread performance hit due to the smaller l1 data/instruction.


_As if_ they would have had _any_ problems slapping in an equally sized or larger than Hammer's L1s... It's not like this is AMD's first CPU architecture ever, or that adding such and amount would be of any die area concern. And for comparison, Nehalem has 32kB per core, 16kB per thread AND a tiny 256kB L2 - I bet Intel must be struggling with similar performance hit. 


cheezburger said:


> each core "only" had 8kb l1 data


Err... No. 
Each Bulldozer module has two set of integer pipelines and both of them have dedicated 16kB L1D. 16+16kB in total per module, 16kB per thread. 


cheezburger said:


> while the instruction cache is share by module which just only 64kb "2 way" in cache*(could have be less...i think...)*


Bulldozer's L1I _is_ 64kB, that's been public for some time now. About the bracketed comment; you think it could have been smaller, or you aren't sure what size it is? 


cheezburger said:


> which is roughly 40kb per core compare to core's 64kb per core. *big disadvantage.*


If you say so... 


cheezburger said:


> so all they can do is add more l3 cache to increase the performance (...) same thing intel did when realized northwood  its poor l1 cache will drag down performance they increase l2 cache from 256kb to 512kb.


And by coincidence, Intel is doing the same. "Obviously" they too must be patching Core m-arch's "poor L1s and L2s" by adding cache levels and continuously increasing their size. 


cheezburger said:


> however orochi is 8 module 16 core processor


No. Orochi is 4 module, 8 thread core. 


cheezburger said:


> so featuring 16mb l3 meant each core can use up to 1mb l3. still way below nehalem's 2mb per core.


Durrr... 
Bulldozer _does not_ have a 16MB L3, even reading the thread title should give away the L3 is 8MB. 2MB L2 + 2MB L3 per module, that is. Thus, per module, Orochi has 8× as much L2 vs. Nehalem and equal L3-ratio.


cheezburger said:


> also unlike intel's architecture amd's cache heavily determine by the stage pipeline.


Strange conclusion considering the public, (that includes me and you) don't know Bulldozer's exact pipeline length, yet. 


cheezburger said:


> lower stage pipeline won't take advantage on bigger cache. but since bulldozer will featuring 4+ghz i doubt this will be at least 20+ stage pipeline in this processor.


Broken sentence. What are you trying to say? 
You do believe it is 20+ stage or you do not? 
Also, the clock rates are completely unknown to public.  


cheezburger said:


> but despite all these feature  as long as intel decide to increase ivy bridge's l2 cache from 256k per core to 512k per core amd will experience same horror they faced when core 2 came out.


Oh really? Now one can only wonder why didn't Intel see such a shortcoming of their L2 before taping out Nehalem, Sandy Bridge... They must have missed the fact their chips' L2 had shrinked to a fraction of the size compared to Conroe, Penryn. 

PS.
In case you find some parts of my reply sarcastic, it is highly likely you are right. 

*Abstract for those with the "TL;DR" -syndrome*:
Burger, please _get your facts straight_. The factual errors I've pointed out are public knowledge, go read them. And please do pay attention to writing proper English, often it is impossible to figure out what you're trying to say as many of your sentences are missing words and the words that are there are often misspelled.


----------



## Wyverex (Sep 25, 2010)

largon, save your breath, he even argued with AMD guy and called his info false, lol
JF-AMD, thank you for your contribution to the thread.

I'm really looking forward to Bulldozer and I hope it succeeds, both in Server and Desktop markets


----------



## btarunr (Sep 25, 2010)

largon said:


> Durrr...
> Bulldozer _does not_ have a 16MB L3, even reading the thread title should give away the L3 is 8MB. 2MB L2 + 2MB L3 per module, that is. Thus, per module, Orochi has 8× as much L2 vs. Nehalem and equal L3-ratio.



Sorry largon, but it's 2 MB L2 per module, 8 MB L3 shared between all four modules. There is no L3 cache at the sub-modular level. Hence the total cache is 16 MB (AMD denotes total L2 + L3 as "total cache").


----------



## largon (Sep 25, 2010)

btarunr said:


> Sorry largon, but it's 2 MB L2 per module, 8 MB L3 shared between all four modules. There is no L3 cache at the sub-modular level. Hence the total cache is 16 MB (AMD denotes total L2 + L3 as "total cache").


You're misinterpreting me. My "2MB L3 per module" is only a way to state _a ratio_, not actual configuration. 




cheezburger said:


> the problem is that 64kb l1 instruction cache and l2 cache are uncore. that is a huge difference. it will make each of bulldozer core have theoretically *only 8kb l1 cache* while no l2 cache built in.


What? 
That's just not true. Bulldozer's L1I and L2 are fully integrated parts of the BD module and they run at core freq, and no less. 


cheezburger said:


> they need larger l1 cache because their l1 cache is way slower than intel's cache.


Bulldozer has 4T L1 latency, same as Nehalem's. 





cheezburger said:


> and now their l1 cache on each core only 8kb. it will be hard to imagine they can outperform any intel line...


Especially if the one "imagining things" is using incorrect numbers... 


cheezburger said:


> instruction prediction, same thing that intel had done long time ago when back to netburst time. such feature only work when you have ridiculous number of pipeline and a trace cache.


What can I say, once again you astound (but not surprise) by posting utter nonsense. 


cheezburger said:


> but despite everything they had done with it they still end up performing pathetic in every benches


Feeling particularly "blue", perhaps? And by saying that I'm not referring to mood. 

But what can you do, a troll is a troll is a troll.


----------



## TAViX (Sep 25, 2010)

I hope it will consume less than 200W...


----------



## ROad86 (Sep 25, 2010)

I have a question that may JF-AMD may not now since he is in the server section, but I want to ask will AMD present in the future 6 core(3 module) or 4 core(2 module) products with lower price?

Or it will be variation at the clock rate of the Orochi design?


----------



## Imsochobo (Sep 25, 2010)

cadaveca said:


> I think he's legit.



He answer stuff like i answer stuff about my company, as short as possible


----------



## Imsochobo (Sep 25, 2010)

Will amd improve the southbridge, harddrive performance, and such ?
Your nb's is quite good.

2nd, theese will be so diffrent compared to K8 K10 K10,5 that vmotion wont work from K10,5 -> bulldozer?

If we still can i'll be praising amd for my servers for a few more years!


----------



## btarunr (Sep 25, 2010)

Imsochobo said:


> Will amd improve the southbridge, harddrive performance, and such ?



There's nothing particularly bad with AMD's storage performance with a proper mode (AHCI or RAID) and proper driver (AMD over Microsoft) installed. The RAID controller sucked only till SB600 southbridge (which had a Silicon Image logic that wasn't implemented so well). SB700/SB710/SB750 is on par with ICH10/R, SB850 has no match (SATA 6 Gb/s).


----------



## Imsochobo (Sep 25, 2010)

btarunr said:


> There's nothing particularly bad with AMD's storage performance with a proper mode (AHCI or RAID) and proper driver (AMD over Microsoft) installed. The RAID controller sucked only till SB600 southbridge (which had a Silicon Image logic that wasn't implemented so well). SB700/SB710/SB750 is on par with ICH10/R, SB850 has no match (SATA 6 Gb/s).



Still not up there, I wonder why a SSD scores 7.3 with my SB750 and with my ICH10/R it does 7,5 in windows.
Why it has about 10 mb/sec more sequential, better 4k, 512, and so on. its not by much.
But its getting beaten by both nvidia and intel.

http://www.tomshardware.com/reviews/ich10r-sb750-780a,2374-10.html
I just googled abit to find some review. never trusted toms too much, but yeh 

Its not like i'm headbanging my head to the wall of my ssd performance, it's just: there are more to get here!


----------



## btarunr (Sep 25, 2010)

Those are access times (in the URL you posted). The lower the better. You can see how SB750 and ICH10R are on par in most access time tests. Anyway, 7.3 to 7.5 is a big deviation in WPI but maybe other factors were at play (such as you may have tested the ICH10R system on a clean(er) installation than the SB750 system).


----------



## ROad86 (Sep 25, 2010)

Windows numbers are inaccurate. In my build a western digital 640gb at a giagabyte 790xt-UD4P was scoring at IDE interface 5,9. After the format I changed the IDE to AHCI and it scores now 7,5. I dont know why I run the test many times and still the same result. (By the way SB750 is the southbridge)

Now I want to make another question to JF-AMD which is related to the previous one. In the blog he mentions that from 33% more cores we take 50% more performance. The test was between magny-cours (12 core) and interlagos(16-core and bulldozer architecture). We will take the same ammount increase of perfomance and the client processors? Because the increase from 6 to 8 cores equals nearly 33, should we expect 50% perfomance jump form phenom II? If this happens will it comes with an equal increase at the price?


----------



## btarunr (Sep 25, 2010)

Again, the client processors will perform different. Client systems will use lower number of DIMMs, usually lower latency memory (DDR3 servers use failsafe 1066 MHz @ 9-9-9-24T settings as a standard). Client processors have 3/4 HT links disabled, etc., etc. So server to client comparison isn't apples-to-apples.


----------



## ROad86 (Sep 25, 2010)

btarunr said:


> Again, the client processors will perform different. Client systems will use lower number of DIMMs, usually lower latency memory (servers use failsafe 1066 MHz @ 9-9-9-24T). Client processors have 3/4 HT links disabled, etc., etc. So server to client comparison isn't apples-to-apples.




I agree totally with you. But imagine (and that is speculations) a perfomance jump up to 40%. It will match or even outperfom sandybridge. If that happens what the prices wiil be? I wish they wont increase the prices as intel does.


----------



## JF-AMD (Sep 25, 2010)

Folks, all we have disclosed in public about cache is the L1 size (that I posted earlier.)

We have not disclosed L2 or L3 sizes, so whatever you quote is not confirmed, only speculation.

L1 is within the core.  L2 is within the module. L3 is within the die.


----------



## btarunr (Sep 25, 2010)

ROad86 said:


> I agree totally with you. But imagine (and that is speculations) a perfomance jump up to 40%. It will match or even outperfom sandybridge. If that happens what the prices wiil be?



If AMD has a faster processor architecture, it will ask whatever it wants to. It's a corporation. 

Just as Intel asks $999 for its Extreme Edition SKUs, AMD used to ask for the same $999 for its FX SKUs (back when K8 was the best client CPU architecture out there). Even today AMD can try to ask for more than $275, if it wants to develop the QuadFX platform. Enthusiasts always have $999 to spend on one Core i7 or two DSDC-capable Phenom II chips in the s1207 package. It's just that AMD's client CPU team has to wake up to that realization. Power and board costs are lame excuses.


----------



## JF-AMD (Sep 25, 2010)

ROad86 said:


> Windows numbers are inaccurate. In my build a western digital 640gb at a giagabyte 790xt-UD4P was scoring at IDE interface 5,9. After the format I changed the IDE to AHCI and it scores now 7,5. I dont know why I run the test many times and still the same result. (By the way SB750 is the southbridge)
> 
> Now I want to make another question to JF-AMD which is related to the previous one. In the blog he mentions that from 33% more cores we take 50% more performance. The test was between magny-cours (12 core) and interlagos(16-core and bulldozer architecture). We will take the same ammount increase of perfomance and the client processors? Because the increase from 6 to 8 cores equals nearly 33, should we expect 50% perfomance jump form phenom II? If this happens will it comes with an equal increase at the price?



You can't do the math that way, but there will be a very good performance gain.

With servers you are measuring throughput, which is hom much stuff you can jam through a pipe at full utilization.  Client loads are more bursty, so throughput is a less relevant measure.


----------



## ROad86 (Sep 25, 2010)

JF-AMD said:


> You can't do the math that way, but there will be a very good performance gain.
> 
> With servers you are measuring throughput, which is hom much stuff you can jam through a pipe at full utilization.  Client loads are more bursty, so throughput is a less relevant measure.




Thanks JF!


----------



## largon (Sep 25, 2010)

JF-AMD said:


> Folks, all we have disclosed in public about cache is the L1 size (that I posted earlier.)
> 
> We have not disclosed L2 or L3 sizes, so whatever you quote is not confirmed, only speculation.


_Interesting_, the fact you commented... 


Now that I took another look on the released (heavily pixelated & manipulated) die shot, it might just be Bulldozer's L3 is either just 6MB, or whopping 12MB. That, or the cells in L3 are actually _less dense_ than those in L2.


----------



## bear jesus (Sep 25, 2010)

largon said:


> _Interesting_, the fact you commented...
> 
> 
> Now that I took another look on the released (heavily pixelated & manipulated) die shot, it might just be Bulldozer's L3 is either just 6MB, or whopping 12MB. That, or the cells in L3 are actually _less dense_ than those in L2.



The one thing i keep thinking about is that i remember articles saying that the cores got photoshopped to hide some things so would not the die shots not be that informative right now even for speculation?


----------



## de.das.dude (Sep 25, 2010)

Gooooooooooooooooooooooooooo amd!!


----------



## cheezburger (Sep 25, 2010)

largon said:


> Oh boy... Here we go.
> 
> _As if_ they would have had _any_ problems slapping in an equally sized or larger than Hammer's L1s... It's not like this is AMD's first CPU architecture ever, or that adding such and amount would be of any die area concern. And for comparison, Nehalem has 32kB per core, 16kB per thread AND a tiny 256kB L2 - I bet Intel must be struggling with similar performance hit.
> Err... No.
> ...



that...is the most aggressive post i ever read... 

first off intel is not 16kb per thread as you may think, largely a core that can do 2 thread is not necessary divide l1 cache in half as NOT all nehalem processor like i7 that came with hyperthreading...and pretty much you have no idea/no understanding about hyperthreading...hyperthread is pipeline measuring, when hyperthreading enable it will use the unused part of clock cycle/pipeline and simulate a "fake" core  during process. which is technically still 32kb l1 data per thread.

the hard fact is bulldozer cores are NOT divide from module, they are the individual core that pair of core are wrap together into each module with a l1 instruction cache in the middle and wiring between two of core. so the instruction cache is uncored for sure(while nehalem's l1/l2 are bulit in each of their core and only left a larger l3 cache outside the core with ringbus connected.) why i said it was 8kb, because it was rumor to be between *8~16kb* in early 2009...since most said that it will use far smaller cache than it was on k10 (128kb!!) some site took smaller number but wth? it's still in speculation period and who knows amd might increase their cache to 32k or even 64k l1 data per core? plus even under 16kb, with running 2 threads it will divide cache into 8kbx2 because they don't have hyperthreading like intel had that optimize single core in multi-threading without drop too much of performance...

now before you start hammer me with your ignorance...you have to understand one thing:

*UNCORE MEANS ANYTHING THAT IS NOT BUILD INSIDE THE CORE!* even they are still in the same die/module it doesn't change the fact these cache are uncore....which i'm not wrong at this point! it makes it look like each core only had 8`16k l1 data while no L1I built in!

before calling me troll you better measure how much you know about miroarchitecture first....





largon said:


> You're misinterpreting me. My "2MB L3 per module" is only a way to state _a ratio_, not actual configuration.
> 
> 
> What?
> ...



bulldozer has same latency as nehalem? that's news to me...no! amd has long history of bad performance on their cache because of low quality silicon yield during production and  bad wiring in die area. what do you think why amd bother go 128k l1 cache design if their cache were so powerful? just so you know in phenom the l1 cache latency can be as high as 10~12 clock per cycle while core 2 is only 2.5clock per cycle. that just not for long ago and what makes you think they are be tweak over night? and with such small cache? it sounded more ridiculous than cayman that only has 32 rops... larger + faster l1 cache means better performance. neither amd will get better result if they keep such garbage design on bulldozer. all they need is just put 128k l1 data in each core and bulldozer will trump nehalem for sure. in IT field TDP means shit! performance is *ALWAYS* measure by how big die size and how many transistor.it will be stupid because smaller l1 cache = performance loss. also they still had alot of room to put cache in their core because their new core are only 1/2~1/3 of nehalem's single core. if they want to win this they better increase their die size by adding more cache lik 256kb l1D per core +128kL1I, 4mb l2 per module and 32mb share l3 cache and feature 400mm^2


oh about pipeline, you can cehck this:

http://www.amdzone.com/phpbb3/viewt...id=1b04a4780b037a6ab2c09efd2ffe3f19&start=350
it was confirm that they are under work on more pipleline and feature higher frequency..don't know if it's true but that will be stupid too

also the l1 cache has confirmed  to be 4 cycle rather than previously thought of 3 cycle(worse than p3...). i mean seriously if they can't outperform intel why dont they just increase more cache instead? if 128k can't beat intel's 64k then why not 256 or even 512k on l1 cache?


----------



## JF-AMD (Sep 25, 2010)

bear jesus said:


> The one thing i keep thinking about is that i remember articles saying that the cores got photoshopped to hide some things so would not the die shots not be that informative right now even for speculation?



Everything in the processor was photoshopped, not just the cores.


----------



## bear jesus (Sep 25, 2010)

JF-AMD said:


> Everything in the processor was photoshopped, not just the cores.



Thank you for confirming that, i was little confused as to if it was cirtain area's or more. But this just makes me wonder how accurate anyone's speculations on any part of the cpu could be.


----------



## Techtu (Sep 25, 2010)

cheezburger said:


> Spoiler
> 
> 
> 
> ...




I'm no expert but are you saying a higher L1 cache is better... I'm sure that isn't the case.

doesn't it go a little something like this...

Smaller L1 cache has better performance over a larger L1 cache.

Larger L2 cache has better performance over a smaller L2 cache.

Same rule as the L2 cache for L3 cache I believe.

EDIT: ignore the above, I realised my mistake shortly after posting.


----------



## DigitalUK (Sep 25, 2010)

JF-AMD said:


> Everything in the processor was photoshopped, not just the cores.



lol nice one, JF-AMD is there anything you can tell us that is real about bulldozer that hasnt been speculated on in this thread. obviously without getting yourself in trouble.  drooling..


----------



## JF-AMD (Sep 25, 2010)

cheezburger said:


> that...is the most aggressive post i ever read...
> 
> first off....



I don't even want to try to pick your response apart to pull out the things that you stated (almost as fact) that were a.) pure speculation on the web and b.) wrong.

I would say that you have some things right, but more wrong and your basic understanding of how the processor architecture is built/interacts is off.

I recommend reading the bulldozer blogs, and most importantly the questions at the end (each blog has about 30+ comments where I am answering questions.)  

That is probably the best place to start if you truly want to understand the architecture.  But, first and foremest, you have to put aside some of the traditional understandings of how things work in semiconductor world and take into consideration that this is a "new dawn" for processor design and technology.  You can't apply old assumptions to a new architecture.


----------



## JF-AMD (Sep 25, 2010)

DigitalUK said:


> lol nice one, JF-AMD is there anything you can tell us that is real about bulldozer that hasnt been speculated on in this thread. obviously without getting yourself in trouble.  drooling..



Read the bulldozer blogs, especially the "20 questions" blogs.  And especially the comments after each blog.  I give a LOT of detail there.  That should cover everything that is fit to print.


----------



## cheezburger (Sep 25, 2010)

JF-AMD said:


> I don't even want to try to pick your response apart to pull out the things that you stated (almost as fact) that were a.) pure speculation on the web and b.) wrong.
> 
> I would say that you have some things right, but more wrong and your basic understanding of how the processor architecture is built/interacts is off.
> 
> ...



this is what i got from you..



> *We get asked that a lot.  The key is that a single core that would be able to compete with the throughput of two smaller cores would consume a disproportionate amount of die space and consume more power.  Taking Bulldozer and turning each module into one “big core” instead of two cores with some shared resources would net you a disproportionately higher price and disproportionately higher power consumption.
> 
> In reality what we are doing is driving efficiency.  And don’t worry about the single threaded performance –we have already stated publicly that Bulldozer single threaded performance is expected to be higher than our current core architectures.
> 
> *


 

so make the point short, you guys make such small individual core inside each module was because of production cost and power consumption?  result: *amd giving up on high end user*...same thing i will be disappoint on hd 6000 if it turns out to be a "mainstream card". along side with"mainstream processor" like this...if such mainstream design can outperform nehalem then i'll never come back to this forum as result of punishment...

however small core strategy is completely wrong. and how much efficiency you can get from a smaller core?


----------



## CDdude55 (Sep 25, 2010)

JF-AMD said:


> Read the bulldozer blogs, especially the "20 questions" blogs.  And especially the comments after each blog.  I give a LOT of detail there.  That should cover everything that is fit to print.



Very nice blog, definitely gonna give it a read.


----------



## cadaveca (Sep 25, 2010)

cheezburger said:


> so make the point short, you guys make such small individual core inside each module was because of production cost and power consumption?  result: *amd giving up on high end user*...same thing i will be disappoint on hd 6000 if it turns out to be a "mainstream card". along side with"mainstream processor" like this...if such mainstream design can outperform nehalem then i'll never come back to this forum as result of punishment...



I think the biggest point is that without an actual Bulldozer-based core on your hands, and a supporting motherboard, any claims of greatness, and likewise, any worries, can only be speculation.

I've got a big bone to pick with AMD. A BIG ONE.


But the fact that JF is here says that they really aren't forgetting about the high-end user. Or else he wouldn't be posting.

Like really, many years ago, when the ATI/AMD merger was fresh, AMD quite publically stated that they were not going to focus on the enthusiast market, and they didn't

To me, the TWKR chips was AMD waving a big flag..."OK, you guys...were coming back."( Of course, they never sent me one, so that was a wasted marketing effort, barely see anyone using them, either....)

Since then, Thuban came out. Who do you think those cpus are really targeting?

Give them some time...If I can deal with the crappy vgas and cpu I got now, until new stuff is released, so can anyone else.




CDdude55 said:


> Very nice blog, definitely gonna give it a read.



...I told ya there was some good, official, info on the AMD blog site...


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## DigitalUK (Sep 25, 2010)

Thanks JF-AMD some really good information there, going to take me all evening to go through all that but thanks. its nice to have some real information from the source.


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## bear jesus (Sep 25, 2010)

cadaveca said:


> If I can deal with the crappy vgas and cpu I got now, until new stuff is released, so can anyone else.





really? "Phenom II 965BE @ 3.6ghz/2400NB 300HTT and XFX HD5870 XXX x2 @ 900/1250" is crappy to you? 

I am still on an old am2+ board with ddr2, and a single 4870.....  i'm kind of offended now


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## cadaveca (Sep 25, 2010)

, well, I'm running triple monitors in Eyefinity. I am unable to get what I consider an acceptable level of performance...I have to sacrifice image quality to do so. I'm sure you've seen at least one of my many posts complaining about my system...it's really unbalananced, in the least... 

That 965BE is probably the worst Phenom2 I've had. I cannot get more than that 3.6ghz stable, due to heat, and when I cool it better, it maxes out @ 3.8ghz. As it is, 3.6ghz requires 1.425, under my current cooling.
 Most 965 will do 3.8ghz with far less than my 3.6ghz.

My vgas overheat, my second card is useless except in Eyefinity, and then it only gives a very slight performance boost...like 10%. I spent $450, to get a $45 performance boost.

I'm sure if you were dealing with the issues I am, you would feel the same way. I was much happier with my 955 and 4890's...that seemed like a very well-balanced system, performance-wise.


So, a big part of the performance, or lack thereof, seems to be cpu. So, of course, I'm paying close attention to Bulldozer...I'll probably buy on release.

I guess I'm still an AMD fanboy...I just cannot take my butt to the store, and buy i7. Might fix things for me, but I just can't do it.:shadedshu


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## bear jesus (Sep 25, 2010)

cadaveca said:


> , well, I'm running triple monitors in Eyefinity. I am unable to get what I consider an acceptable level of performance...I have to sacrifice image quality to do so. I'm sure you've seen at least one of my many posts complaining about my system...it's really unbalananced, in the least...
> 
> That 965BE is probably the worst PHenom2 I've had. I cannot get more than that 3.6ghz stable, due to heat, and when I cool it better, it maxes out @ 3.8ghz. As it is, 3.6ghz requires 1.425, under my current cooling.
> 
> My vgas overheat, my second card is useless except in Eyefinity, and then it only gives a very slight performance boost...like 10%. I spent $450, to get a $45 performance boost.



Ok yes i admit in your situation you are right, and it does kind of suck so i can understand your point now.
Admitdly i'm just running a single 1680x1050 monitor and i was lucky to get a phenom II 965 that will get above 4ghz with enough voltage. apart from a new gpu in a few months i'm more than happy to wait with what i have untill bulldozer so i can make my choice of new cpu, motherboard and ram.

*edit* i wish you had got a chip that could get up to about 4ghz or more (i kept trying to get 4.2ghz stable but mine is just not happy with it) as i think you would have been muc happyer with it.


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## cadaveca (Sep 25, 2010)

Well, you know, I bought the very best AMD had to offer at the time. And I went from a QX9650...down to E8400...then 720BE...and all through that, I was pretty happy with AMD. 720 BE wasn't as fast as E8400 @ 4.0ghz, but it seemed far smoother.

I recently sold a 955 to another member here...it did 4ghz...unfortunately, it wasn't enough, so I moved on to the 965. Of course, the 965 sucked...

I've got a 1090T and 2x GTX480 here too...waiting for Crosshair 4 extreme to build it up. that cpu might do 4ghz...I'm tempted to rip the box open...but maybe I'll just go get another today.

I have to look towards bulldozer. Although i7 might offer a wee bit more performance than I have now, my "high-end" monitor setup seems to require more than i7 can give, even. I need 4.6ghz or so, I think...


Everything about Bulldozer sounds good. In my testing with 965, it seems a big part of my performance issues is not really cpu speed...but the memory controller speed. And that is looking to get a big boost in performance...

AMD has been pretty open with what is physically going to change, but in such a way that the performance that those changes offer doesn't exactly become evident. As JF said, this really seems to be a fundamental shift in cpu design, and I am really hoping that it all falls in line together.


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## bear jesus (Sep 25, 2010)

cadaveca said:


> AMD has been pretty open with what is physically going to change, but in such a way that the performance that those changes offer doesn't exactly become evident. As JF said, this really seems to be a fundamental shift in cpu design, and I am really hoping that it all falls in line together.



I admit that is one of the reasons i am so willing to wait, i feel there is no point in me going with an i7 with both intel's and amd's nex gen coming out relativly soon (considering that i have had most of my setup for several years), i have a lot of hope that bulldozer will be worth the wait.... and if not intel will get my business for the first time in years  although i doubt that as at least for me amd has been giving me the best value for money for years and i dont expect that to change.

Also on another note, i have been reading through JF's blog and have been getting a little too excited from the things i read, i have it bookmarked and will be popping back there very often. I suggest anyone interested in buldozer takes a loook.


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## cheezburger (Sep 25, 2010)

Tech2 said:


> I'm no expert but are you saying a higher L1 cache is better... I'm sure that isn't the case.
> 
> doesn't it go a little something like this...
> 
> ...



what do you think intel/ibm want to go 64k on their l1 cache while they can use the exist 32k on both p6/g4 architecture?? why doubles it? and why amd made such big jump and made world largest l1 cache of 128k when back to k7 era? because L1 is important...if not then why everyone try to enlarge the size? smaller l1 cache can outperform larger l1 cache? yes but depends on clock cycle, latency/missing rate and quality of silicon yield.  currently peyrin/wolfdale/nehalem have far lower latency/missing rate and clock cycle than bulldozer's design while it's more than 3 time larger. bulldozer's l1 cache is revealed to be high latency (on amd's exist cache architecture a phenom's 128k l1 cache will be 10~12/cycle  4~5 /cycle on 16kb and 3~4/cycle on 8kb) if they hope it will drop the latency by just reduce the l1 cache will be a stupid idea. of cause unless they want to clock up really high to fix that missing penalty. but it will end up to be another netburst... 




cadaveca said:


> I think the biggest point is that without an actual Bulldozer-based core on your hands, and a supporting motherboard, any claims of greatness, and likewise, any worries, can only be speculation.
> 
> I've got a big bone to pick with AMD. A BIG ONE.
> 
> ...



i think biggest reason is amd actually thought they can tweak performance on cpu just like what they did on gpu....by adding more smaller core on high end product with relative low price..however cpu is nothing like gpu that you can add as much shader to increase performance on r770. but it seem likely bulldozer is a cpu version of r770.......

it was first romor(again rumor rumor rumor!!! don't frame me plz!) that amd going to make the core so small that only 2kb l1 cache per core and use SIMD unit to "chain" core each core, each module will act as SIMD unit and 2 modules will form a SIMD cluster and l1 instruction cache is share by all simd cluster. while the original oroshi will have 8 SIMD cluster(*again it was rumor so don't bash or attack me....please!*) and each  2 SIMD cluster will share a 256kb l2 cache and all SIMD cluster will share 8mb L3 cache...it was like that in early debut. orochi would end up to be a world first 32 core processor if the concept like this...... if that design was adopted it would be terrible to imagine how bad the single thread performance would be..as that 32 core orochi in fiction timelime was target on quad core nehalem/sandies/ivy

amd did promise they won't go high end design...and they did fulfill that promise completely...hd 5xxx was suppose to be mainstream but due to the fail of fermi which end up become *high end* line...which it was coincidence...phenom 1/2 was supppose to be mainstream and they did play well on their role...they really need a bigger core design if they want to outpace intel and nv..


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## JF-AMD (Sep 25, 2010)

OK, let me see if I have all of the facts straight.

You believe that L1 is the make or break feature in an architecture?
You believe the L1 is outside of the core, yet it is inside the core?
You are posting based on rumors and when confronted with the right information from a legitimate source you don't admit you're wrong?
You have ~60 posts, 10 of which are about bulldozer, all are critical of it?
The rest of the posts do a pretty good job of picking on AMD from a graphics front.

OK, I got it now.


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## cheezburger (Sep 25, 2010)

JF-AMD said:


> OK, let me see if I have all of the facts straight.
> 
> You believe that L1 is the make or break feature in an architecture?
> You believe the L1 is outside of the core, yet it is inside the core?
> ...



i don't use romur as fact but clearly that 16kb l1 data  under current design is just too small for today standard. also i did not criticize anything from amd's product line. it just a bit personal complain on amd's current market strategy which only focus on mainstream line. but you know something? amd needs a top end killer cpu/gpu to crush its opponent. since you work in amd you should realize amd had been underdog for 4 straight years and you already know the reason why....

also the l1 instruction cache is 32kb if consider 2 core share it.....


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## bear jesus (Sep 26, 2010)

cheezburger said:


> i don't use romur as fact but clearly that 16kb l1 data  under current design is just too small for today standard. also i did not criticize anything from amd's product line. it just a bit personal complain on amd's current market strategy which only focus on mainstream line. but you know something? amd needs a top end killer cpu/gpu to crush its opponent. since you work in amd you should realize amd had been underdog for 4 straight years and you already know the reason why....



I have to ask, you were so convinced that the new top end amd gpu would have a 512bit memory bus and would be a $600 card yet you call it mainstream, can you point me to some other mainstream cards with a 512bit bus or that costed $600?

I am pretty sure that a lot of your comments are leading people to believe that you are just trolling amd/ati threads.

Really with both bulldozer and the amd 6xxx card's no will know anything too specfic untill closer to the launch date of each.


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## JF-AMD (Sep 26, 2010)

Since 2 cores are sharing the same instructions much of the time, it can actually be 64K, right?  Instruction caches are far less random than data caches.


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## enaher (Sep 26, 2010)

Loving the more is better part of your blog, gives that famous quote real men use real cores, a whole new life, great blog JF.


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## cheezburger (Sep 26, 2010)

bear jesus said:


> I have to ask, you were so convinced that the new top end amd gpu would have a 512bit memory bus and would be a $600 card yet you call it mainstream, can you point me to some other mainstream cards with a 512bit bus or that costed $600?
> 
> I am pretty sure that a lot of your comments are leading people to believe that you are just trolling amd/ati threads.
> 
> Really with both bulldozer and the amd 6xxx card's no will know anything too specfic untill closer to the launch date of each.



do you believe there source from wiki? second there's still many people rather believe cayman will be a 256bit bus with ridiculously  high frequency GDDR5 and 32rops with also ridiculous number of old style 5D shader...also there are many romur as well. first i did believe cayman is going to be a top end card with 512bit bus and 64rops..along with mighty bulldozer....but after seen specification of orochi i starting doubt amd did not change their mainstream strategy at all...which is what i afraid. bulldozer's small core just reminding me of 5D shader on old r600....small core just make bulldozer don't look that mighty anymore...

also are you sure that i only up on amd/ati thread? go see on fermi thread...i made a lot of criticism about fermi/kapler over there and i believe you should take a look.... and stop calling me troll unless you can prove me wrong but then again that is personal offense.


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## bear jesus (Sep 26, 2010)

cheezburger said:


> do you believe there source from wiki? second there's still many people rather believe cayman will be a 256bit bus with ridiculously  high frequency GDDR5 and 32rops with also ridiculous number of old style 5D shader...also there are many romur as well. first i did believe cayman is going to be a top end card with 512bit bus and 64rops..along with mighty bulldozer....but after seen specification of orochi i starting doubt amd did not change their mainstream strategy at all...which is what i afraid. bulldozer's small core just reminding me of 5D shader on old r600....small core just make bulldozer don't look that mighty anymore...
> 
> also are you sure that i only up on amd/ati thread? go see on fermi thread...i made a lot of criticism about fermi over there and i believe you should take a look.... and stop calling me troll unless you can prove me wrong but then again that is personal offense.



Honestly i don't believe any unofficial source i was just coommenting on your posts, i have not given fermi threads much attetion as i'm waiting to choose what card i will want and have read enough on the fermi reviews to know what i need for now.

I am sorry if it seamed like i was calling you a troll, i was not and that was not my intention.


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## LAN_deRf_HA (Sep 26, 2010)

Am I right in thinking bulldozer was designed with more server than consumer considerations? I'm concerned this will be like fermi. Not the most efficient chip for the average consumer because it includes things aimed at the business sector, all in one blanket package.


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## erocker (Sep 26, 2010)

LAN_deRf_HA said:


> Am I right in thinking bulldozer was designed with more server than consumer considerations? I'm concerned this will be like fermi. Not the most efficient chip for the average consumer because it includes things aimed at the business sector, all in one blanket package.



Through reading this thread and getting whatever information I can wrap my head around, I don't see the correlation at all. If anything, when it was mentioned, things like power consumption were lower than the competition so I have no idea where you're getting that idea from.


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## Techtu (Sep 26, 2010)

erocker said:


> Through reading this thread and getting whatever information I can wrap my head around, I don't see the correlation at all. If anything, when it was mentioned, things like power consumption were lower than the competition so I have no idea where you're getting that idea from.



Maybe not in this thread but here's a little something from one of btarunr's thread's...




btarunr said:


> Market Segments
> As mentioned in the graphic before, AMD's modular design allows it to create different products by simply controlling the number of modules on the die (by whichever method). With this, AMD will have processors ready with most PC and server market segments, all the way from desktop PCs, enthusiast-grade PCs, notebooks, to servers. AMD expects to have a full-fledged lineup in 2011. *The first Bulldozer CPUs will be sold to the server market.*



The whole thread can be found here

Anyway's maybe from hearing something like that has lead to the thought that this is going to be based on servers.


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## erocker (Sep 26, 2010)

Tech2 said:


> Maybe not in this thread but here's a little something from one of btarunr's thread's...
> 
> 
> 
> ...



That's the way it's been for years. Opterons had their "Athlon/Phenom" equivilent as Xeons and Intel Desktop chips are the same. I don't see a change here.


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## Techtu (Sep 26, 2010)

erocker said:


> That's the way it's been for years. Opterons had their "Athlon/Phenom" equivilent as Xeons and Intel Desktop chips are the same. I don't see a change here.



I know this  ... I actually read about it a short while ago whilst trying to find that thread of btarunr's


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## EastCoasthandle (Sep 26, 2010)

JF-AMD
I curious to know if Bulldozer solutions would provide any substantial boost in performance when paired with a 6000 series card over a Intel solution?  I'm not sure if you can comment on such a thing though..


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## bear jesus (Sep 26, 2010)

EastCoasthandle said:


> JF-AMD
> I curious to know if Bulldozer solutions would provide any substantial boost in performance when paired with a 6000 series card over a Intel solution?  I'm not sure if you can comment on such a thing though..



I have to ask, in theory is not not like asking if there would be a boost using a 5000 series card with a phenom over an intel solution. should it not just depend on what cpu is more powerful but then mainly in cpu limited games/situations?


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## crazyeyesreaper (Sep 26, 2010)

well it depends clock speed wise Phenom II is more then adquate for games but with AMDs display drivers after 10.4a performance tanks like a mofo with stock NB so 4ghz cpu 2000nb is slower then 3400 stock cpu 2600nb basically 5k cards on Phenom II with a slow NB performance scaling can be negative aka 2 gpus at 50% = 1 gpu at 99% so that second card basically does nothing on newer drivers on 10.4a tho everything works fine so no one really knows for certain right now


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## HXL492 (Sep 26, 2010)

I hope the bulldozer will come through. The excitement in me is unbearable...


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## Makaveli (Sep 26, 2010)

btarunr said:


> There's nothing particularly bad with AMD's storage performance with a proper mode (AHCI or RAID) and proper driver (AMD over Microsoft) installed. The RAID controller sucked only till SB600 southbridge (which had a Silicon Image logic that wasn't implemented so well). SB700/SB710/SB750 is on par with ICH10/R, SB850 has no match (SATA 6 Gb/s).



I find this interesting.

Where can I see some reviews and or benchmarks of this, because from what i've seen on the web so far ICH10/R has superior performance to any of AMD's southbridges.

That also includes faster USB 2.0 speeds on intel chipsets aswell.


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## bear jesus (Sep 26, 2010)

crazyeyesreaper said:


> well it depends clock speed wise Phenom II is more then adquate for games but with AMDs display drivers after 10.4a performance tanks like a mofo with stock NB so 4ghz cpu 2000nb is slower then 3400 stock cpu 2600nb basically 5k cards on Phenom II with a slow NB performance scaling can be negative aka 2 gpus at 50% = 1 gpu at 99% so that second card basically does nothing on newer drivers on 10.4a tho everything works fine so no one really knows for certain right now



I had no idea about that, i just assumed that it was another screw up by the ati driver team as i geuss i'm used to hearing about people wih crossfire performance problems after upgrading drivers (one of the big reasons i don't want to go back to a dual card setup). i geuss i'm lucky i didnt intend to crossfire on this board as the NB does not seam to like being pushed that far.

I must admit i hope the 6xxx and 7xxx cards go well with bulldozer as i'm hoping all of them meet my needs and budget over the next year or so.


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## Depth (Sep 26, 2010)

ebolamonkey3 said:


> 2011 is shaping up to be quite an interesting year



We say that at the end of every year


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## Hayder_Master (Sep 26, 2010)

first real good news from AMD, make me fell they maybe beat intel this time


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## de.das.dude (Sep 26, 2010)

they always do beat intel for me.


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## pantherx12 (Sep 26, 2010)

Thanks for confirming new socket JF!

Was going to get an am3 set up for x-mas but I'll hold on to my dying intel set up til bulldozer is out.


Feel free to send me AM3+ set up for free for testing and review purposes! XD


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## JF-AMD (Sep 26, 2010)

EastCoasthandle said:


> JF-AMD
> I curious to know if Bulldozer solutions would provide any substantial boost in performance when paired with a 6000 series card over a Intel solution?  I'm not sure if you can comment on such a thing though..



I can't comment on any client info. I work in servers.  I know a lot of the answers but because I am on the forum as an individual and not a company representative, I can't share info on that.

As to whether the bulldozer core was designed as a client or a server core, someone else had it right.  We have leveraged the same core for both products in the past and will continue to do so (Istanbul/Thuban was the only recent departure).

There are client features turned off in servers and vice versa.  

Typically because it is used for both people assume that single threaded performance and clock speed are not going to be good.  I would not worry about either of those.


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## bear jesus (Sep 26, 2010)

JF-AMD said:


> We have leveraged the same core for both products in the past and will continue to do so (Istanbul/Thuban was the only recent departure).
> 
> There are client features turned off in servers and vice versa.
> 
> Typically because it is used for both people assume that single threaded performance and clock speed are not going to be good.  I would not worry about either of those.



Are barcelona and deneb quite close? i thought thuben and istanbul were kind of close but of corse some more differences, i assumed the server and client chips were pretty simmilar to each other excluding socket, the dual channel memory for client and quad channel memory for server, with of corse one major feature (turbo core) not a part of the server chips and as always different clock speeds and tdp.

Although i admit that i really don't know much about the server chips/differences between them and client chips and if there is any difference with the chips designed for say 1U upto 4U, is there anything you could say to give a little insight into the differences?


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## JF-AMD (Sep 26, 2010)

Barcelona was very close to whatever that product was (I don't really know many of their code names).

We used the same die for 1000 through 8000 series.  That is why we consolidated the line down to 4000/6000 and removed the 4P price premium.  Today you can buy a top end AMD 2P or 4P for the same price, $1386, or you could buy the Intel 2P at $1663 and the 4P at ~$3682.  Trust me, their 4P is not 2.5X faster than the 2P.

Plus, by having the same core top to bottom, when you write software and customize it, you aren't dealing with 3 different platforms, only 1.  Even our chipsets are identical, top to bottom. Software people love that, network administrators love that, and if you are doing virtualization it makes things so much easier because you can easily move VMs around.

On the intel side their 4P is old technology and generally lags by a year from 2P.  3 different platforms, 3 different chipsets, lots of inconsistencies.


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## bear jesus (Sep 26, 2010)

JF-AMD said:


> Barcelona was very close to whatever that product was (I don't really know many of their code names).
> 
> We used the same die for 1000 through 8000 series.  That is why we consolidated the line down to 4000/6000 and removed the 4P price premium.  Today you can buy a top end AMD 2P or 4P for the same price, $1386, or you could buy the Intel 2P at $1663 and the 4P at ~$3682.  Trust me, their 4P is not 2.5X faster than the 2P.
> 
> ...



I had no idea that the chipsets were the same, for some reason i thought that may be one of the changed between them, although not sure where i got that idea from.

I'm intending to learn a lot more about the server side as i intend to buy my first real home made server instead of just making client hardware act as a server with missing server features(although i only really know of eec as one of the major things im missing). it is one of the reasons i'm so interested in bulldozer as with interlagos chips i am hoping to build a very powerful server to last me as long as the hardware does. But of corse this wont be any time soon as i am not expecting it to come cheap.


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## wahdangun (Sep 26, 2010)

bear jesus said:


> I had no idea that the chipsets were the same, for some reason i thought that may be one of the changed between them, although not sure where i got that idea from.
> 
> I'm intending to learn a lot more about the server side as i intend to buy my first real home made server instead of just making client hardware act as a server with missing server features(although i only really know of eec as one of the major things im missing). it is one of the reasons i'm so interested in bulldozer as with interlagos chips i am hoping to build a very powerful server to last me as long as the hardware does. But of corse this wont be any time soon as i am not expecting it to come cheap.



hmm aside from ECC ram support i know that server chip have more consistent throughput and can handle intense workload with stable performance where client chip usually focus to burst and not consistent


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## bear jesus (Sep 26, 2010)

wahdangun said:


> hmm aside from ECC ram support i know that server chip have more consistent throughput and can handle intense workload with stable performance where client chip usually focus to burst and not consistent



That sounds a lot more useful as one of the main uses of my "server" pc (now and the planned upgrade) is hosting (mainly steam/source baised) games but also hosting files for remote access/downloading but i admit i would like to try some folding in it's spare time or with enough core's at the same time.


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## wahdangun (Sep 26, 2010)

bear jesus said:


> That sounds a lot more useful as one of the main uses of my "server" pc (now and the planned upgrade) is hosting (mainly steam/source baised) games but also hosting files for remote access/downloading but i admit i would like to try some folding in it's spare time or with enough core's at the same time.



so why don't you just buy magny course CPU ? its have 12 core and quad chanel ram, or even better use 4P system for 48 cores, so you won't run out cpu core lol


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## bear jesus (Sep 26, 2010)

wahdangun said:


> so why don't you just buy magny course CPU ? its have 12 core and quad chanel ram, or even better use 4P system for 48 cores, so you won't run out cpu core lol



Admitdly magny cours would be nice but i want to know if the difference between it and interlagos will be worth it as i would expect higher speed ram, better ipc, more cores, better power saving and hopefully other features

I expect it to be more expensive (even more so with fast high density ecc ddr3) but then of corse it will all be down to if the extra cost is worth the extra features and speed and to be honest i am hoping it will be, plus i am in no hurry to spend several thousand £ on a server that wont be fully used for near a year


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## demonkevy666 (Sep 26, 2010)

JF-AMD said:


> Since 2 cores are sharing the same instructions much of the time, it can actually be 64K, right?  Instruction caches are far less random than data caches.



Hint hint......


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## WarEagleAU (Sep 28, 2010)

sounds like some good news happening. I cant wait to see some reviews. Im not really hyped if it destroys anything intel has I am just hoping it puts it on more of an even par.


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## bear jesus (Sep 28, 2010)

WarEagleAU said:


> sounds like some good news happening. I cant wait to see some reviews. Im not really hyped if it destroys anything intel has I am just hoping it puts it on more of an even par.



All i ever hope from amd is acceptable performance at a good price as for me the gpu is most importaint even more so as i try to avoid dual cards, although i am really looking forward to how the server parts perform and hope they do really well against intel.


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