Monday, January 15th 2007
PCI Express 2.0 ready for use
BEAVERTON, Ore. - January 15, 2007 - PCI-SIG , the Special Interest Group responsible for PCI Express industry-standard I/O technology, today announced the availability of the PCI Express Base 2.0 specification. After a 60-day review of revision 0.9 of the specification in Fall 2006, members of the PCI-SIG finalized and released PCI Express (PCIe) 2.0, which doubles the interconnect bit rate from 2.5GT/s to 5GT/s to support high-bandwidth applications.
The specification seamlessly extends the data rate to 5GT/s in a manner compatible with all existing PCIe 1.1 products currently supporting 2.5GT/s signaling. The key benefit of PCIe 2.0 is its faster signaling, effectively increasing the aggregate bandwidth of a 16-lane link to approximately 16 GB/s. The higher bandwidth will allow product designers to implement narrower interconnect links to achieve high performance while reducing cost.
"In today's world, applications are becoming more advanced and are requiring more bandwidth," said Al Yanes, PCI-SIG chairman and president. "This is the perfect time to release PCIe 2.0, which not only supports high-bandwidth applications such as high-end graphics, but also adds many new architectural enhancements."
In addition to the faster signaling rate, PCI-SIG working groups also added several new protocol layer improvements to the PCIe Base 2.0 specification which will allow developers to design more intelligent devices to optimize platform performance and power consumption while maintaining interoperability, low cost and fast market introduction. These architecture improvements include:
Source:
PCI-SIG
The specification seamlessly extends the data rate to 5GT/s in a manner compatible with all existing PCIe 1.1 products currently supporting 2.5GT/s signaling. The key benefit of PCIe 2.0 is its faster signaling, effectively increasing the aggregate bandwidth of a 16-lane link to approximately 16 GB/s. The higher bandwidth will allow product designers to implement narrower interconnect links to achieve high performance while reducing cost.
"In today's world, applications are becoming more advanced and are requiring more bandwidth," said Al Yanes, PCI-SIG chairman and president. "This is the perfect time to release PCIe 2.0, which not only supports high-bandwidth applications such as high-end graphics, but also adds many new architectural enhancements."
In addition to the faster signaling rate, PCI-SIG working groups also added several new protocol layer improvements to the PCIe Base 2.0 specification which will allow developers to design more intelligent devices to optimize platform performance and power consumption while maintaining interoperability, low cost and fast market introduction. These architecture improvements include:
- Dynamic link speed management allows developers to control the speed at which the link is operating
- Link bandwidth notification alerts platform software (operating system, device drivers, etc) of changes in link speed and width
- Capability structure expansion increases control registers to better manage devices, slots and the interconnect
- Access control services allows for optional controls to manage peer-to-peer transactions
- Completion timeout control allows developers to define a required disable mechanism for transaction timeouts
- Function-level reset provides an optional mechanism to reset functions within a multi-function device
- Power limit redefinition enables slot power limit values to accommodate devices that consume higher power
27 Comments on PCI Express 2.0 ready for use
EDIT: when 64 lane busses arrive we'll have reached the limit of 64-bit processors, you can only have so many traces on a mobo dedicated to a single application. half of all traces from the proc dedicated to a single expansion slot (i.e. pci-e 32x) seems a little asinine... am i the only one that feels this way?
:toast:
the company that made PCI-E Should have just made the AGP slot length longer... so it could be backwards compatible.
Remember when USB 1.1 went to USB 2.0? Speeds went from transfer rates of 12 MBits/second to transfer speeds of 480 MBits/second.
i.e. bandwidth increased 40x. :toast:
And here we have PCIe 2.0. With a bandwidth increase of just 2x.:roll:
LAME LAME LAME.
If they weren't ready, then they should have waited. IMO the new specification should be at least 5-10x. That means a 1 slot/lane card would now have the capacity of a (current) four slot/lane card. And an X1950 Pro could be fit into a 4 slot/lane socket. That makes for low profile etc.
2x is just a waste of time. :banghead:
Its rather stupid that they didn't improve AGP's capability IMO, or make the PCI-E slots backwards compatible.
Also PCIe 2.0 will be backwards compatible to 1.0, so what?
It is always better when the bus is way faster than the device using it. My car can go at 160km/h yet I hardly ever go over 50km/h. I should now cry that the motor is far too strong and go back to steam engines. (I win at faulty comparisions!)
There is no SLI with AGP.
AGP and PCIe 1.0 need aditional power connectors, 2.0 can just draw more from the bus (higher limit at least).
AGP is just for graphics cards, PCIe is used for almost anything now.
If PCIe 2.0 is more efficient and can use less power, I am all for it.
Why are you against improvements? Why not go a step further when you can?
"the industry attempts to avoid the limiting factor for the speed at which data are transferred"