Monday, September 30th 2019
Intel Sunny Cove Successor Significantly Bigger: Jim Keller
Sunny Cove is codename for Intel's first truly new performance CPU core design since "Skylake," and made its debut with the company's 10 nm "Ice Lake" processors, packing the first tangible IPC increase in years. VLSI guru Jim Keller is leading the effort to build Intel's future CPU core designs, and dropped a big hint on what to expect, speaking at a gathering in U.C. Berkeley. It's unclear which specific core Keller is referring to. The immediate successor to "Sunny Cove" is codenamed "Willow Cove," and Intel's own public sketch hints at an incremental upgrade over Sunny Cove, with faster caches and process-level optimization. It's only with "Golden Cove," slated for 2021, that Intel speaks of its next round of IPC increases (dubbed "ST perf"). It's plausible that Keller is referring to this core since a 2021 launch would fit better with a 2018-19 design phase.
In his talk, Keller describes Intel's next big CPU core as being "significantly bigger" than "Sunny Cove," with its 800-wide instruction window, and "massive" data- and branch-predictors, to put Intel back on a linear performance growth trajectory between generations. Keller also commented on this being a "mindset change" at Intel, which over the past decade, only delivered minor IPC increments between generations, and focused on other areas, such as efficiency. In stark contrast, through the 1990s and 2000s, Intel delivered IPC leaps between generations, such as the one between "Netburst" and "Conroe," and onwards to "Nehalem." These were in-part helped by rapid process advancements that slowed in the 2010s as Intel approached the sub-10 nm scale.
The video presentation by U.C. Berkeley follows.
In his talk, Keller describes Intel's next big CPU core as being "significantly bigger" than "Sunny Cove," with its 800-wide instruction window, and "massive" data- and branch-predictors, to put Intel back on a linear performance growth trajectory between generations. Keller also commented on this being a "mindset change" at Intel, which over the past decade, only delivered minor IPC increments between generations, and focused on other areas, such as efficiency. In stark contrast, through the 1990s and 2000s, Intel delivered IPC leaps between generations, such as the one between "Netburst" and "Conroe," and onwards to "Nehalem." These were in-part helped by rapid process advancements that slowed in the 2010s as Intel approached the sub-10 nm scale.
59 Comments on Intel Sunny Cove Successor Significantly Bigger: Jim Keller
So , in another parallel universe, I am safekeeping my 2 entry-level Skylake cpu's one being a Pentium spec whilst the other is a Celeron spec , having them donated to museums all the while story talking my children/grandchildren on how the x86 cpu's "war's" were "fought" and reminiscent of the era's when Intel was top dog in most of those , until "Ivy-Lake" .
"Good night and faa iuu"
All I hear is inadequacy like a truck jacked up 2ft.
This is so far away that newborns will be running around asking where it's at lol
We can speculate why they have not backported for example Sunny Cove to 14nm but there are good technical reasons why this would not be viable. It is bigger which also means hotter. Backporting will take a year or year and a half which Intel architecture engineers thought was reasonable timeframe to get 10nm running. That did not pan out.
Honestly, it all makes sense. Intel can't move to 10 nm because the architecture...which dates back to Nehalem...isn't meant for it. Intel needed to think outside of the box with a new architecture that can transition to 10 nm and beyond. That's what Keller does: new architectures optimized for new nodes.I think he gave this talk at U.C. Berkley to excite the next generation of electrical engineers. There's a whole lot of doom and gloom out there about advancing nodes and Keller is really the only one publicly challenging it.
Edit: I wouldn't be surprised if what Jim Keller has been working on is forked from *Cove products (as in parallel to or after Golden Cove). Keller does the architectural work then leaves. It's handed over to production at that point which can take a long time to improve and test. To hire Keller and then limit him to only modifying your existing cores--it's a waste of effort. Whatever he's working on is going to be like the jump to Conroe or Nehalem.
Remember that Nehalem is almost 11 years old now and was originally designed for 45 nm process. They've been iterating on the same fundamental architecture for far too long. Tick-tock...you eventually got to ring the chime ushering in a new tick-tock.
Keller's main area of expertise is architecture, not manufacturing. While he probably has enough power to impact manufacturing that is a whole different area.
Intel will make a comeback for sure but people think AMD will stay still and are unable to fight back in 2021.
Zen 3 is already rumored to start that. If true, then you can expect a doubling down on that.
And Intel will still have dick for manufacturing.
It's a bad trade-off that only gets worse the more you do it, ILP is bound to hit a hard limit and no matter how much you dedicate logic to extract it you will reach a point where it simply wont give any advantage whatsoever. Moore's law is dying and these nuclear options that Keller is putting forward are proof of it.No, that's exactly the point. They are manufactured in different fabs precisely because they have been designed with that specific fabrication process in mind.
GCN resulted in a power hungry monster at 14nm (and 28nm) as well :)
The complete lack of binning really exacerbated it.
On desktop? If manufacturer is willing to do multiple dies, monolithic should have the potential to be better. Die sizes were reasonable for 8 cores on 12/14/16nm - Zen/Zen+ at ~200mm^2 and 9900K at ~175mm^2. From 12nm to 7nm there is 40-60% area reduction. Chiplets may come into play for other reasons though - some reports on Intel 10nm failures had things to say about IO and AMD has stated IO does not scale down well any more.
It will be interesting to see what AMD will do in terms of APUs next time around. Raven Ridge and Picasso are both monolithic.
For the next gen APU I'd like to see a chiplet with combo IO+GPU die. It would make sense since the IMC is on the IO die already.
Zen is 44mm^2 per CCX (60 mm^2 when L3 is doubled), and ZEN2 is 38 mm^2 L3 included, so we have 38/60 or 36% reduction.
this is Not 7nm, more like 10nm shrink.
jeez, whatasnoozefest........
With Intel’s resources and R&D talent, their come back at complete technology superiority is not a question of if, but when. I hope AMD has planned out their Zen well as it sure will have a tough battle with Intel’s from the ground up design