Sunday, December 8th 2019
AMD "Zen 4" 2021 Launch On Track as TSMC Optimistic About 5 nm
AMD's "Zen 4" CPU microarchitecture is on track for a 2021 launch as its principal foundry partner, TSMC, is optimistic about early yields of its 5 nm silicon fabrication node. TSMC supports the 5 nm product roadmaps of not just AMD, but also Apple and HiSilicon. "Zen 4" is particularly important for AMD, as it will release its next enterprise platform, codenamed "Genoa," along with the new SP5 socket. The new socket will present AMD with the opportunity to significantly change the processor's I/O, such as support for a new memory standard, a new PCIe generation, more memory channels, more PCIe lanes, etc. As early as 2019, the foundry is seeing yields of over 50 percent for the 5 nm node (possibly risk production designed to test the node), which is very encouraging for its customers.
AMD's roadmap for 2020 sees the introduction of "Zen 3" on the 7 nm EUV process (dubbed 7 nm+). AMD recently commented that the performance uplift of "Zen 3" versus "Zen 2" will be "right in line with what you would expect from an entirely new architecture." The 7 nm EUV node provides a significant 20 percent increase in transistor-density compared to the current 7 nm DUV node "Zen 2" chiplets and the company's "Navi" family of GPUs are built on. "Zen 3" could see the company do away with the CCX (quad-core CPU complex), and make chiplets monolithic blocks of CPU cores without sub-divisions. For the client-segment, 5 is a recurring number in 2021. It will see the introduction of the 5th generation Ryzen processors (5000-series), built on the 5 nm process, supporting DDR5 memory, PCI-Express gen 5, and the new AM5 client-segment CPU socket.
Sources:
China Times, WCCFTech, MyDrivers
AMD's roadmap for 2020 sees the introduction of "Zen 3" on the 7 nm EUV process (dubbed 7 nm+). AMD recently commented that the performance uplift of "Zen 3" versus "Zen 2" will be "right in line with what you would expect from an entirely new architecture." The 7 nm EUV node provides a significant 20 percent increase in transistor-density compared to the current 7 nm DUV node "Zen 2" chiplets and the company's "Navi" family of GPUs are built on. "Zen 3" could see the company do away with the CCX (quad-core CPU complex), and make chiplets monolithic blocks of CPU cores without sub-divisions. For the client-segment, 5 is a recurring number in 2021. It will see the introduction of the 5th generation Ryzen processors (5000-series), built on the 5 nm process, supporting DDR5 memory, PCI-Express gen 5, and the new AM5 client-segment CPU socket.
44 Comments on AMD "Zen 4" 2021 Launch On Track as TSMC Optimistic About 5 nm
It'll be interesting to see how the prices and the yields will be if it's based on monolithic design.
("5"nm is just 7nm EUV++) The big jump here is EUV, not the number, this is why you see all these happy reports about new shrinks incoming.
Kudos to ASML ;) Dutch engineering ftw
But I'm more interested in architectural improvements than nodes, as Zen4 will be facing Sapphire Rapids(Golden Cove). Also keep in mind that whenever we see claims that a node offers "up to xx % denser" and "up to xx % less power draw", it always refers to a best-case scenario for a small chip.
Also, RIP AM4; It has had a good run!
asus sabretooth is driving me nuts with its pch fan running at 4500 rpm :kookoo:
EDIT:
My current main should be enough for some time but I definitely will be looking at some low power chips from zen 3/4 to upgrade crunchers though
Now with ZEN2 every CCD chiplet contains 2x CCXs, containing 4 cores each = 8cores per CCD chiplet. The 2x 4core complexes (CCXs) even though are contained within the same CCD chiplet, are separate to each other with a separate L3 cache (16MB each) and cannot communicate directly but only with InfinityFabric through the I/O die. This results high cross talk latency between cores of the 2 different CCXs within the CCD chiplet.
What is strongly rumoured is that at ZEN3 the 2x 4core complexes will become 1 unified CCX of 8cores with shared L3 cache of 32MB assuming that AMD will not increase the cache further. So, then the 1 CCX will equal the entire CCD and will mean the same thing.
AMD will continue using the chiplet design as this benefit the yields/costs/profits per wafer and provides the capability of scalable CPUs in terms of core counts without changing anything. Separate 8core CCX/CCD chiplets and I/O die chiplet which will also be revised in several ways down the road from gen to gen.
It just got started...
An uplift of around 10% performance gains I consider it legit for a year to year improvement.
ZEN 3 Based on Completely New Architecture
One thing to keep in mind though is Intel is in a struggling and vulnerable position and will be for the foreseeable future. I can see AMD taking full advantage of this situation lol