Wednesday, May 13th 2020
OPNs for At Least Twelve Desktop AMD "Renoir" APUs Decoded
Igor's Lab discovered that AMD may be working on as many as twelve desktop Ryzen G "Renoir" processors with integrated graphics. These include six SKUs each covering the 65 W and 35 W TDP categories, and include two each of 8-core/16-thread, 6-core/12-thread, and 4-core/8-thread SKUs per TDP category. All twelve chips feature increased power limits from their mobile siblings, and a reference memory frequency of DDR4-3200. The parts also feature iGPU maximum engine clock boost frequency as high as 2.10 GHz, to overcome the compute unit deficit "Renoir" has against its predecessor, "Picasso/Raven Ridge," with their up to 11 CUs.
The series appears to be led by an 8-core/16-thread SKU with CPU boost frequency as high as 4.45 GHz, iGPU engine clock as high as 2.10 GHz, and various power-state clock speeds detailed in the table below. The 6-core/12-thread part boosts up to 4.30 GHz, with iGPU engine clock up to 1.90 GHz. The 4-core/8-thread part boosts up to 4.10 GHz, with up to 1.70 GHz iGPU engine clocks. The 35 W TDP parts have, on average, 200-300 MHz lower max CPU core boost- and nominal clock speeds, but more aggressive power-management as defined in the various P-states. Half of these OPNs point to chips with identical clock speeds and core configurations. These are probably differentiated from each other with some of them being Ryzen PRO SKUs.
It stands to reason that all SKUs will be launched under the upcoming Ryzen 4000G-series branding. We already know that the 8-core parts will get a Ryzen 7 brand extension from the Ryzen 7 4700G leak. It's possible that the Ryzen 5 parts will be 6-core/12-thread, and Ryzen 3 4-core/8-thread. For the Ryzen 5 desktop APU series in particular, this would amount to a 50% increase in core- and thread-counts (from the 3400G), while it would see the introduction of SMT for Ryzen 3 desktop APU series (from the 3200G). Find some technical commentary in the Igor's Lab report at the source link below.
Source:
Igor's Lab
The series appears to be led by an 8-core/16-thread SKU with CPU boost frequency as high as 4.45 GHz, iGPU engine clock as high as 2.10 GHz, and various power-state clock speeds detailed in the table below. The 6-core/12-thread part boosts up to 4.30 GHz, with iGPU engine clock up to 1.90 GHz. The 4-core/8-thread part boosts up to 4.10 GHz, with up to 1.70 GHz iGPU engine clocks. The 35 W TDP parts have, on average, 200-300 MHz lower max CPU core boost- and nominal clock speeds, but more aggressive power-management as defined in the various P-states. Half of these OPNs point to chips with identical clock speeds and core configurations. These are probably differentiated from each other with some of them being Ryzen PRO SKUs.
32 Comments on OPNs for At Least Twelve Desktop AMD "Renoir" APUs Decoded
AMD could take it easy with the increase of cores (4200G 6C/6T and 4400G 6C/12T) and put another 1~2CU or at least keep the 11CU of the previous generation.
This is not the same graphics as in Picasso (3000G/H/U).
Also, lowering the CPU core count is a very stupid idea. Gaming laptops are a MUCH larger market than laptops with fastest iGP ever. AMD needs 8 cores to be able to compete with Intel.
Mobile 3000 series = Zen+
Mobile 4000 = Zen 2
This is really missleading.
Many people bought mobile 3000 series because they thought it was like 3000 desktop series / Zen 2.
AMD only does this to trick people. It's obvious.
It's a 50% increase (from 1400MHz to 2100MHz) for desktop Renoir. So even bigger gains? New Vega 8 = old Vega 14 (a decent improvement on Picasso's Vega 11).
The problem is memory bandwidth causing the shader cores to idle. What normally needs to happen for full texturing is 8x bandwidth. Z culling reduces that to 4x. However it still is an inordinate amount of memory for a simple pixel operation, so better pixels or better rasterization saving on concurrent writes is pretty important.
RDNA on the other hand is for directx 12 and extending scalarization support to two cycle operations. I wonder if Nvidia has the same extension since warp arrays can be rearranged which is what scalarization is about in the end. It is about not wasting registers for vector operations and having all for a single atomic operation, so the effort is towards running maximum instances of a single shader.
Tegra again, is not a high power chip in my eyes. You only need to go into multicycle register scheduling if you have such lots of shaders that it becomes a losing game to schedule vectors, losing latency to perform the amount of work. Just because you can, doesn't validate you should. Small gpus on the other hand cannot shuffle between so much work simultaneously anyway. Everything is serial by nature, rather than schedule.