Thursday, May 27th 2021
AMD's 2022 Ryzen "Raphael" Zen 4 Processor Packs 20% IPC Gain
AMD's second processor microarchitecture on the Socket AM5 platform, the Ryzen 7000 "Raphael," could introduce a 20% IPC gain over its predecessor, according to a report by Moore's Law is Dead. The processor debuts the company's "Zen 4" microarchitecture, which clocks IPC gains over the rumored "Zen 3+" microarchitecture that the Ryzen 6000 "Rembrandt" processor debuts with, on Socket AM5. The upper limit of AMD's core-counts appear to remain at 16-core for the flagship part. With "Zen 4" CCDs (8-core chiplets) being built on 5 nm, the source predicts a 50% performance/Watt gain. The chips could also introduce AVX-512 support. The Ryzen "Raphael" processor is due for 2022.
Sources:
Moore's Law is Dead (YouTube), Wccftech
27 Comments on AMD's 2022 Ryzen "Raphael" Zen 4 Processor Packs 20% IPC Gain
No SMT4 this time?:laugh:
Anyone that follow the news/rumors and actual leakers on twitter, can come up with that list.
This guys is a BS artist.
Idk, I dont want his channel, watched some videos but they are boring af and he claims he does not want ot be a "leak" channel but he knows that that is where the money lies so thats what he does.
How many decades have we been on this puny, minischule "5-10-15-20% gains" carnival ride anyways ????
Reminds me of Intsmel's never-ending 14nm ++++++++++++++++++++++++++++ routine :cry:
also im still on the 2600k so by the time ill upgrade (fingers crossed Alderlake is worth a damn otherwise Zen 3/4 it is) the 20%'s over time will have added up to a nice jump.
Kudos to him for finding this gold mine, tho'.
Also disappointing is DDR5 performance, the numbers released so far look awful, with DDR4 being the better option for at least another 2 years. It would have been good to see AMD drop one last AM4 CPU refresh, with a nice 10% IPC uplift.
But the real question will be if AMD has the ability or balls to up the core count on AM5.
The hardest tape out is the one just leap frogging the previous. These chips used to cost a lot. Now, AMD can keep the interconnects the same and just upgrade execution units year after year. You do that with a monolithic die and you have just blown your investment payoff projections with huge tapeout costs.
DDR5 brings the bandwidth, so it'll be good for bandwidth-limited use cases (iGPU gaming is getting one hell of a boost at least), but beyond that consumer use cases are more latency bound. And DDR5 is designed primarily for servers, which are mostly bandwidt-bound, hence it staying at the same or even increasing latencies in order to increase bandwidth. DDR4 and DDR5 is likely to perform equivalently for most non-datacenter uses for quite some time. DDR5 might not ever be tangibly faster in terms of latency - but then DDR RAM latencies haven't budged much at all since DDR(1).
as competitive pressure.
(Largely corrupt) OEM ties is the only reason Intel is not feeling major pain from it, notebook/server market in particular.
DDR5 is a bust, at least for now, and certainly does not "bring the bandwidth", at least according to a press release on this site a couple of weeks ago. DDR4 has higher bandwidth, and MUCH better latency right now, and probably for the next couple of years, until DDR5 ramps up its speed and lower it's timings. - Just like every single memory standard we have ever had on the PC - The new standard is slower, has crappy timings, and is expensive... We have seen this many times before.
I think a 20% IPC gain, but a loss of memory bandwidth and higher memory latency, is not exactly stunning this time round - especially if we keep the thought of Intel not sitting on it's ass much longer taken in to account.
at least MLiD talk about the actual stuff so. But like usual, rumors tend to become more real when multiple reliable source start to talk about it. DDR5 is bringing more bandwidth. DDR5-6400 is double the bandwidth of DDR4-3200. The actual real life latency (And not the memory timming) is in the same ballpark as all previous generation of DDR memory (about 14ns), The memory have new function that are game changer like same bank refresh (Only a bank is refreshed and the rest of memory can continue to be accessed unlike right now when the memory ops pause while the memory is being refresh). Also Onboard voltage controller, on die ECC, dual channel per dimm. etc.
And, same thing as all previous generation. JEDEC SPEC ram will suck versus previous DOCP/XMP 'retail memory'. There will be the same XMP/DOCP retail memory kit around that have better timing than JEDEC.
The only thing there is at first it is going to be cost prohibitive versus DDR4. But DDR5 is better and will perform better than DDR4 in same scenario (JEDEC VS JEDEC or XMP high end kit vs XMP high end kit)
Delayed 2 years ;)
The few times they are right, then pretty much anyone could have reached the same conclusion.
People need to use their common sense and see through this. Pretty much all these leakers claim to have numerous "sources" inside Intel, AMD and Nvidia. But think about that for a moment; a real source with access to useful information under NDA would risk losing their job and could be facing a large lawsuit for leaking this, and they are supposedly doing so regularly to nobodies on YouTube with nothing in return?
In reality though, they are pulling all of these "leaks" out of their tuchus. Yeah, his "IPC" estimates are all over the place, even for Alder Lake he has been posting claims at ~10-30% at various times, claiming it to be accurate at the time. But in reality though, real IPC is determined by architecture, and is actually known fairly precisely at the design stage, it's one of those metrics that will not change (unless they have to disable features etc.).
His claims in this video about Zen 4 not being design complete, and "things" can change clearly displays he is clueless about how microarchitectures are developed. The features of an architecture is decided before the design is begun, no major feature can be added far into the design process. Things like AVX-512, SMT4 etc. are fundamental design features that affects the entire design of the pipeline. In the past, he has claimed Zen 3 exists in SMT2 and SMT4 variants, if this were true, then these would have been developed as separate designs from the start, yet we've seen no evidence of its existence.
So remember this; real sources who actually work on these projects would know these details, and they are not subject to change. Last minute design changes are just excuses used by "leakers", when in reality the features of Zen 4 were decided years ago.
But this guy usually takes the cake whenever he claims to know much more, but don't want to tell us yet for some reason.
Anyone can do this; claim to know next week's lottery numbers, but only reveal them after the fact… No one should complain if we can get ~20% real IPC gains ever two years for a while.
That will be great, and result in noticable improvements in responsiveness etc.
And remember, you don't have to buy every generation ;) "Refresh"?
IPC gains come from architectural improvements, so unless some feature have been disabled/tuned down due to a bug, you will not see any IPC gains from a "refresh". I actually think it would be a bad move for AMD to do this, in the long term;
The majority of desktops CPUs are sold to system integrators, and most of their customers look at specs like clock speed and core count (and is blissfully unaware that those high-core 65W CPUs will throttle like crazy), so good "specs" on paper sells. This is why Intel (and probably AMD) is moving to hybrid CPU designs for the desktop, even though it makes little practical sense. It's hard to "go back" and sell a faster 6 core once your customers already bought a 16 core of the previous generation. There are a lot of great CPU improvements coming in the next 5+ years, but they will require a lot of die size, so building >16 core low TDP CPUs with just high-performance cores is unrealistic for the foreseeable future.
Shyster