Friday, August 6th 2021

AMD "Zen 3" 3D Vertical Cache Detailed Some More

Senior Technology Fellow Yuzo Fukuzaki shed light on the elusive new CPU technology AMD unveiled at its Computex 2021 keynote, 3D Vertical Cache (3DV Cache). The company had then detailed it as an additional 64 MB last-level cache stacked on top of a CCD (CPU core complex die), which significantly improves performance, including a claimed 15% average gain in gaming performance, which accounts for a generational performance gain over "Zen 3." The prototype AMD unveiled in its keynote was based on a Socket AM4 processor with "Zen 3" CCDs that have the 3DV Cache components in place. With two such CCDs, a 16-core processor would end up with 192 MB of L3 cache.

Yuzo Fukuzaki's theory sheds light on the most plausible position of 3DV Cache in the processor's cache hierarchy. Apparently, it expands the CCD's L3 cache, and doesn't serve as an "L4" victim cache to the L3. This way, the cache setup remains transparent to the OS, which sees it as a contiguous 96 MB block of L3 cache (per CCD). The 3DV Cache die is an SRAM chip fabricated on the same 7 nm process as the "Zen 3" CCD. It measures 6 mm x 6 mm (36 mm²), and is located above the region of the CCD that typically has the 32 MB L3 SRAM. Fukuzaki estimates that roughly 23,000 TSVs (through-silicon vias), each about 17 µm in size, connect the 3DV Cache die to the main CCD.
Sources: Yuzo Fukuzaki (Linkedin), Retired Engineer (Twitter)
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46 Comments on AMD "Zen 3" 3D Vertical Cache Detailed Some More

#26
Xajel
PunkenjoyThat guy comment was pretty rude, but it's not full 3D but more 2.5D

3D chip is not there yet and not around the corner (if it ever come). Right now it's each die are in 2D. they can stack those and have TSV, but it remain that each layer is 2D. 3D will allow very complex transistor layout. It would help with propagation as you would be able to make denser logic with less space. But I am still not even sure we can make those in labs...


Anyway, that do not mean that this 3D cache isn't impressive. It's actually very impressive and only the beginning of die stacking. The next decade will be very interesting, trust me on that. This is only the beginning.
You're missing a lot bro.

Modern CPU's and GPU's are already 3D, there are many layers in the design. A regular modern CPU (14nm era) is already 13+ layers. The transistors and interconnects are present in multiple layers, like a tiny futuristic city.

3D NAND is a different process, while there are layers, but these are mostly films, and the nature of NAND make it very different than a modern CPU/GPU.

2.5D is when you put different silicon die over a silicon interposer, like how HBM memory is packaged, because HBM memory have very high density interconnect that normal packaging substrate is not enough, modern packaging material is called organic substrate, it is used to connect the actual die to the package pins (with a socketed or non-socketed package like BGA). It's okay for the organic interposer to be used in this case because you have a limited number of traces per mm. With HBM, you need much more traces per mm that organic substrate can't handle it, you need a silicon substrate which is made just like how a normal silicon die is made which will have traces between the GPU/CPU to the HBM memory and traces between them to the organic substrate/interposer below it to connect to the PCB board.
There are two kinds of silicon interposers here, Passive and Active. Passive interposers have no functionality beside connecting the dies and the substrate together. Active interposers can have an actual logic in it, such as basic IO logic, Cache, power management or some other basic functional circuitry.

AMD has used passive interposers 2.5D packaging for a while, and now both NV and Intel are also uses it. Intel announced plans on using Active interposers in future plans (making the interposer with some basic IO functionality), but they don't have any product yet.

3D is similar to 2.5D in the term is that two silicon dies are on top of each other. But the different is that at least the base silicon die is a totally functional die. Here we have just that, the base die is the actual CPU die.

3D die stacking has been in the work for years but the main issues are interconnect and heat which made the tech unusable for high-end designs. TSV has been in use for years (mainly in 3D NAND) and AMD has used it in this proven technology with a twist, TSV is usually done with solder, but AMD used copper instead which helps more with the heat problem. To add another solution, they used a smaller top silicon die that only covers the cache in the base die, cache doesn't produce that much heat to begin with, so the left the actual cores exposed, they only need to put some dummy silicon over the CPU core to make the V height equal and get even pressure and contact on the whole Core die. Silicon is a good heat conductor as well (not as good as copper, but slightly better than aluminium).
Posted on Reply
#27
freeagent
Now I know how Matisse owners felt when Zen 3 was announced.

Posted on Reply
#28
TumbleGeorge
XajelThe transistors and interconnects are present in multiple layers, like a tiny futuristic city.
For interconnectors that is partially true... Show me transistors out of silicone(in layers of other metal or insulator which is part of core (make calculations).
Posted on Reply
#29
tabascosauz
freeagentNow I know how Matisse owners felt when Zen 3 was announced.

At least that's how we felt at first, before we found out that a stable late 2020 3900X was a lot more useful than a cancer-ridden 2020 5900X supported by crappy firmware :laugh: same deal with 2019 2700X vs 2019 3700X. Moral of the story, don't ever trust AMD with your money on launch day (or for the next month at the minimum), because YOU are AMD testing department's unpaid interns

But I mean, it's really just supposed to help gaming performance and niche ST workloads right? So, not expecting any change to productivity or MT performance, and Cezanne will still be the mem OC king
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#30
Aquinus
Resident Wat-man
TumbleGeorgesilicone
I don't know about you, but I prefer the natural thing.
Posted on Reply
#31
TheoneandonlyMrK
TumbleGeorgeFor interconnectors that is partially true... Show me transistors out of silicone(in layers of other metal or insulator which is part of core (make calculations).
Any finfet transistor is already 3d.
Stacked finfet is as 3d as we are getting I'm sure of that.
Gate all around, triple ribbon whatever are more 3D not less, staking those is the goal.
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#32
TumbleGeorge
TheoneandonlyMrKStacked finfet
Where is this in real use? In current Intel Core i ? Or in AMD ZENX? Or in GPUs? I know that companies has plans for future.
But you not answer right to my previous question: Show me transistors out of silicone(in layers of other metal or insulator which is part of core (make calculations)
Posted on Reply
#33
TheoneandonlyMrK
TumbleGeorgeWhere is this in real use? In current Intel Core i ? Or in AMD ZENX? Or in GPUs? I know that companies has plans for future.
But you not answer right to my previous question: Show me transistors out of silicone(in layers of other metal or insulator which is part of core (make calculations)
You can Google that shit online, Intel introduction of fin fet was year's ago 10Nm ?! AMD got an implementation with 7n I believe so Zen 2. AFAIK.

Was I wrong"On May 2, 2011, Intel announced its first 22 nm microprocessor, codenamed Ivy Bridge, using a FinFET technology called 3-D tri-gate. IBM's POWER8 processors are produced in a 22 nm SOI process."
Posted on Reply
#34
jigar2speed
AquinusThe problem isn't cooling capacity, it's heat flux. The more layers you have, the worse heat flux gets because it has to go through more material before hitting a medium that actually can move the heat away from the CPU. The more that we start seeing 2.5D and 3D circuits, the more this will become a problem.
I bet CPU dies within 1 month. AMD don't know how to built a CPU.
Posted on Reply
#35
TumbleGeorge
I think 3D mean connected(wired) transistors dispersed in insulator not on insulator i.e. without layers, without basement.
Posted on Reply
#36
Haile Selassie
AquinusThe problem isn't cooling capacity, it's heat flux. The more layers you have, the worse heat flux gets because it has to go through more material before hitting a medium that actually can move the heat away from the CPU. The more that we start seeing 2.5D and 3D circuits, the more this will become a problem.
It's exactly what I'm talking about. One can stack multiple L3 layers as the surface area is sufficiently large enough while heat flux in cache area is significantly lower than in the core area.
Thermal conductivity of the die is about 1/4-1/3 of pure copper, depending on the operating temperature (higher at higher Tjmax), so this approach works for a chip of this configuration.
Posted on Reply
#37
TheoneandonlyMrK
TumbleGeorgeI think 3D mean connected(wired) transistors dispersed in insulator not on insulator i.e. without layers, without basement.
Well hopefully they hurry up reverse engineering those UFO's because chips without layer's that disperse transistors vertically, again without layer's?!, Wtaf, are some kind of fantasy.
Wtaf are you on about, have you any idea how chip's are made, if so briefly explain how anything you'd like to see could be made in your version of 3D?!
Posted on Reply
#38
TumbleGeorge
TheoneandonlyMrKWell hopefully they hurry up reverse engineering those UFO's because chips without layer's that disperse transistors vertically, again without layer's?!, Wtaf, are some kind of fantasy.
Wtaf are you on about, have you any idea how chip's are made, if so briefly explain how anything you'd like to see could be made in your version of 3D?!
My version of explain is what is 3D, not what is marketing "3"D
Posted on Reply
#39
TheoneandonlyMrK
TumbleGeorgeMy version of explain is what is 3D, not what is marketing "3"D
No your version is dreamy bullshit that totally ignores how chip's have been made since day one, in layer's so how then do we build ANY chip in any way without using layer's.

Is hyperbolic without the slightest thought of how in the world anyone makes it, do we genetically engineer a ferit that shits out 3D chips?! Without layer's.

I mean your idea of 3d means f all to anyone with a sensible logical mind who has any idea how chip's are made.

But yeah these then are not 3D because they don't meet your FD up clueless definition of 3D.

Please inform Intel and AMD of your refutation of their work, but don't expect a reply from them , I doubt they reply to letters from your type.

Kin Rita.
Posted on Reply
#40
Punkenjoy
Layers are mostly used for electrical path between transistors but transistors are mostly on the same layer. They are all also all on the same 2 dimension. That mean the input/output orientation of each transistors is always on the same plane. Layer are not news and if would have been what Intel and AMD even closely think that it's 3D transistor, they would have marketed that all over the place (like now what they are doing with 3D Cache)

HBM is considered 2.5D since they stack die, so technically, this chip should be called Zen 3 2.5D cache. NAND-3D is considered 3d because they don't stack die but layers of cells (not just wiring like CPU).

But 2.5D cache is ugly and who cares really except few nerds on TPU forums lol. And i also really think AMD and Intel Engineer really do not care about what people say on tech forums

A full 3D die, (not layer stacked) would have transistors with input/output in all orientation possible. You wouldn't have TSV between chips or layers, but actual path going up and down. You could have a transistor where the input is horizontal and the output is vertical if that is what make sense.
Posted on Reply
#41
TheoneandonlyMrK
PunkenjoyLayers are mostly used for electrical path between transistors but transistors are mostly on the same layer. They are all also all on the same 2 dimension. That mean the input/output orientation of each transistors is always on the same plane. Layer are not news and if would have been what Intel and AMD even closely think that it's 3D transistor, they would have marketed that all over the place (like now what they are doing with 3D Cache)

HBM is considered 2.5D since they stack die, so technically, this chip should be called Zen 3 2.5D cache. NAND-3D is considered 3d because they don't stack die but layers of cells (not just wiring like CPU).

But 2.5D cache is ugly and who cares really except few nerds on TPU forums lol. And i also really think AMD and Intel Engineer really do not care about what people say on tech forums

A full 3D die, (not layer stacked) would have transistors with input/output in all orientation possible. You wouldn't have TSV between chips or layers, but actual path going up and down. You could have a transistor where the input is horizontal and the output is vertical if that is what make sense.
Intel have used 3 dimensions to create fin fet, built using LAYErS, with the 3rd dimension being either etched away or vapour deposition to create 3D structures.

Any hypothetical 3D built chip WILL be built with layer's, and any argument against what they do now being 3D is both uninformed and missled , but feel free to join George in showing the world what real 3D chip's are and please divulge how you think you would make one.

Because until you back your opinionated BS with some portion of fact I'll rely on the published fact that Intel and AMD already made 3D structures and stacking said structures is the way we can make 3D integrated chip's.

I suggest Intel crack on with the ferit hybrid too because they'll need too, to make this fantasy 3D chip your imagination has incarnated which doesn't use layer's or tsvs.
Posted on Reply
#42
Punkenjoy
TheoneandonlyMrKIntel have used 3 dimensions to create fin fet, built using LAYErS, with the 3rd dimension being either etched away or vapour deposition to create 3D structures.

Any hypothetical 3D built chip WILL be built with layer's, and any argument against what they do now being 3D is both uninformed and missled , but feel free to join George in showing the world what real 3D chip's are and please divulge how you think you would make one.

Because until you back your opinionated BS with some portion of fact I'll rely on the published fact that Intel and AMD already made 3D structures and stacking said structures is the way we can make 3D integrated chip's.

I suggest Intel crack on with the ferit hybrid too because they'll need too, to make this fantasy 3D chip your imagination has incarnated which doesn't use layer's or tsvs.
Even if they use multiple layer to build these fin fet transistors, those are still 2d transistors on a 2d plane.
Posted on Reply
#43
TheoneandonlyMrK
PunkenjoyEven if they use multiple layer to build these fin fet transistors, those are still 2d transistors on a 2d plane.
Not what physics, the manufacturer or common sense says just George and you.
Crack on and explain how they're going to make 3D chip's in the future without layer's, I'm intrigued.
Posted on Reply
#44
Aquinus
Resident Wat-man
TheoneandonlyMrKNot what physics, the manufacturer or common sense says just George and you.
Crack on and explain how they're going to make 3D chip's in the future without layer's, I'm intrigued.
Just because an IC has layers doesn't mean all layers have the same "stuff". I'm pretty sure that @Punkenjoy is right about this for most cases. Clearly this depends on the implementation, but it's far more complicated to stack transistors than wires. Other kinds of 3D circuits are easier to produce because it's the same pattern over and over and over again. It's far more complicated with CPUs, particularly if you're trying to keep things like clock slew in check. Forget the issues with heat flux.
Posted on Reply
#45
Steevo
PunkenjoyEven if they use multiple layer to build these fin fet transistors, those are still 2d transistors on a 2d plane.
What dimension do they not measurably exist in? At the scales they are built on they are more 3D than you probably think.
Posted on Reply
#46
TheoneandonlyMrK
AquinusJust because an IC has layers doesn't mean all layers have the same "stuff". I'm pretty sure that @Punkenjoy is right about this for most cases. Clearly this depends on the implementation, but it's far more complicated to stack transistors than wires. Other kinds of 3D circuits are easier to produce because it's the same pattern over and over and over again. It's far more complicated with CPUs, particularly if you're trying to keep things like clock slew in check. Forget the issues with heat flux.
He says they're 2D , they're not.
I didn't say everything is made of the same stuff?!.
Every part of a chip IS built using layering, etching , and adding material via vapour deposition to build features or more layers.
AMD and Intel already make 3D circuits and stack these in different ways (ATM only) and 3D packages ,in the truest way they will in any fashion, for at least 10 years likely more.

Anyone saying they want transistors vertically in the chip,. While also somehow doing away with layering ,I will hold my words, they're harsh.

Believe what you want though yeh.
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