Monday, March 28th 2022
AMD's Upcoming Zen 4 Based Genoa CPUs Confirmed to Have 1 MB L2 Cache per Core
As unreliable as Geekbench can be as a comparative benchmark, it's also an excellent source for upcoming hardware leaks and in this case more details about AMD's upcoming Zen 4 based Genoa server and workstation processors has leaked. Someone with access to a 32-core engineering sample thought it was a good idea to run geekbench on it and upload the results. As the engineering sample CPU is locked at 1.2 GHz, the actual benchmark numbers aren't particularly interesting, but the one interesting titbit we get is that AMD has increased the L2 cache to 1 MB per core, or twice as much as its predecessor.
What seems to be missing from this engineering sample is any kind of 3D V-Cache, as it only has a total of 128 MB L3 cache. Despite the gimped clock speed, the Genoa CPU is close to an EPYC 7513 in the single core tests and that CPU has a 2.6 GHz base clock and a 3.65 GHz boost clock, both system running Ubuntu 20.04 LTS. It manages to beat it in a couple of the sub-tests, such as Navigation, SQLite, HTML5, gaussian blur and face detection and it's within a few points in things like speech recognition and rigid body physics. This is quite impressive considering the Genoa engineering sample is operating at less than half the clock speed, or possibly even at a third of the clock speed of the EPYC 7513. AMD is said to be launching its Zen 4 based Genoa CPUs later this year and models with up to 96 core and 192 threads, with 12-channel DDR5 memory and PCIe 5.0 support are expected.
Sources:
Geekbench, via VideoCardz
What seems to be missing from this engineering sample is any kind of 3D V-Cache, as it only has a total of 128 MB L3 cache. Despite the gimped clock speed, the Genoa CPU is close to an EPYC 7513 in the single core tests and that CPU has a 2.6 GHz base clock and a 3.65 GHz boost clock, both system running Ubuntu 20.04 LTS. It manages to beat it in a couple of the sub-tests, such as Navigation, SQLite, HTML5, gaussian blur and face detection and it's within a few points in things like speech recognition and rigid body physics. This is quite impressive considering the Genoa engineering sample is operating at less than half the clock speed, or possibly even at a third of the clock speed of the EPYC 7513. AMD is said to be launching its Zen 4 based Genoa CPUs later this year and models with up to 96 core and 192 threads, with 12-channel DDR5 memory and PCIe 5.0 support are expected.
30 Comments on AMD's Upcoming Zen 4 Based Genoa CPUs Confirmed to Have 1 MB L2 Cache per Core
Zen 4 will be a huge uplift over Zen 3. This is the biggest architectural change to Zen so far. 25-30% IPC uplifts, 2x L2 caches, higher clocks, possibly 3D cache on many models.
But it's about time the L2 got some love, 512Kb is just not enough. Well done AMD.
Sure those didn't have L3 but still shows that it's possible.
If you have a too large L2, you can take too much time to lookup if what you request is in it, loosing performance. a CPU core can only compute so many data during x period of time. It's not efficient for data to stay into fast cache for a long period of time if it's not being used. It's then best to put it into L3 or memory. L2 cache take a lot of space so if you put too much, you are wasting opportunities to make your core more wide, increasing the performance.
L3 on the other hand sit outside the core and can be increased without impacting too much the core itself, although in the end, you are still using the same silicon space. This also probably why they don't get over 32 MB yet without the 3D V-cache. They probably simulated that wider core are better than 64 MB of L3 cache for the main die. There will always be a war on the low hanging fruits. the MHz wars was when it was "easy" to ramp up that number, then when they got stuck, they witched to core count. Now, except for very specific workload, there is diminishing return to go beyond a certain threshold at the detriment of faster core. So those days, it's cache. But i don't think that this 1 MB L2 cache is such big thing in the end. it's just to keep up with wider cores. The Added L3 cache on top of the CPU is probably more related. After all, Alder Lake already have 1.25 MB of L2.
But this "massive" L2 cache is not that big and it won't reduce at all the need of a larger L3 cache. They don't have the same purpose. The L3 cache is also used to communicate between cores. It's place in the design allow much larger size than L2 that is situated inside the core. On the latest Epyc 77x3, L1 is about 4 cycles latency, L2 is about 12, L3 is about 50 and a trip to memory is about 300+. (And L3 have way more bandwidth than main memory.)
It's all about what you run, how large is the working set, how frequently you access all of it, etc. Just putting all the time a super large cache wouldn't be a great idea right now like putting a big bunch of core wasn't that great of a idea a while ago. There are not that many application outside game, some server workload and scientific application that would benefits with their data set of having a super large L3. The area is better spend into wider core like in the past, i was smarter up to a point to make 4 wide core instead of 8 small.
That will probably change in the future and we will see soon enough CPU that have GBs of L3 cache.