Monday, October 17th 2022
AMD Rolls Out GCC Enablement for "Zen 4" Processors with Zenver4 Target, Enables AVX-512 Instructions
AMD earlier this week released basic enablement for the GNU Compiler Collections (GCC), which extend "Zen 4" microarchitecture awareness. The "basic enablement patch" for the new Zenver4 target is essentially similar to Zenver3, but with added support for the new AVX-512 instructions, namely AVX512F, AVX512DQ, AVX512IFMA, AVX512CD, AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, AVX512BITALG, and AVX512VPOPCNTDQ. Besides AVX-512, "Zen 4" is largely identical to its predecessor, architecturally, and so the enablement is rather basic. This should come just in time for software vendors to prepare for next-generation EPYC "Genoa" server processors, or even small/medium businesses building servers with Ryzen 7000-series processors.
Source:
Phoronix
6 Comments on AMD Rolls Out GCC Enablement for "Zen 4" Processors with Zenver4 Target, Enables AVX-512 Instructions
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Hopefully not true for their source code.
en.wikipedia.org/wiki/AVX-512
You're not used to assembly are you? It's very common to have many variants of each class of instructions, like one for each relevant data type and bit width, signedness, logical negation, types of comparison etc.
Just in the original 8086 assembly there were 32 jump instructions (+ 3 return instructions).
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Considering how impressive the gains from AVX-512 were for Zen 4, the gains will soon be even larger as the GNU C library adds more AVX-512 optimizations for common core features used in numerous applications.