Monday, January 30th 2023
AMD "Navi 31" Memory Cache Die Has Preparation for 3D Vertical Cache?
AMD possibly has a straightforward path to increasing the performance of the "Navi 31" RDNA3 GPU to power future high-end SKUs, according to semiconductor engineer Tom Wassick. The GPU's main SIMD machinery is located in the Graphics Compute Die (GCD) built on the 5 nm EUV foundry process, surrounded by six Memory Cache Dies (MCDs) built on 6 nm, which each contain GDDR6 memory controllers, and a 16 MB segment of the GPU's 96 MB Infinity Cache memory.
In microscopic observations, Wassick noticed structures on the MCD which he thinks look like an array of through-silicon vias (TSVs), of the kind used in "Zen 3" and "Zen 4" CCDs, to wire out stacked 3D Vertical Cache memory on the L3D (L3 cache die). If the theory holds up, it could be possible for AMD to increase the L3 cache segment size per MCD from 16 MB, and the GPU's overall Infinity Cache memory size. With its RDNA2 graphics architecture (RX 6000 series), AMD significantly enlarged on-die caches on its GPUs, particularly the last-level L3 cache, even giving them the special branding of "Infinity Cache," claiming that they had a big impact in lubricating the memory sub-system, letting GPUs with 256-bit memory buses compete with NVIDIA GPUs with wider 320-bit to 384-bit interfaces.
Sources:
Tom Wassick (Twitter), Tom's Hardware
In microscopic observations, Wassick noticed structures on the MCD which he thinks look like an array of through-silicon vias (TSVs), of the kind used in "Zen 3" and "Zen 4" CCDs, to wire out stacked 3D Vertical Cache memory on the L3D (L3 cache die). If the theory holds up, it could be possible for AMD to increase the L3 cache segment size per MCD from 16 MB, and the GPU's overall Infinity Cache memory size. With its RDNA2 graphics architecture (RX 6000 series), AMD significantly enlarged on-die caches on its GPUs, particularly the last-level L3 cache, even giving them the special branding of "Infinity Cache," claiming that they had a big impact in lubricating the memory sub-system, letting GPUs with 256-bit memory buses compete with NVIDIA GPUs with wider 320-bit to 384-bit interfaces.
76 Comments on AMD "Navi 31" Memory Cache Die Has Preparation for 3D Vertical Cache?
1) Switch GDDR6 20 Gbps to GDDR6X 24 Gbps chip
2) Put higher Power limite like 450W + 15% slider
3) take best binned silicone add 0.25V and a OC
That was the magical ~ bonus from a 6900 xt to 6950 xt and gain was correct for 100$ more ?
Guess what? That's not gaming.
The mile you're talking about doesn't matter a inch to the average gamer because outside of bar charts there is no visible difference for the average gamer in the real world. Mind you, I'm not advocating AMD, I'm just saying that outside of technological fanaticism those percentage differences really matter little.
It's one step at a time but it's clearly RT is the future.
Sure I could have fun with whatever GPU i have got, but I would definitely have more fun with faster and more features packed GPU vs slower one.
It varies from the gpu prices, lack of competitive features, drivers issues, no CUDA alternative etc.
What does it mean ? I don't know, but it's by a mile, I guess it depends how much of a fanboy you are.In case you forgot, AMD is still on top in terms of performance/price and Nvidia at the bottom, so this is complete nonsense.
2. It is not the power limit that is limiting performance. Reference cards need 3x8pin instead of 2x8pin and better official software undervolting to get better temps, lower pawer draw and higher clock speeds.
3. Neither AMD or Nvidia has any binned silicon at this point in terms of GPU's. Only some AIB's do binning (EVGA in the past and Galax now). But it's very resource intensive in terms of manpower.
4. I would also double the infinity cache because the option is there but not used on 7900XTX.
5. Does not add much but upgrade to PCIe 5.0 connector instead of PCIe 4.0 allowing to use fewer lanes on AM5 boards.
Mainstream consumer motherboards could come way down in price if we can get rid of the obligatory x16 PCIe connectors. Just four lanes of PCIe 5.0 is enough for the latest GPUs. Less lanes also means less expensive chipsets or no chipset at all.
The problem is the package compared to performance.
Everything else apart from the performance is worse.
Image reconstruction tech, RT performance, drivers issues, no cuda alternative, no NVENC alternative, at least AV1 on 7900s, etc.
So they are not cheap enough for the package they offer.
But we are off topic.
On topic, the 3D V cache even if it works with the gpus, it will give something that AMD does not need necessarily. More performance.
Someone with more knowledge can correct me or provide more detail.