Wednesday, February 28th 2024
Intel 10A (1 nm-class) Node to Enter Mass Production in 2027
Last week at the Intel Foundry Services Connect event, Intel unveiled its Intel 14A foundry node (1.4 nm-class), to succeed its Intel 18A and Intel 20A nodes, with mass production on this node expected to commence in 2026. It turns out that there is an even more advanced node Intel is working on, which it didn't announce last week, but which was part of an NDA presentation that the company forgot to lift. We're talking about the new Intel 10A node, a 1 nm-class silicon fabrication node that's a generation ahead of Intel 20A. The company says that it expects mass production on the node to begin toward the end of 2027. It is on the backs of these sub-2 nm class nodes, and the impending organizational changes that sees Intel Foundry Services become a more independent commercial entity, that Intel CEO Pat Gelsinger thinks that Intel will become the "TSMC of the West."
Currently, fabs that utilize EUV (extreme ultraviolet) lithography, namely the Intel 4, Intel 3, and Intel 20A; together make barely 15% of Intel's wafer volumes, with the bulk of the foundry's production focusing on the DUV based Intel 7. EUV-based nodes are expected to linearly grow till 2025, but what's interesting is that Intel doesn't see the kind of multi-year stagnation on Intel 4 and Intel 3 that it's currently experiencing with Intel 7; with wafer volumes of Intel 20A and 18A expected to exceed those of the Intel 4 and Intel 3 within 2025. By 2026, Intel expects that there will be twice as many Intel 20A/18A wafers pushed as Intel 4 and Intel 3. Although they use EUV, Intel 4 and Intel 3 are Intel's final nodes to implement FinFET transistors, as the company transitions to nanosheets with Intel 20A (which are called RibbonFETs in Intel jargon). Intel did not get into the technology behind Intel 10A. The company, along with Samsung and TSMC, demonstrated its stacked CFET transistor in 2023, which will power foundry nodes as nanosheets mature. Intel in its presentation also talked about the next wave of factory automation implemented by IFS, which sees AI-driven "cobots" (collaborative robots) replace humans for more roles in the clean room.
Source:
Tom''s Hardware
Currently, fabs that utilize EUV (extreme ultraviolet) lithography, namely the Intel 4, Intel 3, and Intel 20A; together make barely 15% of Intel's wafer volumes, with the bulk of the foundry's production focusing on the DUV based Intel 7. EUV-based nodes are expected to linearly grow till 2025, but what's interesting is that Intel doesn't see the kind of multi-year stagnation on Intel 4 and Intel 3 that it's currently experiencing with Intel 7; with wafer volumes of Intel 20A and 18A expected to exceed those of the Intel 4 and Intel 3 within 2025. By 2026, Intel expects that there will be twice as many Intel 20A/18A wafers pushed as Intel 4 and Intel 3. Although they use EUV, Intel 4 and Intel 3 are Intel's final nodes to implement FinFET transistors, as the company transitions to nanosheets with Intel 20A (which are called RibbonFETs in Intel jargon). Intel did not get into the technology behind Intel 10A. The company, along with Samsung and TSMC, demonstrated its stacked CFET transistor in 2023, which will power foundry nodes as nanosheets mature. Intel in its presentation also talked about the next wave of factory automation implemented by IFS, which sees AI-driven "cobots" (collaborative robots) replace humans for more roles in the clean room.
40 Comments on Intel 10A (1 nm-class) Node to Enter Mass Production in 2027
Transistor scaling is compared against older planar transistors. With the introduction of FinFet, GAAfet and others, the effective density is given a shrink value compared to how many of these old planar transistors would fit in the same area.
The smallest feature sizes of all competing nodes are still well over 10 nm and nowhere near atomic sizes. Someone posted a good youtube video explaining this a few days ago.
Edit: here it is
And you can ‘see it’ with a scanning electron microscope (SEM) just like you can see the rings of Saturn with a telescope. SEM allows you to measure the smallest feature sizes. Its not magic. Its science.
Intel makes Meteor Lake chips on Intel 4 which is around TSMC 4-5nm in terms of density (hence the name)
Intels 20A factory in germany should be up and running, I guess we will see if Arrow Lake will use 20A or not later this year, might be Intel 4
Also, Intel reserving and taking up space at TSMC is bad for AMD, probably part of the plan too. Apple, Nvidia and now Intel all have priority over AMD at TSMC. AMD always use the older nodes because they are cheaper. Apple always have top priority at TSMC tho. Without Apple, TSMC would not be in the lead. Apple put billions upon billions in TSMCs pockets over the years.
I expect Intel to regain leadership in the coming years tho and they will open up their foundry business. Maybe AMD can get their chips made at Intel LOL
www.techpowerup.com/319517/intel-ceo-discloses-tsmc-production-details-n3-for-arrow-lake-n3b-for-lunar-lake
“According to a China Times news article: "Gelsinger also confirmed the expansion of orders to TSMC, confirming that TSMC will hold orders for Intel's Arrow and Lunar Lake CPU, GPU, and NPU chips this year, and will produce them using the N3B process.”
“Past leaks have indicated that Intel's Arrow Lake processor family will have CPU tiles based on their in-house 20A process, while TSMC takes care of the GPU tile aspect with their 3 nm N3 process node.”
For the record, Intel 7 has a smaller fin pitch than TSMC 7 even though its channel length (where traditionally transistors get their sizes) is longer. Intel 7 is also comparable in density as TSMC 7 because the fin pitch is less. Kind of why they call it Intel 7. It used to be their Superfin 10, but recent improvements too it makes it their 7. Its just kind of bad perf/watt.
Basically, saying something is Xnm doesnt mean shit these days due to transistor structures being very different than they used to be and largely marketting now. Transistors can be the same size from say TSMC 7 to TSMC 6, but to make it TSMC 6 they just say its density is improved, perf/watt is better, area better but transistors themselves didnt change. There could even be another flavor of cell that has different VT characteristics added to the library.
But it's not too early for a pedantic debate about what "unveiled" (TPU) or "put on the roadmap" (Tom's) means...
@btarunr The link to Tom's doesn't work, it's truncated by one character.