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VIA Nano U2400

1
Cores
1
Threads
8 W
TDP
1300 MHz
Frequency
1400 MHz
Boost
CNA
Codename
VIA nanoBGA2
Socket
Front
Front
Back
Back
VIA nanoBGA2
VIA nanoBGA2
The VIA Nano U2400 was a mobile processor with 1 core, launched in May 2008. It is part of the Nano U lineup, using the Isaiah (CNA) architecture with VIA nanoBGA2. Nano U2400 has 1 MB of L2 cache and operates at 1300 MHz by default, but can boost up to 1400 MHz, depending on the workload. VIA is making the Nano U2400 on a 65 nm production node using 94 million transistors. The silicon die of the chip is not fabricated at VIA, but at the foundry of Fujitsu. The multiplier is locked on Nano U2400, which limits its overclocking potential.
With a TDP of 8 W, the Nano U2400 consumes extremely little energy. VIA's processor supports DDR2 and DDR3 memory with a single-channel interface. The highest officially supported memory speed is 1333 MT/s, but with overclocking (and the right memory modules) you can go even higher.
The SSE4 instruction set is not supported, which can cause problems with modern games, as they require that capability. Hardware virtualization is available on the Nano U2400, which greatly improves virtual machine performance.

Physical

Socket: VIA nanoBGA2
Foundry: Fujitsu
Process Size: 65 nm
Transistors: 94 million
Die Size: 63 mm²
Package: FC-BGA400

Processor

Market: Mobile
Production Status: End-of-life
Release Date: May 29th, 2008
Part#: unknown

Performance

Frequency: 1300 MHz
Turbo Clock: up to 1400 MHz
Base Clock: 200 MHz
Multiplier: 6.5x
Multiplier Unlocked: No
Voltage: 1 V
TDP: 8 W
Idle Power:0.1 W

Architecture

Codename: CNA
Generation: Nano U
(Isaiah (CNA))
Memory Support: DDR2, DDR3
Rated Speed: 1333 MT/s
Memory Bus: Single-channel
ECC Memory: No
Chipsets: VIA VX855, VIA VX900, VIA VN1000, VIA VX11

Core Config

# of Cores: 1
# of Threads: 1
SMP # CPUs: 1
Integrated Graphics: On certain motherboards (Chipset feature)

Cache

Cache L1: 128 KB
Cache L2: 1 MB

Features

  • MMX
  • SSE
  • SSE2
  • SSE3
  • SSSE3
  • AES
  • NX-bit
  • VT-x
  • SHA-1
  • SHA-256
  • x86-64
  • VIA Padlock
  • VIA Power Saver
  • Adaptive Overclocking

Notes

VIA V4 Bus is a quad-pumped front side bus architecture, therefore Base Clock*4 gives the advertised FSB.

DRAM, Graphics, I/O, and Audio handled by the VIA MSP chipset used.

VIA Adaptive Overclocking enabled. Adaptive Overclocking relies on the CPU die temperature to remain under the software defined maximum while at the highest rated P-State, which triggers a half-multiplier step-up by switching to the idle secondary PLL.
Jan 23rd, 2025 00:16 EST change timezone

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