AMD today announced the AMD Versal Premium VP1902 adaptive system-on-chip (SoC), the world's largest adaptive SoC. The VP1902 adaptive SoC is an emulation-class, chiplet-based device designed to streamline the verification of increasingly complex semiconductor designs. Offering 2X the capacity over the prior generation, designers can confidently innovate and validate application-specific integrated circuits (ASICs) and SoC designs to help bring next generation technologies to market faster.

AI workloads are driving increased complexity in chipmaking, requiring next-generation solutions to develop the chips of tomorrow. FPGA-based emulation and prototyping provides the highest level of performance, allowing faster silicon verification and enabling developers to shift left in the design cycle and begin software development well before silicon tape-out. AMD, through Xilinx, brings over 17 years of leadership and six generations of the industry's highest capacity emulation devices, which have nearly doubled in capacity each generation.

Back in January, we got our first look at the cinder block-like 4-slot cooling solution of NVIDIA's upcoming flagship graphics card (called either the RTX 4090 Ti, or the TITAN (Ada). "ExperteVallah" on Twitter scored additional pictures of the cooler. Its design sees the heat dissipation surface pushed to the entire thickness of the cooler, and ventilated the entire length.

The card's PCB isn't conventional—not perpendicular to the plane of the motherboard like any other add-in card—but is rather along the plane of the motherboard, with additional breakaway daughter cards interfacing with the sole 12VHPWR power connector, and the PCIe slot. This slender, ruler-shaped PCB spans the entire length of the card, without coming in the way of its heat dissipation surfaces. The length is used for the large AD102 ASIC that's probably maxed out (with all its 144 SM enabled), twelve GDDR6X (possibly faster 23 Gbps), and a mammoth VRM that nearly maxes out the 600 W continuous power delivery design limit of the 12VHPWR.

AMD Radeon RX 7800 XT will be a much-needed performance-segment addition to the company's Radeon RX 7000-series, which has a massive performance gap between the enthusiast-class RX 7900 series, and the mainstream RX 7600. A report by "Moore's Law is Dead" makes a sensational claim that it is based on a whole new ASIC that's neither the "Navi 31" powering the RX 7900 series, nor the "Navi 32" designed for lower performance tiers, but something in between. This GPU will be AMD's answer to the "AD103." Apparently, the GPU features the same exact 350 mm² graphics compute die (GCD) as the "Navi 31," but on a smaller package resembling that of the "Navi 32." This large GCD is surrounded by four MCDs (memory cache dies), which amount to a 256-bit wide GDDR6 memory interface, and 64 MB of 2nd Gen Infinity Cache memory.

The GCD physically features 96 RDNA3 compute units, but AMD's product managers now have the ability to give the RX 7800 XT a much higher CU count than that of the "Navi 32," while being lower than that of the RX 7900 XT (which is configured with 84). It's rumored that the smaller "Navi 32" GCD tops out at 60 CU (3,840 stream processors), so the new ASIC will enable the RX 7800 XT to have a CU count anywhere between 60 to 84. The resulting RX 7800 XT could have an ASIC with a lower manufacturing cost than that of a theoretical Navi 31 with two disabled MCDs (>60 mm² of wasted 6 nm dies), and even if it ends up performing within 10% of the RX 7900 XT (and matching the GeForce RTX 4070 Ti in the process), it would do so with better pricing headroom. The same ASIC could even power mobile RX 7900 series, where the smaller package and narrower memory bus will conserve precious PCB footprint.

Molex, a company known for making various electronics and connectors, has today announced that the company has developed a first-of-its-kind chip-to-chip connector. Designed mainly for the data center, the Molex 224G product portfolio includes next-generation cables, backplanes, board-to-board connectors, and near-ASIC connector-to-cable solutions. Running at 224 Gbps speeds, these products use PAM4 signaling and boast with " highest levels of electrical, mechanical, physical and signal integrity." As the company states, future high-performance computing (HPC) data centers require a lot of board-to-board, chip-to-chip, and other types of communication to improve overall efficiency and remove bottlenecks in data transfer. To tackle this problem, Molex has a range of products, including Mirror Mezz Enhanced, Inception, and CX2 Dual Speed products.

Future generative AI, 1.6T (1.6 Tb/s) Ethernet, and other data center challenges need a dedicated communication standard, which Molex is aiming to provide. Working with various data center and enterprise customers, the company claims to have set the pace for products based on this 224G PAM4 chip-to-chip technology. We suspect that Open Compute Project (OCP) will be first in the line of adoption, ad Molex has historically worked with them as they adopted Mirror Mezz and Mirror Mezz Pro board-to-board connectors. The new products can be seen below, and we expect to hear more announcements from Molex's partners. Solutions like OSFP 1600, QSFP 800, and QSFP-DD 1600 already use 224G products.

Bosch is expanding its semiconductor business with silicon carbide chips. The technology company plans to acquire assets of the U.S. chipmaker TSI Semiconductors, based in Roseville, California. With a workforce of 250, the company is a foundry for application-specific integrated circuits, or ASICs. Currently, it mainly develops and produces large volumes of chips on 200-millimeter silicon wafers for applications in the mobility, telecommunications, energy, and life sciences industries. Over the next years, Bosch intends to invest more than 1.5 billion USD in the Roseville site and convert the TSI Semiconductors manufacturing facilities to state-of-the-art processes. Starting in 2026, the first chips will be produced on 200-millimeter wafers based on the innovative material silicon carbide (SiC).

In this way, Bosch is systematically reinforcing its semiconductor business, and will have significantly extended its global portfolio of SiC chips by the end of 2030. Above all, the global boom and ramp-up of electromobility are resulting in huge demand for such special semiconductors. The full scope of the planned investment will be heavily dependent on federal funding opportunities available via the CHIPS and Science Act as well as economic development opportunities within the State of California. Bosch and TSI Semiconductors have reached an agreement to not to disclose any financial details of the transaction, which is subject to regulatory approval.

Today Intel announced that they would be discontinuing production of their Blockscale 1000 series of ASICs built for cryptocurrency mining. Blockscale was designed by the Custom Compute Group within what was Intel's AXG graphics division at the time, and launched to market back in April 2022 when the value of Bitcoin was still above $40K USD. Blockscale initially succeeded with efficiency and supply advantages over competing ASICs as Intel leveraged their manufacturing capacity to produce the chips, however the valuation of the crypto currency market experienced a major slump over the second half of 2022. Intel's AXG has also recently seen a major restructuring, though there have been no mentions of what the operable status is of the Custom Compute Group. Support for existing Blockscale customers is set to continue for some time. Intel has not announced any possible follow-up crypto ASIC generation, only saying, "We continue to monitor market opportunities."

Intel's Blockscale was rather late to the market as far as crypto mining ASICs go. Early mining ASICs began hitting the scene in mid-2012 as FPGAs started to reach their limits in efficiency, and investment funds began to funnel into crypto startups. Intel's interest in cryptocurrency hardware lagged behind even their contemporaries at NVIDIA and AMD, both of which had crypto-focused variants of consumer GPUs on the market as early as 2017 during the first major mining-induced hardware shortages. Intel hasn't mentioned whether the timing of Blockscale contributed to its short shelf life, but Bitcoin is on its way back up after the recent slump, shooting up to around $30K USD just prior to Intel's announcement.

AMD today announced the AMD Alveo MA35D media accelerator featuring two 5 nm, ASIC-based video processing units (VPUs) supporting the AV1 compression standard and purpose-built to power a new era of live interactive streaming services at scale. With over 70% of the global video market being dominated by live content, a new class of low-latency, high-volume interactive streaming applications are emerging such as watch parties, live shopping, online auctions, and social streaming.

The Alveo MA35D media accelerator delivers the high channel density, with up to 32x 1080p60 streams per card, power efficiency and ultra-low-latency performance critical to reducing the skyrocketing infrastructure costs now required for scaling such compute intensive content delivery. Compared to the previous generation Alveo U30 media accelerator, the Alveo MA35D delivers up to 4x higher channel density, 4x max lower latency in 4K and 1.8x greater compression efficiency to achieve the same VMAF score—a common video quality metric.

Phison Electronics, a global leader in NAND flash and storage solutions, announced today the launch of IMAGIN+, an upgraded platform offering R&D resource sharing and ASIC (Application-Specific Integrated Circuit) design services for NAND flash controllers, storage solutions, PMIC, and Redrivers/Retimers. The introduction of IMAGIN+ comes during the Embedded World Exhibition & Conference (March 14-16) in Nuremberg, a premier global event for the embedded community.

Phison's rejuvenated platform, bolstered by more than two decades of research and development expertise, empowers global partners and customers to create not just ASIC chips and NAND flash storage solutions but also to participate in the growth of a thriving ecosystem of emerging technologies. Phison understands that success in today's fast-paced market requires more than just providing NAND storage solutions; it requires the ability to influence and shape the industry through signal integrity and power management ICs, Compute Express Link and other value-added offerings.

Aetina Corporation, a leading provider of AI solutions for the creations of different types of vertical AI, will showcase its new embedded computers, AI inference platforms, GPUs, AI accelerators, and edge devices management software at upcoming Embedded World 2023. Aetina provides different types of form factors based on GPUs or ASICs, such as MXMs, graphic cards, and edge computing systems. The MXMs that are powered by NVIDIA Ampere architecture-based GPU offer extra computing power to existing AI systems, ensuring low-latency data analytics tasks. The MXMs and systems that are built with ASICs, on the other hand, are ideal for the creation of any specific applications or AI systems that involve multi-inference processes.

As an Elite member of the NVIDIA Partner Network, Aetina offers a variety of edge computing systems and platforms powered by the NVIDIA Jetson edge AI and robotics platform. Aetina's newly released embedded computers are built with the Jetson Orin series SoMs—Jetson AGX Orin, Jetson Orin NX, and Jetson Orin Nano ; these small-sized systems and platforms, supporting different peripherals, can be easily integrated into larger AI-powered systems while also being able to function as a standalone AI computer.

An entity calling themselves "TP-Link ASIC" recently announced a Wi-Fi 7 capable ASIC cryptocurrency miner with claims of hashing rates above even the mighty RTX 4090... In one specific ASIC friendly algorithm. If the concept of a router that mines crypto sounds strange, deranged, or downright questionable to you, you're not alone. The consumer market for crypto mining has waned heavily in the last handful of months due in no small part to Ethereum switching to Proof of Stake last September, which led to GPUs being ineffectual for mining the previously profitable coin. However, ASIC mining does remain prevalent across the sea of various algorithms and alt-coins that exist. One such alt-coin is Kadena, a smaller Proof of Work cryptocurrency that appears to flutter around the $1USD range. This is where "TP-Link ASIC" has placed their engineering efforts with the, "TP-Link NX31 31.2 THS Router Miner," which, as the name implies, offers 31.2 TH/s of Kadena hashing power at a cool $1,990 USD (previously $1,440).

If you've been around long enough to remember the Butterfly Labs fiasco and fallout, you're probably already groaning and holding your head in your hands. Buying ASICs from new and unproven vendors promising the moon is never a good idea. But TP-Link isn't an unproven company, they have a successful business and sell legitimate products. Surely this would be handled properly since this is a well established brand, right? Well, here's the twist; "TP-Link ASIC" is NOT TP-Link. When questioned about this new launch by Tom's Hardware a TP-Link representative responded that "TP-Link ASIC" has no affiliation with TP-Link, nor does their NX31 mining router.

For more than a decade, Intel and its partners have been on a mission to virtualize the world's networks, from the core to the RAN (radio access network) and out to the edge, moving them from fixed-function hardware onto programmable, software-defined platforms, making networks more agile while driving down their complexity and cost.

Now operators are looking to cross the next chasm in delivering cloud-native functionality for automating, managing and responding to an increasingly diverse mix of data and services, providing organizations with the intelligence needed at the edge of their operations. Today, Intel announced a range of products and solutions driving this transition and broad industry support from leading operators, original equipment manufacturers (OEMs) and independent software vendors (ISVs).

Fortinet, the global cybersecurity leader driving the convergence of networking and security, today announced FortiSP5, the latest breakthrough in ASIC technology from Fortinet, propelling major leaps forward in securing distributed network edges. Building on over 20 years of ASIC investment and innovation from Fortinet, FortiSP5 delivers significant secure computing power advantages over traditional CPU and network ASICs, lower cost and power consumption, the ability to enable new secure infrastructure across branch, campus, 5G, edge compute, operational technologies, and more.

"With the introduction of FortiSP5, Fortinet once again sets new industry records for performance, cost, and energy efficiency. As the only cybersecurity vendor leveraging purpose-built ASICs, an over 20-year investment in innovation, Fortinet delivers the secure computing power that will support the next generation of secure infrastructure." Ken Xie, Founder, Chairman of the Board, and Chief Executive Officer at Fortinet

In a continuing commitment to enabling industry-leading data acceleration in heterogeneous compute environments, Achronix Semiconductor Corporation, the industry's only independent supplier of high-end FPGAs and eFPGA IP solutions, today announced the production release of its AC7t1500 FPGA and the addition of the power-efficient AC7t800 FPGA to the Achronix Tool Suite.

"The Speedster 7t product family offers unprecedented FPGA-based performance for data acceleration applications," said Steve Mensor, VP of Marketing and Business Development at Achronix. "The release of the AC7t1500 to production along with the addition of the AC7t800 in our ACE design tools gives customers multiple options from this industry-leading, high-performance family that offers FPGA programmability with ASIC-level performance. These advancements give customers confidence that they can design on a robust, validated FPGA product family that meets their high-performance and high-bandwidth needs."

Aetina, an edge AI solution provider that offers edge computing hardware and software for use in AI and IoT, has launched the first-ever MXM module that is powered by Hailo-8 AI inference processors. The ASIC-based MXM 3.1 module—AI-MXM-H84A—is designed for different AI applications, to boost their performance; the applications include automatic guided vehicles (AGVs) in logistics, virtual fence systems in manufacturing, as well as other kinds of autonomous machines and computer vision systems.

Aetina AI-MXM-H84A modules feature four Hailo-8 AI processors, providing up to 104 Tera-Operations Per Second (TOPS) AI performance with best-in-class power efficiency to speed up deployment of neural network (NN) and deep learning (DL) processes on edge devices by AI developers. The Hailo-8 AI accelerator allows edge devices to run DL applications at full scale with superb efficiency, effectiveness, and sustainability. Due to its small-sized form factor, the high-performance MXM 3.1 type B module can be easily integrated into a variety of embedded systems by developers and system integrators to handle heavy inference workloads with low latency.

Seagate Technology Holdings plc, a world leader in mass-data storage infrastructure solutions, today announced its next-generation Exos X systems, the advanced storage arrays powered by Seagate's sixth generation controller architecture. The new Exos X systems feature up to twice the performance of the previous generation and enhanced enterprise-class durability. To help protect the stored data, Exos X systems incorporate ADAPT (Advanced Distributed Autonomic Protection Technology) erasure coding solution with Seagate's innovative self-healing storage technology ADR (Autonomous Drive Regeneration).

The Exos X series is a family of petabyte-scale, rack-mounted block storage enclosures that aggregate and virtualize dozens to hundreds of hard drives and SSDs for maximum data resiliency, availability and performance. Exos X systems are ideal as highly available enterprise storage infrastructure for conventional enterprise data centers as well as private clouds.

Silicon Motion Technology Corporation ("Silicon Motion"), a global leader in designing and marketing NAND flash controllers and solid-state storage devices today announces MonTitan, a PCIe Gen5 SSD solution platform perfectly suited for the most challenging Datacenter and Enterprise applications. Silicon Motion's new MonTitan platform features an entirely new, purpose-built ASIC and FW architecture, optimized for performance and QoS. Its unique Layered FW stack enables the development of customer differentiated solutions with a high degree of flexibility and accelerated time to market, all while reducing engineering cost.

"SSD storage solutions are evolving to address new challenges in data centers which demand changes in storage platforms and operating models," said Nelson Duann, Silicon Motion's Senior Vice President of Marketing and R&D. "Our MonTitan SSD solution is an innovative PCIe Gen5 SSD platform designed to satisfy the unique demands of datacenters today while providing flexibility and programmability to meet future evolving standards."

According to TrendForce investigations, foundries have seen a wave of order cancellations with the first of these revisions originating from large-size Driver IC and TDDI, which rely on mainstream 0.1X μm and 55 nm processes, respectively. Although products such as MCU and PMIC were previously in short supply, foundries' capacity utilization rate remained roughly at full capacity through their adjustment of product mix. However, a recent wave cancellations have emerged for PMIC, CIS, and certain MCU and SoC orders. Although still dominated by consumer applications, foundries are beginning to feel the strain of the copious order cancellations from customers and capacity utilization rate has officially declined.

Looking at trends in 2H22, TrendForce indicates, in addition to no relief from the sustained downgrade of driver IC demand, inventory adjustment has begun for smartphones, PCs, and TV-related peripheral components such as SoCs, CIS, and PMICs, and companies are beginning to curtail their wafer input plans with foundries. This phenomenon of order cancellations is occurring simultaneously in 8-inch and 12-inch fabs at nodes including 0.1X μm, 90/55 nm, and 40/28 nm. Not even the advanced 7/6 nm processes are immune.

Ayar Labs, the leader in chip-to-chip optical connectivity, is developing with NVIDIA groundbreaking artificial intelligence (AI) infrastructure based on optical I/O technology to meet future demands of AI and high performance computing (HPC) workloads. The collaboration will focus on integrating Ayar Labs' technology to develop scale-out architectures enabled by high-bandwidth, low-latency and ultra-low-power optical-based interconnects for future NVIDIA products. Together, the companies plan to accelerate the development and adoption of optical I/O technology to support the explosive growth of AI and machine learning (ML) applications and data volumes.

Optical I/O uniquely changes the performance and power trajectories of system designs by enabling compute, memory and networking ASICs to communicate with dramatically increased bandwidth, at lower latency, over longer distances and at a fraction of the power of existing electrical I/O solutions. The technology is also foundational to enabling emerging heterogeneous compute systems, disaggregated/pooled designs, and unified memory architectures that are critical to accelerating future data center innovation.

Samsung Electronics, the world leader in advanced memory technology, today announced its development of the industry's first 512-gigabyte (GB) Compute Express Link (CXL) DRAM, taking an important step toward the commercialization of CXL which will enable extremely high memory capacity with low latency in IT systems. Since introducing the industry's first CXL DRAM prototype with a field-programmable gate array (FPGA) controller in May 2021, Samsung has been working closely with data center, enterprise server and chipset companies to develop an improved, customizable CXL device.

The new CXL DRAM is built with an application-specific integrated circuit (ASIC) CXL controller and is the first to pack 512 GB of DDR5 DRAM, featuring four times the memory capacity and one-fifth the system latency over the previous Samsung CXL offering. "CXL DRAM will become a critical turning point for future computing structures by substantially advancing artificial intelligence (AI) and big data services, as we aggressively expand its usage in next-generation memory architectures including software-defined memory (SDM)," said Cheolmin Park, Vice President of Memory Global Sales & Marketing at Samsung Electronics, and Director of the CXL Consortium. "Samsung will continue to collaborate across the industry to develop and standardize CXL memory solutions, while fostering an increasingly solid ecosystem."

Seagate Technology Holdings plc, a world leader in mass-data storage infrastructure solutions, and Phison Electronics Corp., a global leader in NAND flash controller and storage solutions, announced today plans to expand their SSD portfolio of next-gen high-performance, high-density enterprise NVMe SSDs. The new SSDs will help enterprises lower total cost ownership (TCO) through increased storage density, lower power consumption, and higher performance. The companies also announced that they have entered a long-term partnership that will strengthen the development cycle and distribution of enterprise-class SSDs.

Seagate and Phison have collaborated on Seagate's mainstream SATA SSD products since 2017. That close cooperation has continued through the company's performance-leading line of FireCuda consumer gaming NVMe PCIe Gen4 x4 SSDs and the world's first purpose-built NAS NVMe SSDs. The partnership will now focus on meeting the evolving global enterprise demand for higher density, faster, and smarter storage infrastructure needs that complement HDD storage to enable comprehensive enterprise applications such as hyperscale data center, high-performance computing and AI.

AMD's Radeon RX product stack refresh for Spring-Summer, is reportedly set to launch on May 10, 2022. Here's the first picture of what a reference-design RX 6950 XT flagship, RX 6750 XT, and the mid-range RX 6650 XT, could look like. These reference board designs are essentially identical to the original RX 6000 made-by-AMD (MBA) reference designs, but ditch the two-tone silver+black color-scheme for an all-black scheme with some diamond-cut edges around the fan vents, and some piano-black accents.

At this point it is not known if this refresh sees the Navi 20-series ASICs optically-shrunk to the TSMC N6 (6 nm) silicon fabrication node, or if it's the existing 7 nm ASICs with their total graphics power (TGP) values dialed up to make room for increased engine clocks, and faster 18 Gbps-rated GDDR6 memory chips. It's interesting to see the RX 6750 XT now come with a triple-fan cooler that resembles the RX 6800 (non-XT) cooler in design, if not color. We're not sure if the RX 6650 XT reference design will ever make it to the real-world, or if it's just a concept, and the SKU is an AIB-exclusive (custom-designs only).

Intel today announced details for its new Intel Blockscale ASIC. Building on years of Intel research and development (R&D), this application-specific integrated circuit (ASIC) will provide customers with energy-efficient hashing for proof-of-work consensus networks. Compute requirement for blockchains utilizing proof-of-work consensus mechanisms is growing at a rapid rate due to their resiliency and ability to scale without sacrificing decentralization. This growing pool of computing power requires an enormous amount of energy, necessitating new computing technologies that can provide the requisite power in a more energy-efficient manner while also being durable enough to mitigate long-term e-waste concerns.

"Momentum around blockchain continues to build. It is the enabler of decentralized and distributed computing, making way for innovative business models. To power this new era of computing, Intel is delivering solutions that can offer an optimal balance of hashing throughput and energy efficiency regardless of a customer's operating environment. Intel's decades of R&D in cryptography, hashing techniques and ultra-low voltage circuits make it possible for blockchain applications to scale their computing power without compromising on sustainability," said Balaji Kanigicherla, Intel vice president and general manager of Custom Compute in the Accelerated Computing Systems and Graphics Group.

Some interesting technical specifications of the elusive two GPUs behind the Intel Arc "Alchemist" series surfaced. The larger DG2-512 silicon in particular, which forms the base for the Arc 5 and Arc 7 series, is interesting, in that it is larger in every way than the performance-segment ASICs from both NVIDIA and AMD. The table below compares the physical specs of the DG2-512, with the NVIDIA GA104, and the AMD Navi 22. This segment of GPUs has fairly powerful use-cases, including native 1440p gameplay, or playing at 4K with a performance enhancement—something Intel has, in the form of the XeSS.

The DG2-512 is built on the 6 nm TSMC N6 foundry node, the most advanced node among the three GPUs in this class. It has the highest transistor density of 53.4 mTr/mm², and the largest die-area of 406 mm², and the highest transistor-count of 21.7 billion. The Xe-HPG graphics architecture is designed for full DirectX 12 Ultimate feature support, and the DG2-512 dedicated hardware for ray tracing, as well as AI acceleration. The Arc A770M is the fastest product based on this silicon, however, it is a mobile GPU with aggressive power-management characteristic to the form-factor it serves. Here, the DG2-512 has an FP32 throughput of 13.5 TFLOPs, compared to 13.2 TFLOPs of the Navi 22 on the Radeon RX 6700 XT desktop graphics card, and the 21.7 TFLOPs of the GA104 that's maxed out on the GeForce RTX 3070 Ti desktop graphics card.

When NVIDIA launched the GeForce RTX 3050 "Ampere" based on the "GA106" silicon with specifications that could be fulfilled with the smaller "GA107," we knew that the company could eventually start making RTX 3050 boards with the smaller chip, and they did. Igor's Lab reports that RTX 3050 cards based on GA107 come with a typical board power of 115 W, which is about 11 percent lower than that of the GA106-based cards (130 W).

There's no difference in specifications between the two cards. Both feature 2,560 CUDA cores across 20 streaming multiprocessors, 80 Tensor cores, 20 RT cores, and a 128-bit wide GDDR6 memory interface, holding 8 GB of memory that ticks at 14 Gbps data-rate (224 GB/s bandwidth). The GA106 and GA107 ASICs share a common fiberglass substrate, and hence are pin-compatible for the convenience of board partners, with the latter having a smaller die, so any cooling solution designed for the launch-day RTX 3050 should work perfectly fine with those based on GA107.

Digital computing continues to enrich our lives in more ways than we can imagine. We acquire, consume, and create content and services with a few clicks or taps of our fingertips. Exponential increases in compute performance, enabled by Moore's Law, play a significant role in making these experiences seamless. Moore's Law is also enabling us to democratize access to this enormous pool of processing power. Amazing things happen when a lot of compute is available to a lot of people without much friction.

Blockchain is a technology that has the potential to enable everyone to own much of the digital content and services they create. Some even call it an inflection point in computing, fundamentally disrupting the way we store, process and transact our digital assets as we usher in the era of metaverse and Web 3.0. No matter how the future evolves, it is certain the availability of a lot more compute to everyone will play a central role.