AMD today announced the AMD Alveo UL3422 accelerator card, the latest addition to its record-breaking family of accelerators1 designed for ultra-low latency electronic trading applications. AMD Alveo UL3422 provides trading firms, market makers and financial institutions with a slim form factor accelerator optimized for rack space, cost and designed for a fast path to deployment in a wide range of servers. The Alveo UL3422 accelerator is powered by an AMD Virtex UltraScale+ FPGA that features a novel transceiver architecture with hardened, optimized network connectivity cores, custom built for high-speed trading. It enables ultra-low latency trade execution, achieving less than 3ns FPGA transceiver latency and breakthrough 'tick-to-trade' performance not achievable with standard off-the-shelf FPGAs.

"Speed is the ultimate advantage in the increasingly competitive world of high-speed trading," said Yousef Khalilollahi, corporate vice president & general manager, Adaptive Computing Group, AMD. "The Alveo UL3422 card provides a lower-cost entry point while still delivering cutting-edge latency performance, making it accessible to firms of all sizes that want to stay competitive in the ultra-low latency trading space."

Jabil Inc. announced today that it is expanding its server portfolio with the J421E-S and J422-S servers, powered by AMD 5th Generation EPYC and Intel Xeon 6 processors. These servers are purpose-built for scalability in a variety of cloud data center applications, including AI, high-performance computing (HPC), fintech, networking, storage, databases, and security — representing the latest generation of server innovation from Jabil.

Built with customization and innovation in mind, the design-ready J422-S and J421E-S servers will allow engineering teams to meet customers' specific requirements. By fine-tuning Jabil's custom BIOS and BMC firmware, Jabil can create a competitive advantage for customers by developing the server configuration needed for higher performance, data management, and security. The server platforms are now available for sampling and will be in production by the first half of 2025.

Infineon Technologies AG today announced the addition of the EZ-USB FX20 programmable USB peripheral controller to its EZ-USB product family. It enables developers to create USB devices that meet the highest performance requirements in AI, image processing and emerging applications. The EZ-USB FX20 peripheral controller offers high-speed connectivity with USB 20 Gbps and LVDS interfaces, increasing the total bandwidth up to six times over its predecessor, the EZ-USB FX3.

"With the growing popularity of USB devices, the demand for compatible and adaptable USB controllers is increasing," said Ganesh Subramaniam, Senior Vice President and General Manager of the Wired Connectivity Solutions Product Line at Infineon. "Therefore, we are continuously improving the features and performance of our EZ-USB peripheral controllers and are pleased to support developers with our new addition to the product family, providing them with a flexible component to create powerful and advanced applications."

Altera, an Intel Company, today unveiled an array of FPGA hardware, software and development tools that make its programmable solutions more accessible across a broader range of use cases and markets. At its annual developer's conference, Altera revealed new details on its next-generation, power- and cost-optimized Agilex 3 FPGAs and announced new development kits and software support for its Agilex 5 FPGAs.

"Working closely with our ecosystem and distribution partners, Altera remains committed to delivering FPGA-based solutions that empower innovators with leading-edge programmable technologies that are easy to design and deploy. With these key announcements, we continue to execute on our vision of shaping the future by using programmable logic to help customers unlock greater value across a broad range of use cases within the data center, aerospace and defense sectors, communications infrastructure, automotive, industrial, test, medical and embedded markets," said Sandra Rivera, CEO of Altera.

Magewell's USB Capture family has long been the gold standard for professional video capture devices, earning a reputation for being the easiest and most reliable way to bring video and audio signals into software for live streaming, video conferencing, medical imaging and more. Magewell has expanded the renowned product line with the unveiling of a new model that captures video sources up to 4K resolution at 60 frames per second - the USB Capture HDMI 4K Pro. The new model will be demonstrated alongside other Magewell innovations in stand 7.A44 at the IBC2024 exhibition in Amsterdam from September 13 to 16.

Magewell's compact USB Capture devices enable computers including laptops to capture high-quality AV signals through a USB interface, with no additional power source required. The new USB Capture HDMI 4K Pro offers everything that users love about the existing USB Capture HDMI 4K Plus model, while leveraging 20 Gbps USB transfer performance on compatible host systems to enable the capture of 4K video at higher frame rates and color precision.

Intel is reportedly exploring the sale of its Altera business, a move guided by CEO Pat Gelsinger as part of broader restructuring efforts. Acquired by Intel in 2015 for $16.7 billion, Altera, formerly known as the Programmable Solutions Group, has been a profitable segment. However, with Intel facing financial strain due to extensive spending, the company is now considering divesting its FPGA business to recoup capital. Currently, Altera operates as a separate entity within Intel, relying on the tech giant for R&D, sales, marketing, and support. Gelsinger is expected to propose the sale at a board meeting scheduled for mid-September, where he will outline his vision for Intel's future. This restructuring could also affect other parts of Intel's operations, including its Foundry business.

While previous reports suggested that Intel might spin off its Foundry unit or sell it to industry leaders like TSMC or Samsung, the latest information indicates that Intel plans to retain this division, albeit with scaled-back expansion efforts. The $32 billion factory in Germany, for example, may be scrapped, along with other capital-intensive projects, and other capital expansions may also be put on hold. Pat Gelsinger's vision still needs to be finalized and is still in the drafting phase, so until the mid-September board meeting, we have to wait to gain more information.

Tachyum today announced the final build of its Prodigy FPGA emulation system in advance of chip production and general availability next year. As part of the announcement, the company is also ending its purchase program for prototype systems that was previously offered to commercial and federal customers.

These last hardware FPGA prototype units will ensure Tachyum hits its extreme-reliability test targets of more than 10 quadrillion cycles prior to tape-out and before the first Prodigy chips hit the market. Tachyum's software emulation system - and access to it - is expanding with additional availability of open-source software ported ahead of Prodigy's upstreaming.

According to sources close to Bloomberg, Intel plans to cut 10,000 jobs from its global workforce. The news comes amid heavy pressure on the semiconductor giant, which has been on a steady decline over the years, while other industry rivals like AMD and NVIDIA have been rising and taking market share in various areas from Intel. It is reported that Intel currently has 110,000 employees globally, and reducing the workforce by 10,000 would net Intel around 100,000 global employees left. These figures exclude employees from spun-out units like Altera FPGA company, which is under Intel's ownership. Intel's aim to reduce its workforce is expected to come with a significant cost benefit to the company, with projected savings of $10 billion by 2025.

The news isn't yet official, but it is expected to see the light of the day as soon as this week. As Intel's CEO Pat Gelsinger invests heavily into the fab construction and development of next-generation products, there have been a few notes that Intel would have to overcome some challenges shortly to reach its long-term goals like more advanced silicon manufacturing facilities and new products for AI/HPC and client sector. One of those short-term measures is reducing the workforce to cut down expenses. Intel has reduced its workforce before. In 2022, the company announced reduced spending in non-critical areas and reducing the workforce, and in 2023, cut the workforce by 5% to 124,800 employees last year, only to be left with 110,000 employees in 2024.

MaxLinear, Inc., a leading provider of data storage acceleration solutions for enterprise and data center applications, today announced it will demonstrate the advanced compression, encryption, and security performance of its storage acceleration solution, Panther III, at the Future of Memory and Storage (FMS) 2024 trade show from August 6-8, 2024. The demos will show that Panther III can achieve up to 40 times more throughput, up to 190 times better latency, and up to 1000 times less CPU utilization than a software-only solution, leading to significant cost savings in terms of flash drives and needed CPU cores.

MaxLinear's Panther III creates a bold new product category for maximizing the performance of data storage systems - a comprehensive, all-in-one "storage accelerator." Unlike encryption and/or compression solutions, MaxLinear's Panther III consolidates a comprehensive suite of storage acceleration functions, including compression, deduplication, encryption, data protection, and real-time validation, in a single hardware-based solution. Panther III is engineered to offload and expedite specific data processing tasks, thus providing a significant performance boost, storage cost savings, and energy savings compared to traditional software-only, FPGA, and other competitive solutions.

Lattice Semiconductor, the low power programmable leader, today announced the addition of new, logic-optimized Lattice Certus -NX FPGA devices to its leadership small FPGA portfolio. The new offering includes two new capacity points, the Certus -NX-28 and Certus -NX-09, and multiple package options that offer class-leading power efficiency, small size, and reliability with flexible migration options. These devices are designed to accelerate a broad range of Communications, Computing, Industrial, and Automotive applications.

"Lattice is committed to delivering continued innovation in small, low power FPGAs to empower our customers with optimized solutions for space-constrained applications ranging from sensor interfacing to co-processing to low power AI," said Dan Mansur, Corporate Vice President, Product Marketing, Lattice Semiconductor. "We're excited to expand our Nexus-based small FPGA offerings by adding more migratable logic and package options including 0.8 mm pitch, ideal for Industrial applications."

TrendForce's latest industry report on AI servers reveals that high demand for advanced AI servers from major CSPs and brand clients is expected to continue in 2024. Meanwhile, TSMC, SK hynix, Samsung, and Micron's gradual production expansion has significantly eased shortages in 2Q24. Consequently, the lead time for NVIDIA's flagship H100 solution has decreased from the previous 40-50 weeks to less than 16 weeks.

TrendForce estimates that AI server shipments in the second quarter will increase by nearly 20% QoQ, and has revised the annual shipment forecast up to 1.67 million units—marking a 41.5% YoY growth.

Today marks a new milestone in the growth of Intel Foundry's design ecosystem as key partners Ansys, Cadence, Siemens, and Synopsys have announced the availability of reference flows for Intel's embedded multi-die interconnect bridge (EMIB) advanced packaging technology. This comes on the heels of recent announcements where those same partners declared readiness for Intel 18A designs. "Today's news shows how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI systems ambitions," said Suk Lee, vice president for Ecosystem Development, Intel Foundry.

The success of Intel Foundry is rooted in collaboration with a vibrant design ecosystem. This ensures customers can access our leading process and packaging technologies. Now, in collaboration with our ecosystem partners, we are making it as easy and as fast as possible for companies to optimize, fabricate and assemble their system-on-chip designs through our foundries, while enabling their designers with validated EDA tools, design flows and IP portfolios for silicon-through-package design. This systems foundry approach allows our customers to innovate at every layer of the stack so they can meet the complex computing demands of the AI era, where chip architectures increasingly rely on multiple CPUs, GPUs and NPUs in a package to achieve performance requirements.

A Finnish company called Flow Computing is making some very bold claims when it comes to its new IP. The company has developed what it calls a Parallel Processing Unit or a PPU, which the company claims can boost the performance of any CPU by a hundred times its current performance. Furthermore, the company claims that its PPU can double the performance of any current code execution, with no need for any kind of optimisation for its PPU. The PPU can be integrated into new processors, but it can also be designed as a discrete chip that can be added to any current hardware and Flow Computing claims the performance benefits will be the same in both instances.

Flow Computing is a spinoff from the VTT Technical Research Centre of Finland and the company emerged from stealth mode last week with around €4 million in funding. Flow Computing doesn't intend to make its PPU by itself, but instead, the company wants to licence its tech to third parties, to give everyone an equal opportunity to take advantage of what's on offer. At this point in time, Flow Computing hasn't made any custom silicon, instead the company has validated its PPU using an FPGA tested against various Intel CPUs. As such, there are numbers to back up its claims and we've provided links below to a whitepaper and an FAQ for those that are interested in doing a deep dive into its claims. Flow Computing appears to have a few different implementations of its PPU, ranging from 16 to 256 cores, with the latter being for high-end computers, but the basic is said to be suitable for something as basic as a smartwatch. Time will tell if Flow Computing will be able to deliver on its claims and it'll be an interesting company to follow.

According to a report by KED Global, Korean chipmaking giant Samsung is ramping up its efforts to compete with global giants like TSMC and Intel. The latest partnership on the horizon is AMD's collaboration with Samsung. AMD is planning to utilize Samsung's cutting-edge 3 nm technology for its future chips. More specifically, AMD wants to utilize Samsung's gate-all-around FETs (GAAFETs). During ITF World 2024, AMD CEO Lisa Su noted that the company intends to use 3 nm GAA transistors for its future products. The only company offering GAAFETs on a 3 nm process is Samsung. Hence, this report from KED gains more credibility.

While we don't have any official information, AMD's utilization of a second foundry as a manufacturing partner would be a first for the company in years. This strategic move signifies a shift towards dual-sourcing, aiming to diversify its supply chain and reduce dependency on a single manufacturer, previously TSMC. We still don't know what specific AMD products will use GAAFETs. AMD could use them for CPUs, GPUs, DPUs, FPGAs, and even data center accelerators like Instinct MI series.

AMD today announced the expansion of the AMD Versal adaptive system on chip (SoC) portfolio with the new Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 adaptive SoCs, which bring preprocessing, AI inference, and postprocessing together in a single device for end-to-end acceleration of AI-driven embedded systems.

These initial devices in the Versal Series Gen 2 portfolio build on the first generation with powerful new AI Engines expected to deliver up to 3x higher TOPs-per-watt than first generation Versal AI Edge Series devicesi, while new high-performance integrated Arm CPUs are expected to offer up to 10x more scalar compute than first gen Versal AI Edge and Prime series devicesii.

At Embedded World 2024, Enclustra will showcase limitless potential to innovate the next big thing with over 20 FPGA (Field Programmable Gate Array) embedded system on module (SoM) technology solutions. Starting with unveiling Pluto, its tiny titan at 30 x 30 mm, the new coin-sized SoM with the strength of AMD Zynq UltraScale+ MPSoC, features ultra-compact embedded intelligence and portability, accelerating development of compact and portable low-power applications in industrial, healthcare, and security. Pluto's miniature form factor and high processing power are ideal for real-time video processing in medical smart glasses, VR, environmental monitoring, drones, autonomous navigation, and artificial intelligence inference.

"Enclustra leverages strategic partnerships with AMD, Altera and Microchip to provide customers with a comprehensive ecosystem of cutting-edge FPGA solutions optimized for performance and cost. We integrated their technology into our Pluto SoM, enabling unparalleled processing power and efficiency in a compact form factor," said Philipp Baechtold, CEO of Enclustra GmbH. "The future is bright for innovation with FPGA embedded chip technologies, creating life-saving, life-changing, and dream-making solutions."

AEWIN provides a series of performant Network Appliances and Edge Server powered by single AMD Zen 4c EPYC 8004 processor codenamed Siena. The latest AMD Siena CPU is produced with 5 nm manufacturing technology to have up to 64 cores (extreme density of 2CCX/CCD) and 225 W TDP with lower energy consumption compared to EPYC SP5. Siena SP6 CPU has the best performance per watt and is with the support of rich I/O and CXL 1.1.

SCB-1945 (1U) and SCB-1947A (2U) are two performant Network Appliances supporting 12x DDR5 sockets and 4x/8x PCIe Gen 5 slots for AEWIN self-design NICs with 1G to 100G copper/fiber interfaces (with/without bypass function) or other accelerators and NVMe SSDs. Both models provide the flexibility to change 2x front panel PCIe slots to 1x PCIe x16 slot for installing off-the-shelf add-on card for additional functions required. It can support 400G NIC card installed such as NVIDIA Mellanox PCIe 5.0 NIC.

Yesterday, AMD announced that its cutting-edge adaptive computing technology was selected by Sony Semiconductor Solutions (SSS) for its newest automotive LiDAR reference design. SSS, a global leader in image sensor technology, and AMD joined forces to deliver a powerful and efficient LiDAR solution for use in autonomous vehicles. Using adaptive computing technology from AMD significantly extends the SSS LiDAR system capabilities, offering extraordinary accuracy, fast data processing, and high reliability for next-generation autonomous driving solutions.

In the rapidly evolving landscape of autonomous driving, the demand for precise and reliable sensor technology has never been greater. LiDAR (Light Detection and Ranging) technology plays a pivotal role in enabling depth perception and environmental mapping for various industries. LiDAR delivers image classification, segmentation, and object detection data that is essential for 3D vision perception enhanced by AI, which cannot be provided by cameras alone, especially in low-light or inclement weather. The dedicated LiDAR reference design addresses the complexities of autonomous vehicle development with a standardized platform to enhance safety in navigating diverse driving scenarios.

During its 55th annual shareholders' meeting, Samsung Electronics announced its entry into the AI processor market with the upcoming launch of its Mach-1 AI accelerator chips in early 2025. The South Korean tech giant revealed its plans to compete with established players like NVIDIA in the rapidly growing AI hardware sector. The Mach-1 generation of chips is an application-specific integrated circuit (ASIC) design equipped with LPDDR memory that is envisioned to excel in edge computing applications. While Samsung does not aim to directly rival NVIDIA's ultra-high-end AI solutions like the H100, B100, or B200, the company's strategy focuses on carving out a niche in the market by offering unique features and performance enhancements at the edge, where low power and efficient computing is what matters the most.

According to SeDaily, the Mach-1 chips boast a groundbreaking feature that significantly reduces memory bandwidth requirements for inference to approximately 0.125x compared to existing designs, which is an 87.5% reduction. This innovation could give Samsung a competitive edge in terms of efficiency and cost-effectiveness. As the demand for AI-powered devices and services continues to soar, Samsung's foray into the AI chip market is expected to intensify competition and drive innovation in the industry. While NVIDIA currently holds a dominant position, Samsung's cutting-edge technology and access to advanced semiconductor manufacturing nodes could make it a formidable contender. The Mach-1 has been field-verified on an FPGA, while the final design is currently going through a physical design for SoC, which includes placement, routing, and other layout optimizations.

AMD today announced the AMD Spartan UltraScale+ FPGA family, the newest addition to the extensive portfolio of AMD Cost-Optimized FPGAs and adaptive SoCs. Delivering cost and power-efficient performance for a wide range of I/O-intensive applications at the edge, Spartan UltraScale+ devices offer the industry's highest I/O to logic cell ratio in FPGAs built in 28 nm and lower process technology, deliver up to 30 percent lower total power consumption versus the previous generation, and contain the most robust set of security features in the AMD Cost-Optimized Portfolio.

"For over 25 years the Spartan FPGA family has helped power some of humanity's finest achievements, from lifesaving automated defibrillators to the CERN particle accelerator advancing the boundaries of human knowledge," said Kirk Saban, corporate vice president, Adaptive and Embedded Computing Group, AMD. "Building on proven 16 nm technology, the Spartan UltraScale+ family's enhanced security and features, common design tools, and long product lifecycles further strengthen our market-leading FPGA portfolio and underscore our commitment to delivering cost-optimized products for customers."

Intel announced today that it is reviving the Altera brand name for its new standalone FPGA (field-programmable gate array) company. The business was previously known as Intel's Programmable Solutions Group before being spun off into an independent entity two months ago. The chipmaking giant acquired Altera in 2015 for $16.7 billion to bolster its FPGA capabilities. Using the well-known Altera moniker for the new standalone company signals Intel's confidence in the FPGA market opportunity, which it estimates to be over $55 billion across data centers, communications, and embedded segments. As a standalone company with its own board of directors, Altera will be able to focus exclusively on the FPGA market. Intel will remain a majority shareholder, but outside investment could help fund expansion plans.

Altera plans to build on the Programmable Solutions Group's recent efforts targeting lower-end and mid-range FPGAs for embedded devices in industrial, automotive and aerospace/defense applications. According to Intel CEO Pat Gelsinger, independence will give Altera "the mandate, focus and resources to better capitalize on the attractive expected growth of FPGAs." The revival of the Altera brand and refocus on the FPGA market comes alongside Intel's plan to invest heavily in new chip factories and advanced manufacturing capabilities. With Altera as a standalone business, Intel aims to be a significant player in the expected high growth of the global FPGA industry. Alongside new naming, Altera is introducing Agilex 9, which is now in volume production; Agilex 7 F-series and I-series released to production; Agilex 5 now broadly available, and Agilex 3 coming soon, with functions for cloud, communications and intelligent edge applications. Below, you can see the specification table of the upcoming FPGAs.

Tachyum today announced that it has added a Performance Monitoring Unit (PMU) to its Prodigy FPGA emulation system, empowering customers and partners with the ability to address bottlenecks and better optimize Prodigy performance for all applications and workloads. The PMU is an essential tool for collecting information about performance bottlenecks. It offers the ability to record a wide range of events that encompass every aspect of the Prodigy Universal Processor without slowing down the application itself. Tools like perf then present this information after the application is finished, enabling the identification and characterization of performance bottlenecks that may exist in the processor core, full mesh interconnect fabric, memory, and I/O subsystems. Perf is a go-to instrument for everybody working on performance assessment and tuning under Linux. The PMU's wide range of performance counters - supported by both software C-model and FPGA - facilitates both system debugging and performance tuning.

Tachyum's PMU enables faster time to market by allowing customers and partners to quickly identify performance issues and rapidly converge to a solution for all phases of go-to-market, including evaluation, development and final production testing. It provides an invaluable tool suite for customers spanning a broad array of markets, including AI, HPC and cloud computing.

AMD has quietly issued a product discontinuation notice—their PDF document is dated January 1 2024—for a whole bunch of Xilinx Complex Programmable Logic Device (CLPD) and lower-end FPGA models. Team Red's opening statement on the matter reads: "AMD will be discontinuing XC9500XL, CoolRunner XPLA 3, CoolRunner II, Spartan II, and Spartan 3, 3A, 3AN, 3E, 3ADSP Commercial/ Industrial "XC" and Automotive "XA" Product Families due to declining run-rate and supplier sustainability reasons." The American multinational semiconductor inherited a large back catalog of programmable logic products once their acquisition of Xilinx was completed back in 2022.

Industry analysts believed that this takeover was mainly motivated by a desire to expand into FPGA territories, although Team Red indicated that it would carry on producing and supporting Xilinx's older CLPD products—for example, the Spartan 3 family debuted back in 2011, while a couple of the CoolRunner II parts on the list are of 2002 vintage. AMD's discontinuation notice provides details of Last Time Buy (LTB) final orders—the cut-off date for soon-to-be-axed devices appears to be June 29 2024.

Naver, the firm behind the HyperCLOVA X large language model (LLM), has been working with Samsung Electronics toward the development of power-efficient AI accelerators. The collaboration brings Naver's expertise with Samsung's vast systems IP over silicon design, the ability to build complex SoCs, semiconductor fabrication, and its plethora of DRAM technologies. The two recently designed a proof of concept for an upcoming AI chip, which they iterated on an FPGA. Naver claims the AI chip it is co-developing with Samsung will be 8 times more energy efficient than an NVIDIA H100 AI accelerator, but did not elaborate on its actual throughput. Its solution, among other things, leverages energy-efficient LPDDR memory from Samsung. The two companies have been working on this project since December 2022.

Ayar Labs, a leader in silicon photonics for chip-to-chip connectivity, will showcase its in-package optical I/O solution integrated with Intel's industry-leading Agilex Field-Programmable Gate Array (FPGA) technology. In demonstrating 5x current industry bandwidth at 5x lower power and 20x lower latency, the optical FPGA - packaged in a common PCIe card form factor - has the potential to transform the high performance computing (HPC) landscape for data-intensive workloads such as generative artificial intelligence (AI), machine learning, and support novel new disaggregated compute and memory architectures and more.

"We're on the cusp of a new era in high performance computing as optical I/O becomes a 'must have' building block for meeting the exponentially growing, data-intensive demands of emerging technologies like generative AI," said Charles Wuischpard, CEO of Ayar Labs. "Showcasing the integration of Ayar Labs' silicon photonics and Intel's cutting-edge FPGA technology at Supercomputing is a concrete demonstration that optical I/O has the maturity and manufacturability needed to meet these critical demands."