China's domestic extreme ultraviolet (EUV) lithography development is far from a distant dream. The newest system, now undergoing testing at Huawei's Dongguan facility, leverages laser-induced discharge plasma (LDP) technology, representing a potentially disruptive approach to EUV light generation. The system is scheduled for trial production in Q3 2025, with mass manufacturing targeted for 2026, potentially positioning China to break ASML's technical monopoly in advanced lithography. The LDP approach employed in the Chinese system generates 13.5 nm EUV radiation by vaporizing tin between electrodes and converting it to plasma via high-voltage discharge, where electron-ion collisions produce the required wavelength. This methodology offers several technical advantages over ASML's laser-produced plasma (LPP) technique, including simplified architecture, reduced footprint, improved energy efficiency, and potentially lower production costs.

The LPP method relies on high-energy lasers and complex FPGA-based real-time control electronics to achieve the same result. While ASML has refined its LPP-based systems over decades, the inherent efficiency advantages of the LDP approach could accelerate China's catch-up timeline in this critical semiconductor manufacturing technology. When the US imposed sanctions on EUV shipments to Chinese companies, the Chinese semiconductor development was basically limited as standard deep ultraviolet (DUV) wave lithography systems utilize 248 nm (KrF) and 193 nm (ArF) wavelengths for semiconductor patterning, with 193 nm immersion technology representing the most advanced pre-EUV production technique. These longer wavelengths contrast with EUV's 13.5 nm radiation, requiring multiple patterning techniques to achieve advanced nodes.

Semiconductor intellectual property core provider CAST today announced a new IP core that implements the SNOW-V stream cipher algorithm to meet the security and performance demands of modern communication systems. Available now for ASICs or FPGAs, the company believes it to be the first such commercial IP core.

The new SNOW-V Stream Cipher Engine provides a flexible and reusable hardware implementation of the official SNOW-V mechanism as published in 2019 by the IACR Transactions on Symmetric Cryptology. SNOW-V revises the SNOW 3G stream cipher algorithm to help satisfy the high-speed, low-latency security requirements of 5G, 6G, and future mobile networks. The core:

Synopsys, Inc. today announced the expansion of its industry-leading hardware-assisted verification (HAV) portfolio with new HAPS prototyping and ZeBu emulation systems using the latest AMD Versal Premium VP1902 adaptive SoC. The next generation HAPS-200 prototyping and ZeBu-200 emulation systems deliver improved runtime performance, better compile time and improved debug productivity. They are built on new Synopsys Emulation and Prototyping (EP-Ready) Hardware that optimizes customer return on investment by enabling emulation and prototyping use cases via reconfiguration and optimized software. ZeBu Server 5 is enhanced to deliver industry-leading scalability beyond 60 billion gates (BG) to address the escalating hardware and software complexity in SoC and multi-die designs. It continues to offer industry-best density to optimize data center space utilization.

"With the industry approaching 100s of billions of gates per chip and 100s of millions of lines of software code in SoC and multi-die solutions, verification of advanced designs poses never-before seen challenges," said Ravi Subramanian, chief product management officer, Synopsys. "Continuing our strong partnership with AMD, our new systems deliver the highest HAV performance while offering the ultimate flexibility between prototyping and emulation use. Industry leaders are adopting Synopsys EP-Ready Hardware platforms for silicon to system verification and validation."

Report with market evolution powered by AI—The global artificial intelligence (AI) chips market size is estimated to grow by USD 902.6 billion from 2025-2029, according to Technavio. The market is estimated to grow at a CAGR of over 81.2% during the forecast period. Increased focus on developing AI chips for smartphones is driving market growth, with a trend towards convergence of AI and IoT. However, dearth of technically skilled workers for ai chips development poses a challenge. Key market players include Advanced Micro Devices Inc., Baidu Inc., Broadcom Inc., Cerebras, Fujitsu Ltd., Google LLC, Graphcore Ltd., Huawei Technologies Co. Ltd., Intel Corp., International Business Machines Corp., MediaTek Inc., Microchip Technology Inc., NVIDIA Corp., NXP Semiconductors NV, Qualcomm Inc., SambaNova Systems Inc., Samsung Electronics Co. Ltd., SenseTime Group Inc., Taiwan Semiconductor Manufacturing Co. Ltd., and Tesla Inc.

Recently, SpacemiT, a RISC-V AI CPU company from China, announced breakthrough progress in the development of its server CPU chip SpacemiT Vital Stone V100. It now provides a complete RISC-V CPU chip hardware and software platform that fully supports server specifications.

RISC-V CPU core X100, AIA and APLIC supporting interrupt virtualization, IOMMU supporting memory virtualization, IOPMP supporting security functions, LPC and eSPI supporting communication with mainstream BMCs, etc.

• The 64-bit server-grade RISC-V CPU core X100 delivers a single-core performance of >9 points/GHz on SPECINT2006 at 2.5 GHz 12 nm. X100 supports the RVA23 Profile, full virtualization (Hypervisor 1.0, AIA 1.0, IOMMU), RAS features, Vector 1.0 extension, vector encryption and decryption, security, 64-core interconnect, and more.
• The IOMMU IP adheres to the RISC-V IOMMU architecture specification and the AXI4-Stream DTI interface, supporting configurable DID, PID, virtual address, physical address width, and various levels of translation cache sizes. It can be flexibly integrated into different locations within the SoC bus system to enable distributed peripheral virtualization and accelerator acceleration.

Today, at Lattice Developers Conference 2024, Lattice Semiconductor expanded its edge to cloud FPGA innovation leadership with the launch of exciting new hardware and software solutions. The new Lattice Nexus 2 next-gen small FPGA platform and the first device family based on the platform, Lattice Certus -N2 general purpose FPGAs, offer advanced connectivity, optimized power and performance, and class-leading security. Lattice also announced new mid-range FPGA device capacity options - Lattice Avant 30 and Avant 50 - and new versions of Lattice design software tools and application-specific solution stacks to help accelerate customer time-to-market.

"At Lattice, we are proud to lead technological advancements in low power, small form factor FPGAs, ensuring our customers have the optimal devices, tools, and solutions to design groundbreaking applications that are power efficient, fast, and secure," said Esam Elashmawi, Chief Strategy and Marketing Officer, Lattice Semiconductor. "From the edge to the cloud across a variety of industries, FPGAs stand at the forefront of innovation, and we're committed to delivering versatile and robust small and mid-range FPGA solutions that enable our customers and partners to unlock their full potential."

AMD today announced the expansion of the AMD Versal adaptive system-on-chip (SoC) portfolio with the introduction of the Versal RF Series that includes the industry's highest compute performance in a single-chip device with integrated direct radio frequency (RF)-sampling data converters.

Versal RF Series offers precise, wideband-spectrum observability and up to 80 TOPS of digital signal processing (DSP) performance in a size, weight, and power (SWaP)-optimized design, targeting RF systems and test equipment applications in the aerospace and defense (A&D) and test and measurement (T&M) markets, respectively.

Intel Altera's FPGA unit is attracting a lot of attention in the semiconductor industry according to a recent report by Bloomberg, Lattice Semiconductor emerging as a potential buyer for the entire division. Bloomberg reports that Lattice actively works with advisers and seeks private-sector backing to support their bid. However, Intel's preference appears to be leaning toward selling only a small portion of its Altera shares instead of selling everything and this can be a decisive factor in upcoming negotiations. The potential sale has attracted interest from many outside Lattice Semiconductor, including major private equity firms such as Francisco Partners, Bain Capital, and Silver Lake Management. Qualcomm has also expressed interest in acquiring parts of Intel's design business.

Bloomberg also reports that selling just a portion of Altera's shares would likely require complex financial arrangements, while private equity firms are considering investing about $3 billion through instruments. This could result in Intel's valuation being lower than the original purchase price. Intel CEO Pat Gelsinger has indicated plans to close the Altera transaction in early 2024, with the company valuing the nearly $16.7 billion Intel paid for Altera in 2015 at approximately $17 billion. Lattice's market value of $7.48 billion is certainly smaller and can challenge Lattice's ambitions for complete control of Altera. The Intel board discussed Altera's future last week and prefers to sell only a minority stake, with a decision expected soon.

For over half a century, general-purpose processors have been built on the Tomasulo algorithm, developed by IBM engineer Robert Tomasulo in 1967. It's a $500B industry built on specialized CPU, GPU and other chips for different computing tasks. Hardware startup Ubitium has shattered this paradigm with a breakthrough universal processor that handles all computing workloads on a single, efficient chip - unlocking simpler, smarter, and more cost-effective devices across industries - while revolutionizing a 57-year-old industry standard.

Alongside this, Ubitium is announcing a $3.7 million in seed funding round, co-led by Runa Capital, Inflection, and KBC Focus Fund. The investment will be used to develop the first prototypes and prepare initial development kits for customers, with the first chips planned for 2026.

AMD on Tuesday released its flagship FPGA series, and possibly its most important product launch after the company's Xilinx acquisition, the Versal Premium Series Gen 2 SoC. It's hard to call this an FPGA, much in the same way as it's hard to call a modern processor "a CPU," there are many integrated devices, platform interfaces, and application-specific accelerators, and much in the same way, the Versal Premium Series Gen 2 is marketed as an "adaptive SoC," rather than a really powerful FPGA. Speaking of I/O, this is AMD's first product to implement PCI-Express Gen 6 and CXL 3.1.

There's no host platform that currently support these standards—neither EPYC "Turin" nor Xeon 6 "Granite Rapids," but it goes to show that the chip is future-ready and can put the new I/O standards to use. The chip is designed to be implemented as a standalone SoC, and so it supports both DDR5 RDIMMs and LPDDR5X, giving end-users the flexibility to go with the two vastly different memory standards depending on what their application is. These capabilities make the Versal Premium Series Gen 2 well-suited for demanding applications in sectors like data centers, communications, test and measurement, aerospace, and defense, where high-speed data processing is critical.

AMD today announced the AMD Alveo UL3422 accelerator card, the latest addition to its record-breaking family of accelerators1 designed for ultra-low latency electronic trading applications. AMD Alveo UL3422 provides trading firms, market makers and financial institutions with a slim form factor accelerator optimized for rack space, cost and designed for a fast path to deployment in a wide range of servers. The Alveo UL3422 accelerator is powered by an AMD Virtex UltraScale+ FPGA that features a novel transceiver architecture with hardened, optimized network connectivity cores, custom built for high-speed trading. It enables ultra-low latency trade execution, achieving less than 3ns FPGA transceiver latency and breakthrough 'tick-to-trade' performance not achievable with standard off-the-shelf FPGAs.

"Speed is the ultimate advantage in the increasingly competitive world of high-speed trading," said Yousef Khalilollahi, corporate vice president & general manager, Adaptive Computing Group, AMD. "The Alveo UL3422 card provides a lower-cost entry point while still delivering cutting-edge latency performance, making it accessible to firms of all sizes that want to stay competitive in the ultra-low latency trading space."

Jabil Inc. announced today that it is expanding its server portfolio with the J421E-S and J422-S servers, powered by AMD 5th Generation EPYC and Intel Xeon 6 processors. These servers are purpose-built for scalability in a variety of cloud data center applications, including AI, high-performance computing (HPC), fintech, networking, storage, databases, and security — representing the latest generation of server innovation from Jabil.

Built with customization and innovation in mind, the design-ready J422-S and J421E-S servers will allow engineering teams to meet customers' specific requirements. By fine-tuning Jabil's custom BIOS and BMC firmware, Jabil can create a competitive advantage for customers by developing the server configuration needed for higher performance, data management, and security. The server platforms are now available for sampling and will be in production by the first half of 2025.

Infineon Technologies AG today announced the addition of the EZ-USB FX20 programmable USB peripheral controller to its EZ-USB product family. It enables developers to create USB devices that meet the highest performance requirements in AI, image processing and emerging applications. The EZ-USB FX20 peripheral controller offers high-speed connectivity with USB 20 Gbps and LVDS interfaces, increasing the total bandwidth up to six times over its predecessor, the EZ-USB FX3.

"With the growing popularity of USB devices, the demand for compatible and adaptable USB controllers is increasing," said Ganesh Subramaniam, Senior Vice President and General Manager of the Wired Connectivity Solutions Product Line at Infineon. "Therefore, we are continuously improving the features and performance of our EZ-USB peripheral controllers and are pleased to support developers with our new addition to the product family, providing them with a flexible component to create powerful and advanced applications."

Altera, an Intel Company, today unveiled an array of FPGA hardware, software and development tools that make its programmable solutions more accessible across a broader range of use cases and markets. At its annual developer's conference, Altera revealed new details on its next-generation, power- and cost-optimized Agilex 3 FPGAs and announced new development kits and software support for its Agilex 5 FPGAs.

"Working closely with our ecosystem and distribution partners, Altera remains committed to delivering FPGA-based solutions that empower innovators with leading-edge programmable technologies that are easy to design and deploy. With these key announcements, we continue to execute on our vision of shaping the future by using programmable logic to help customers unlock greater value across a broad range of use cases within the data center, aerospace and defense sectors, communications infrastructure, automotive, industrial, test, medical and embedded markets," said Sandra Rivera, CEO of Altera.

Magewell's USB Capture family has long been the gold standard for professional video capture devices, earning a reputation for being the easiest and most reliable way to bring video and audio signals into software for live streaming, video conferencing, medical imaging and more. Magewell has expanded the renowned product line with the unveiling of a new model that captures video sources up to 4K resolution at 60 frames per second - the USB Capture HDMI 4K Pro. The new model will be demonstrated alongside other Magewell innovations in stand 7.A44 at the IBC2024 exhibition in Amsterdam from September 13 to 16.

Magewell's compact USB Capture devices enable computers including laptops to capture high-quality AV signals through a USB interface, with no additional power source required. The new USB Capture HDMI 4K Pro offers everything that users love about the existing USB Capture HDMI 4K Plus model, while leveraging 20 Gbps USB transfer performance on compatible host systems to enable the capture of 4K video at higher frame rates and color precision.

Intel is reportedly exploring the sale of its Altera business, a move guided by CEO Pat Gelsinger as part of broader restructuring efforts. Acquired by Intel in 2015 for $16.7 billion, Altera, formerly known as the Programmable Solutions Group, has been a profitable segment. However, with Intel facing financial strain due to extensive spending, the company is now considering divesting its FPGA business to recoup capital. Currently, Altera operates as a separate entity within Intel, relying on the tech giant for R&D, sales, marketing, and support. Gelsinger is expected to propose the sale at a board meeting scheduled for mid-September, where he will outline his vision for Intel's future. This restructuring could also affect other parts of Intel's operations, including its Foundry business.

While previous reports suggested that Intel might spin off its Foundry unit or sell it to industry leaders like TSMC or Samsung, the latest information indicates that Intel plans to retain this division, albeit with scaled-back expansion efforts. The $32 billion factory in Germany, for example, may be scrapped, along with other capital-intensive projects, and other capital expansions may also be put on hold. Pat Gelsinger's vision still needs to be finalized and is still in the drafting phase, so until the mid-September board meeting, we have to wait to gain more information.

Tachyum today announced the final build of its Prodigy FPGA emulation system in advance of chip production and general availability next year. As part of the announcement, the company is also ending its purchase program for prototype systems that was previously offered to commercial and federal customers.

These last hardware FPGA prototype units will ensure Tachyum hits its extreme-reliability test targets of more than 10 quadrillion cycles prior to tape-out and before the first Prodigy chips hit the market. Tachyum's software emulation system - and access to it - is expanding with additional availability of open-source software ported ahead of Prodigy's upstreaming.

According to sources close to Bloomberg, Intel plans to cut 10,000 jobs from its global workforce. The news comes amid heavy pressure on the semiconductor giant, which has been on a steady decline over the years, while other industry rivals like AMD and NVIDIA have been rising and taking market share in various areas from Intel. It is reported that Intel currently has 110,000 employees globally, and reducing the workforce by 10,000 would net Intel around 100,000 global employees left. These figures exclude employees from spun-out units like Altera FPGA company, which is under Intel's ownership. Intel's aim to reduce its workforce is expected to come with a significant cost benefit to the company, with projected savings of $10 billion by 2025.

The news isn't yet official, but it is expected to see the light of the day as soon as this week. As Intel's CEO Pat Gelsinger invests heavily into the fab construction and development of next-generation products, there have been a few notes that Intel would have to overcome some challenges shortly to reach its long-term goals like more advanced silicon manufacturing facilities and new products for AI/HPC and client sector. One of those short-term measures is reducing the workforce to cut down expenses. Intel has reduced its workforce before. In 2022, the company announced reduced spending in non-critical areas and reducing the workforce, and in 2023, cut the workforce by 5% to 124,800 employees last year, only to be left with 110,000 employees in 2024.

MaxLinear, Inc., a leading provider of data storage acceleration solutions for enterprise and data center applications, today announced it will demonstrate the advanced compression, encryption, and security performance of its storage acceleration solution, Panther III, at the Future of Memory and Storage (FMS) 2024 trade show from August 6-8, 2024. The demos will show that Panther III can achieve up to 40 times more throughput, up to 190 times better latency, and up to 1000 times less CPU utilization than a software-only solution, leading to significant cost savings in terms of flash drives and needed CPU cores.

MaxLinear's Panther III creates a bold new product category for maximizing the performance of data storage systems - a comprehensive, all-in-one "storage accelerator." Unlike encryption and/or compression solutions, MaxLinear's Panther III consolidates a comprehensive suite of storage acceleration functions, including compression, deduplication, encryption, data protection, and real-time validation, in a single hardware-based solution. Panther III is engineered to offload and expedite specific data processing tasks, thus providing a significant performance boost, storage cost savings, and energy savings compared to traditional software-only, FPGA, and other competitive solutions.

Lattice Semiconductor, the low power programmable leader, today announced the addition of new, logic-optimized Lattice Certus -NX FPGA devices to its leadership small FPGA portfolio. The new offering includes two new capacity points, the Certus -NX-28 and Certus -NX-09, and multiple package options that offer class-leading power efficiency, small size, and reliability with flexible migration options. These devices are designed to accelerate a broad range of Communications, Computing, Industrial, and Automotive applications.

"Lattice is committed to delivering continued innovation in small, low power FPGAs to empower our customers with optimized solutions for space-constrained applications ranging from sensor interfacing to co-processing to low power AI," said Dan Mansur, Corporate Vice President, Product Marketing, Lattice Semiconductor. "We're excited to expand our Nexus-based small FPGA offerings by adding more migratable logic and package options including 0.8 mm pitch, ideal for Industrial applications."

TrendForce's latest industry report on AI servers reveals that high demand for advanced AI servers from major CSPs and brand clients is expected to continue in 2024. Meanwhile, TSMC, SK hynix, Samsung, and Micron's gradual production expansion has significantly eased shortages in 2Q24. Consequently, the lead time for NVIDIA's flagship H100 solution has decreased from the previous 40-50 weeks to less than 16 weeks.

TrendForce estimates that AI server shipments in the second quarter will increase by nearly 20% QoQ, and has revised the annual shipment forecast up to 1.67 million units—marking a 41.5% YoY growth.

Today marks a new milestone in the growth of Intel Foundry's design ecosystem as key partners Ansys, Cadence, Siemens, and Synopsys have announced the availability of reference flows for Intel's embedded multi-die interconnect bridge (EMIB) advanced packaging technology. This comes on the heels of recent announcements where those same partners declared readiness for Intel 18A designs. "Today's news shows how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI systems ambitions," said Suk Lee, vice president for Ecosystem Development, Intel Foundry.

The success of Intel Foundry is rooted in collaboration with a vibrant design ecosystem. This ensures customers can access our leading process and packaging technologies. Now, in collaboration with our ecosystem partners, we are making it as easy and as fast as possible for companies to optimize, fabricate and assemble their system-on-chip designs through our foundries, while enabling their designers with validated EDA tools, design flows and IP portfolios for silicon-through-package design. This systems foundry approach allows our customers to innovate at every layer of the stack so they can meet the complex computing demands of the AI era, where chip architectures increasingly rely on multiple CPUs, GPUs and NPUs in a package to achieve performance requirements.

A Finnish company called Flow Computing is making some very bold claims when it comes to its new IP. The company has developed what it calls a Parallel Processing Unit or a PPU, which the company claims can boost the performance of any CPU by a hundred times its current performance. Furthermore, the company claims that its PPU can double the performance of any current code execution, with no need for any kind of optimisation for its PPU. The PPU can be integrated into new processors, but it can also be designed as a discrete chip that can be added to any current hardware and Flow Computing claims the performance benefits will be the same in both instances.

Flow Computing is a spinoff from the VTT Technical Research Centre of Finland and the company emerged from stealth mode last week with around €4 million in funding. Flow Computing doesn't intend to make its PPU by itself, but instead, the company wants to licence its tech to third parties, to give everyone an equal opportunity to take advantage of what's on offer. At this point in time, Flow Computing hasn't made any custom silicon, instead the company has validated its PPU using an FPGA tested against various Intel CPUs. As such, there are numbers to back up its claims and we've provided links below to a whitepaper and an FAQ for those that are interested in doing a deep dive into its claims. Flow Computing appears to have a few different implementations of its PPU, ranging from 16 to 256 cores, with the latter being for high-end computers, but the basic is said to be suitable for something as basic as a smartwatch. Time will tell if Flow Computing will be able to deliver on its claims and it'll be an interesting company to follow.

According to a report by KED Global, Korean chipmaking giant Samsung is ramping up its efforts to compete with global giants like TSMC and Intel. The latest partnership on the horizon is AMD's collaboration with Samsung. AMD is planning to utilize Samsung's cutting-edge 3 nm technology for its future chips. More specifically, AMD wants to utilize Samsung's gate-all-around FETs (GAAFETs). During ITF World 2024, AMD CEO Lisa Su noted that the company intends to use 3 nm GAA transistors for its future products. The only company offering GAAFETs on a 3 nm process is Samsung. Hence, this report from KED gains more credibility.

While we don't have any official information, AMD's utilization of a second foundry as a manufacturing partner would be a first for the company in years. This strategic move signifies a shift towards dual-sourcing, aiming to diversify its supply chain and reduce dependency on a single manufacturer, previously TSMC. We still don't know what specific AMD products will use GAAFETs. AMD could use them for CPUs, GPUs, DPUs, FPGAs, and even data center accelerators like Instinct MI series.

AMD today announced the expansion of the AMD Versal adaptive system on chip (SoC) portfolio with the new Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 adaptive SoCs, which bring preprocessing, AI inference, and postprocessing together in a single device for end-to-end acceleration of AI-driven embedded systems.

These initial devices in the Versal Series Gen 2 portfolio build on the first generation with powerful new AI Engines expected to deliver up to 3x higher TOPs-per-watt than first generation Versal AI Edge Series devicesi, while new high-performance integrated Arm CPUs are expected to offer up to 10x more scalar compute than first gen Versal AI Edge and Prime series devicesii.