AMD has applied for a United States Patent that describes a CPU design with FPGA (Field-Programmable Gate Array) elements integrated into its core design. Titled "Method and Apparatus for Efficient Programmable Instructions in Computer Systems", the patent application describes a CPU with FPGA elements inscribed into its very core design, where the FPGA elements actually share CPU resources such as registers for floating-point and integer execution units. This patent undoubtedly comes in the wake of AMD's announced Xilinx acquisition plans, and brings FPGA and CPU marriages to a whole other level. FPGA,as the name implies, are hardware constructions which can reconfigure themselves according to predetermined tables (which can also be updated) to execute desired and specific functions.

Intel have themselves already shipped a CPU + FPGA combo in the same package; the company's Xeon 6138P, for example, includes an Arria 10 GX 1150 FPGA on-package, offering 1,150,000 logic elements. However, this is simply a CPU + FPGA combo on the same substrate; not a native, core-integrated FPGA design. Intel's product has severe performance and latency penalties due to the fact that complex operations performed in the FPGA have to be brought out of the CPU, processed in the FPGA, and then its results have to be returned to the CPU. AMD's design effectively ditches that particular roundabout, and should thus allow for much higher performance.

Tachyum Inc. today announced that it is signing early adopter customers for the software emulation system for its Prodigy Universal Processor, customers may begin the process of native software development (i.e. using Prodigy Instruction Set Architecture) and porting applications to run on Prodigy. Prodigy software emulation systems will be available at the end of January 2021.

Customers and partners can use Prodigy's software emulation for evaluation, development and debug, and with it, they can begin to transition existing applications that demand high performance and low power to run optimally on Prodigy processors. Pre-built systems include a Prodigy emulator, native Linux, toolchains, compilers, user mode applications, x86, ARM and RISC-V emulators. Software updates will be issued as needed.

Today at AWS re:Invent 2020, AWS CEO Andy Jassy announced EC2 instances that will leverage up to eight Habana Gaudi accelerators and deliver up to 40% better price performance than current graphics processing unit-based EC2 instances for machine learning workloads. Gaudi accelerators are specifically designed for training deep learning models for workloads that include natural language processing, object detection and machine learning training, classification, recommendation and personalization.

"We are proud that AWS has chosen Habana Gaudi processors for its forthcoming EC2 training instances. The Habana team looks forward to our continued collaboration with AWS to deliver on a roadmap that will provide customers with continuity and advances over time." -David Dahan, chief executive officer at Habana Labs, an Intel Company.

BittWare, a Molex company, today unveiled the IA-840F, the company's first Intel Agilex -based FPGA card designed to deliver significant performance-per-watt improvements for next-generation data center, networking and edge compute workloads. Agilex FPGAs deliver up to 40% higher performance or up to 40% lower power, depending on application requirements. BittWare maximized I/O features using the Agilex chip's unique tiling architecture with dual QSFP-DDs (4× 100G), PCIe Gen4 x16, and three MCIO expansion ports for diverse applications. BittWare also announced support for Intel oneAPI, which enables an abstracted development flow for dramatically simplified code re-use across multiple architectures.

"Modern data center workloads are incredibly diverse, requiring customers to implement a mix of scalar, vector, matrix and spatial architectures," said Craig Petrie, vice president of marketing for BittWare. "The IA-840F ensures that customers can quickly and easily exploit the advanced features of the Intel Agilex FPGA. For those customers who prefer to develop FPGA applications at an abstracted level, we are including support for oneAPI. This new unified software programming environment allows customers to program the Agilex FPGA from a single code base with native high-level language performance across architectures."

Intel continues to "shed fat" on its business portfolio. After last year's sale of its smartphone modem chip business to Apple, the company is now parting ways with its power management circuitry division - Enpirion - and offloading it to Richtek, a division of Taiwanese MediaTek. The sale price of $85 million is a drop in the bucket for Intel's overall bottom line, so it's not a way for the company to cash in some desperately needed money - all accounts of Intel's troubles in the wake of its semiconductor manufacturing issues and AMD's market resurgence pale in comparison to Intel's revenues.

This actually looks like a company that's actually streamlining its R&D expenditures and focusing on execution for the markets Intel sees as most important for today and for tomorrow. Intel's Enpirion focuses on building power management chips for FPGA circuits, SoCs, CPUs, and ASICs, and will now serve to bolster MediaTek's SoC business while allowing the Taiwanese company to expand and diversify its business portfolio, even as Intel focuses on their core competencies.

Intel and Argonne National Laboratory are collaborating on the co-design and validation of exascale-class applications using graphics processing units (GPUs) based on Intel Xe-HP microarchitecture and Intel oneAPI toolkits. Developers at Argonne are tapping into Intel's latest programming environments for heterogeneous computing to ensure scientific applications are ready for the scale and architecture of the Aurora supercomputer at deployment.

"Our close collaboration with Argonne is enabling us to make tremendous progress on Aurora, as we seek to bring exascale leadership to the United States. Providing developers early access to hardware and software environments will help us jumpstart the path toward exascale so that researchers can quickly start taking advantage of the system's massive computational resources." -Trish Damkroger, Intel vice president and general manager of High Performance Computing.

Xilinx, Inc. and Samsung Electronics Co., Ltd. today announced the availability of the Samsung SmartSSD Computational Storage Drive (CSD). Powered by Xilinx FPGAs, the SmartSSD CSD is the industry's first adaptable computational storage platform providing the performance, customization, and scalability required by data-intensive applications.

Xilinx will showcase the SmartSSD CSD and partner solutions at the Flash Memory Summit Virtual Conference and Expo taking place November 10-12. The SmartSSD CSD is a flexible, programmable storage platform that developers can use to create a variety of unique and scalable accelerators that solve a broad range of data center problems. It empowers a new breed of software developers to easily build innovative hardware-accelerated solutions in familiar high-level languages. The SmartSSD CSD accelerates data processing performance by 10x or more for applications such as database management, video processing, artificial intelligence layers, complex search, and virtualization.

Intel today unveiled the suite of new security features for the upcoming 3rd generation Intel Xeon Scalable platform, code-named "Ice Lake." Intel is doubling down on its Security First Pledge, bringing its pioneering and proven Intel Software Guard Extension (Intel SGX) to the full spectrum of Ice Lake platforms, along with new features that include Intel Total Memory Encryption (Intel TME), Intel Platform Firmware Resilience (Intel PFR) and new cryptographic accelerators to strengthen the platform and improve the overall confidentiality and integrity of data.

Data is a critical asset both in terms of the business value it may yield and the personal information that must be protected, so cybersecurity is a top concern. The security features in Ice Lake enable Intel's customers to develop solutions that help improve their security posture and reduce risks related to privacy and compliance, such as regulated data in financial services and healthcare.

AMD is planning to enter the FPGA market by buying out one of Intel's largest competitors, Xilinx. The Wall Street Journal reports that AMD is in "advanced talks" to acquire the San Jose-based firm which specializes in FPGAs of all shapes and sizes, including large, high logic cell-count FPGAs under the Virtex UltraScale brand, the main competitor to Intel's Stratix 10. Xilinx is valued at $26 billion, although analysts estimate the AMD acquisition to go down at close to $30 billion, making it one of the largest tech acquisitions of the year, after NVIDIA's buyout of Arm from Softbank. An FPGA lineup would give AMD a near complete portfolio of computing hardware IP: CPUs with x86 and Arm licenses, GPUs, GPU-based scalar compute processors, semi-custom SoCs, low-power media processors, and now FPGA.

Intel Corp. and Lightbits Labs today announced an agreement to propel development of disaggregated storage solutions to solve the challenges of today's data center operators who are craving improved total-cost-of-ownership (TCO) due to stranded disk capacity and performance. This strategic partnership includes technical co-engineering, go-to-market collaboration and an Intel Capital investment in Lightbits Labs. Lightbits' LightOS product delivers high-performance shared storage across servers while providing high availability and read-and-write management designed to maximize the value of flash-based storage. LightOS, while being fully optimized for Intel hardware, provides customers with vastly improved storage efficiency and reduces underutilization while maintaining compatibility with existing infrastructure without compromising performance and simplicity.

Lightbits Labs will enhance its composable disaggregated software-defined storage solution, LightOS, for Intel technologies, creating an optimized software and hardware solution. The system will utilize Intel Optane persistent memory and Intel 3D NAND SSDs based on Intel QLC Technology, Intel Xeon Scalable processors with unique built-in artificial intelligence (AI) acceleration capabilities and Intel Ethernet 800 Series Network Adapters with Application Device Queues (ADQ) technology. Intel's leadership FPGAs for next-generation performance, flexibility and programmability will complement the solution.

SiliconArts today released RC-MC, its next generation RayCore graphics architecture. The RayCore MC is scalable and modular to enable integration on a wide variety of gaming platforms including cloud, desktop, mobile, console and VR/AR. The RC-MC is being made available in an external Graphics Accelerator (eGFX) for content developers and SOC design evaluation.

Jon Peddie, principle and founder of Jon Peddie Research, says of the RayCore MC product release: "SiliconArts' latest product breaks another barrier between the professional rendering and the broader graphics market, with path tracing features such as global illumination and soft shadows that are being deployed in advanced rendering farms today."

Magewell - the award-winning developer of innovative video interface and IP workflow solutions - today announced the sixth model in its Eco Capture family of ultra-compact, power-efficient, M.2 video capture cards. Providing input signal compatibility for older 4K source equipment, the Eco Capture QL-SDI 4K M.2 captures one channel of video - with embedded audio - up to 4096x2160 at 60 frames per second over quad-link, 3G-SDI connectivity.

Magewell's Eco Capture cards offer systems integrators and OEM developers high-performance video capture with low power consumption in a space-efficient form factor. The cost-effective, low-latency devices feature a high-speed PCIe 2.0 bus interface with an M.2 connector and measure only 22x80mm (0.87x3.15 in), making them perfect for use in small or portable systems where full-sized PCIe slots are not available.

Lattice Semiconductor Corporation, the low power programmable leader, today launched the new Lattice Certus -NX family of FPGAs. The devices lead the general-purpose FPGA market in I/O density, delivering up to twice the I/O density per mm2 in comparison to similar competing FPGAs, and provide best-in-class power savings, small size, reliability, instant-on performance, and support fast PCI Express (PCIe) and Gigabit Ethernet interfaces to enable data co-processing, signal bridging, and system control. Certus-NX FPGAs target a range of applications, from data processing in automated industrial equipment to system management in communications infrastructure. The Certus-NX devices are the second family of FPGAs developed on the Lattice Nexus platform, the industry's first low power FPGA platform using 28 nm FD-SOI process technology. With the launch of Certus-NX, Lattice marks the release of the second device family developed under Lattice's new product development strategy in just six months.

"Certus-NX delivers unique and innovative capabilities that set it apart," said Linley Gwennap, Principal Analyst at The Linley Group. "Compared to competing FPGAs of similar gate counts, Lattice offers a much smaller package, greater I/O density, and lower power."

Today, The Khronos Group, an open consortium of industry-leading companies creating graphics and compute interoperability standards, announces the ratification and public release of the SYCL 2020 Provisional Specification. SYCL is a standard C++ based heterogeneous parallel programming framework for accelerating High Performance Computing (HPC), machine learning, embedded computing, and compute-intensive desktop applications on a wide range of processor architectures, including CPUs, GPUs, FPGAs, and AI processors.The SYCL 2020 Provisional Specification is publicly available today to enable feedback from developers and implementers before the eventual specification finalization and release of the SYCL 2020 Adopters Program, which will enable implementers to be officially conformant—tentatively expected by the end of the year.

A royalty-free open standard, SYCL 2020 enables significant programmer productivity through an expressive domain-specific language, compact code, and simplified common patterns, such as Class Template Argument Deduction and Deduction Guides, all while preserving significant backwards compatibility with previous versions. SYCL 2020 is based on C++17 and includes new programming abstractions, such as unified shared memory, reductions, group algorithms, and sub-groups to enable high-performance applications across diverse hardware architectures.

Intel today introduced its 3rd Gen Intel Xeon Scalable processors and additions to its hardware and software AI portfolio, enabling customers to accelerate the development and use of AI and analytics workloads running in data center, network and intelligent-edge environments. As the industry's first mainstream server processor with built-in bfloat16 support, Intel's new 3rd Gen Xeon Scalable processors makes artificial intelligence (AI) inference and training more widely deployable on general-purpose CPUs for applications that include image classification, recommendation engines, speech recognition and language modeling.

"The ability to rapidly deploy AI and data analytics is essential for today's businesses. We remain committed to enhancing built-in AI acceleration and software optimizations within the processor that powers the world's data center and edge solutions, as well as delivering an unmatched silicon foundation to unleash insight from data," said Lisa Spelman, Intel corporate vice president and general manager, Xeon and Memory Group.

Xilinx, Inc., the leader in adaptive and intelligent computing, today introduced two real-time computing video appliances for easy-to-scale, ultra-high-density video transcoding applications. Based on the new Xilinx Real-Time (RT) Server reference architecture, these new appliances will enable service providers delivering applications such as eSports and game streaming platforms, social and video conferencing, live distance learning, telemedicine and live broadcast video to optimize video quality and bitrate at the lowest cost per channel for significant TCO savings over both software-based and fixed-architecture approaches.

Designed for edge and on-premise compute-intensive workloads where video channel density, throughput and latency are critical requirements, the new Xilinx Real-Time Video Appliances feature optimized hardware architectures and software to deliver the industry's highest channel density and lowest latency performance. The appliances are available in two pre-configured options integrating Xilinx Alveo data center accelerator cards - the High Channel Density Video Appliance and the Ultra-Low Bitrate Video Appliance.

Teledyne e2v has announced the DDR4T04G72M - the first radiation-tolerant DDR4 memory chip, featuring a total 4 GB capacity. Currently validated at 2133 MT/s, and targeting to offer 2400MT/s in the near future, this next-generation solution offers ultra-responsive low latency operation, while fitting into a highly compact form factor. Furthermore, high-reliability manufacturing and radiation-tolerant robustness makes it highly suitable for dealing with the rigors of space environments.

With 15 mm x 20 mm x 1.92 mm dimensions, this new space-grade device comprises an array of Micron based memory chips, integrated in a single package. It features a 72-bit bus, where 64 bits are dedicated to data and 8 bits to error correction code (ECC). Radiation tests have been performed on these memory chips and a single event effects (SEE) report is available from Teledyne e2v. In particular, the memory has been demonstrated to be single event latch-up (SEL) free up to 60+ MeV.cm²/mg.

Xilinx, Inc., the leader in adaptive and intelligent computing, today announced the industry's first 20-nanometer (nm) space-grade FPGA, delivering full radiation tolerance and ultra-high throughput and bandwidth performance for satellite and space applications. The new 20 nm Radiation Tolerant (RT) Kintex UltraScale XQRKU060 FPGA provides true unlimited on-orbit reconfiguration, over a 10x increase in digital signal processing (DSP) performance - ideal for payload applications - and full radiation tolerance across all orbits.

The XQRKU060 also brings high performance machine learning (ML) to space for the first time. A diverse portfolio of ML development tools supporting industry standard frameworks, including TensorFlow and PyTorch, enable neural network inference acceleration for real-time on-board processing in space with a complete "process and analyze" solution. The XQRKU060's dense, power-efficient compute with scalable precision and large on-chip memory, provides 5.7 tera operations per second (TOPs) of peak INT8 performance optimized for deep learning, a nearly 25X increase compared to the prior generation.

Today, Intel is pledging an additional $50 million in a pandemic response technology initiative to combat the coronavirus through accelerating access to technology at the point of patient care, speeding scientific research and ensuring access to online learning for students. Included in Intel's effort is an additional innovation fund for requests where access to Intel expertise and resources can have immediate impact. This is in addition to prior announcements of $10 million in donations that are supporting local communities during this critical time.

The world faces an enormous challenge in fighting COVID-19. Intel is committed to accelerating access to technology that can combat the current pandemic and enable new technology and scientific discovery that better prepares society for future crises. We hope that by sharing our expertise, resources and technology, we can help to accelerate work that saves lives and expands access to critical services around the world during this challenging time," said Bob Swan, Intel chief executive officer.

Xilinx, Inc. today announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry's highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the industry's first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.

Xperi Corporation today announced that it entered into a new patent and technology license agreement with SK hynix, one of the world's largest semiconductor manufacturers. The agreement includes access to Xperi's broad portfolio of semiconductor intellectual property (IP) and a technology transfer of Invensas DBI Ultra 3D interconnect technology focused on next-generation memory.

"We are delighted to announce the extension of our long-standing relationship with SK hynix, a world-renowned technology leader and manufacturer of memory solutions," said Craig Mitchell, President of Invensas, a wholly owned subsidiary of Xperi Corporation. "As the industry increasingly looks beyond conventional node scaling and turns toward hybrid bonding, Invensas stands as a pioneering leader that continues to deliver improved performance, power, and functionality, while also reducing the cost of semiconductors. We are proud to partner with SK hynix to further develop and commercialize our DBI Ultra technology and look forward to a wide range of memory solutions that leverage the benefits of this revolutionary technology platform."

CHIPS Alliance, the leading consortium advancing common and open hardware for interfaces, processors and systems, today announced industry leading chipmaker Intel as its newest member. Intel is contributing the Advanced Interface Bus (AIB) to CHIPS Alliance to foster broad adoption.

CHIPS Alliance is hosted by the Linux Foundation to foster a collaborative environment to accelerate the creation and deployment of open SoCs, peripherals and software tools for use in mobile, computing, consumer electronics and Internet of Things (IoT) applications. The CHIPS Alliance project develops high-quality open source Register Transfer Level (RTL) code and software development tools relevant to the design of open source CPUs, SoCs, and complex peripherals for Field Programmable Gate Arrays (FPGAs) and custom silicon.

At Supercomputing 2019, Intel unveiled its vision for extending its leadership in the convergence of high-performance computing (HPC) and artificial intelligence (AI) with new additions to its data-centric silicon portfolio and an ambitious new software initiative that represents a paradigm shift from today's single-architecture, single-vendor programming models.

Addressing the increasing use of heterogeneous architectures in high-performance computing, Intel expanded on its existing technology portfolio to move, store and process data more effectively by announcing a new category of discrete general-purpose GPUs optimized for AI and HPC convergence. Intel also launched the oneAPI industry initiative to deliver a unified and simplified programming model for application development across heterogenous processing architectures, including CPUs, GPUs, FPGAs and other accelerators. The launch of oneAPI represents millions of Intel engineering hours in software development and marks a game-changing evolution from today's limiting, proprietary programming approaches to an open standards-based model for cross-architecture developer engagement and innovation.

Intel has today announced the Stratix 10 GX 10M - a Field Programmable Gate Array (FPGA) built on 14 nm technology that has an astonishing 43.3 Billion transistors, making it the largest FPGA in the world, dethroning the Xilinx with their previously largest Virtex VU19P FPGA which had a "mere" 35 Billion transistors. The Stratix 10 GX 10M is a home to over 10.2 million logic cells housed inside two large dies, connected by Intel's own Embedded Multi-die Interconnect Bridge (EMIB).

The 10M model is packing four additional dies besides the two for logic, also connected by EMIB, that feature 48 transceivers in total which have a combined bandwidth of up to 4.5Tb/s. If you are wondering about the bandwidth between all dies, then judging by EMIB's 25,920 connections, there is 6.5 Tb/s of inner-die bandwidth, meaning that components will not be starving for additional speeds to transfer the data. Additionally there are 2,304 user I/O pins, allowing for some creative integration solutions that involve plenty of ports for development purposes.

Intel today announced shipments of new Intel Stratix 10 DX field programmable gate arrays (FPGA). The new FPGAs are designed to support Intel Ultra Path Interconnect (Intel UPI), PCI-Express (PCIe) Gen4 x16 and a new controller for Intel Optane technology to provide flexible, high-performance acceleration. VMware is one of many early access program participants.

"Intel Stratix 10 DX FPGAs are the first FPGAs designed to combine key features that dramatically boost acceleration of workloads in the cloud and enterprise when used with Intel's portfolio of data center solutions. No other FPGA currently offers this combination of features for server designs based on future select Intel Xeon Scalable processors," said David Moore, Intel vice president and general manager, FPGA and Power Products, Network and Custom Logic Group.