Intel is making progress in its development of a new discrete GPU architecture, after its failed attempt with "Larrabee" that ended up as an HPC accelerator; and ancient attempts such as the i740. This comes in the wake of the company's high-profile hiring of Raja Koduri, AMD's former Radeon Technologies Group (RTG) head. The company unveiled slides pointing to the direction in which its GPU development is headed, at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco. That direction is essentially scaling up its existing iGPU architecture, and bolstering it with mechanisms to sustain high clock speeds better.

The company's first 14 nm dGPU prototype, shown as a test-chip at the ISSCC, is a 2-chip solution. The first chip contains two key components, the GPU itself, and a system agent; and the second chip is an FPGA that interfaces with the system bus. The GPU component, as it stands now, is based on Intel's Gen 9 architecture, and features a three execution unit (EU) clusters. Don't derive numbers from this yet, as Intel is only trying to demonstrate a proof of concept. The three clusters are wired to a sophisticated power/clock management mechanism that efficiently manages power and clock-speed of each individual EU. There's also a double-clock mechanism that doubles clock speeds (of the boost state) beyond what today's Gen 9 EUs can handle on Intel iGPUs. Once a suitable level of energy efficiency is achieved, Intel will use newer generations of EUs, and scale up EU counts taking advantage of newer fab processes, to develop bigger discrete GPUs.More slides follow.

Intel today announced the availability of the Intel Stratix 10 MX FPGA, the industry's first field programmable gate array (FPGA) with integrated High Bandwidth Memory DRAM (HBM2). By integrating the FPGA and the HBM2, Intel Stratix 10 MX FPGAs offer up to 10 times the memory bandwidth when compared with standalone DDR memory solutions1. These bandwidth capabilities make Intel Stratix 10 MX FPGAs the essential multi-function accelerators for high-performance computing (HPC), data centers, network functions virtualization (NFV), and broadcast applications that require hardware accelerators to speed-up mass data movements and stream data pipeline frameworks.

In HPC environments, the ability to compress and decompress data before or after mass data movements is paramount. HBM2-based FPGAs can compress and accelerate larger data movements compared with stand-alone FPGAs. With High Performance Data Analytics (HPDA) environments, streaming data pipeline frameworks like Apache Kafka and Apache Spark Streaming require real-time hardware acceleration. Intel Stratix 10 MX FPGAs can simultaneously read/write data and encrypt/decrypt data in real-time without burdening the host CPU resources.

Fujitsu Laboratories Ltd. today announced the development of WAN acceleration technology that can deliver transfer speeds up to 40Gbps for migration of large volumes of data between clouds, using servers equipped with field-programmable gate arrays (FPGAs).

Connections in wide area networks (WANs) between clouds are moving from 1Gbps lines to 10Gbps lines, but with the recent advance of digital technology, including IoT and AI, there is an even greater demand for faster high-speed data transfers as huge volumes of data are collected in the cloud. Until now the effective transfer speed of WAN connections has been raised using techniques to reduce the volume of data, such as compression and deduplication. However, with WAN lines of 10Gbps there are enormous volumes of data to be processed, and existing WAN acceleration technologies usable in cloud servers have not been able to sufficiently raise the effective transfer rate.

Intel Corporation today reported third-quarter 2017 financial results. "We executed well in the third quarter with strong results across the business, and we're on track to a record year," said Brian Krzanich, Intel CEO. "I'm excited about our progress and our future. Intel's product line-up is the strongest it has ever been with more innovation on the way for artificial intelligence, autonomous driving and more." "In the third quarter, we delivered record earnings, exceeded our EPS expectations, and increased our profit expectations for the full year," said Bob Swan, Intel CFO. "We feel great about Intel's transformation and where we are nine months into our three year plan." In the third quarter, the company generated approximately $6.3 billion in cash from operations, paid dividends of $1.3 billion, and used $1.1 billion to repurchase 31 million shares of stock.

In the third quarter, Intel saw strength across the business. The data center, Internet of Things and memory businesses all achieved record quarterly revenue, and Intel extended its performance leadership with the launches of 8th Gen Intel Core and Intel Xeon Scalable processors. Intel's FPGA business, the Programmable Solutions Group, is experiencing strong momentum, winning designs with automotive and cloud service provider customers that advance Intel's position in artificial intelligence. The company also furthered its autonomous driving efforts with exciting customer wins and the completion of the Mobileye tender offer, four months earlier than expected.

Intel today announced it has begun shipping its Intel Stratix 10 SX FPGA - the only high-end FPGA family with an integrated quad-core ARM* Cortex*-A53 processor. With densities greater than 1 million logic elements (MLE), Intel Stratix 10 SX FPGAs provide the flexibility and low latency benefit of integrating an ARM processor with a high-performance, high-density FPGA needed to tackle the design challenges of next-generation, high-performance systems.

By integrating the FPGA and the ARM processor, Intel Stratix 10 SX FPGAs provide an ideal solution for 5G wireless communication, software defined radios, secure computing for military applications, network function virtualization (NFV) and data center acceleration.

Intel is undoubtedly at the forefront of silicon processing technology these days, and has been for a long time. Being a fully integrated company from the bottom up, through the design and actual production of its silicon semiconductors, really does have a way of either paying of tremendously (as has been the case with Intel), or not at all (as was the case with AMD). That fabrication processes' nm ratings don't mean much in thhe industry right now has been the case for a while now; different companies use different calculations towards achieving a 22 nm or 14 nm claim, with some components in the same nm process having almost double the size of the same components in a competitor's equivalent. Intel has always been one of the more adamant defenders of an industry-wide categorization, both to avoid confusion and - naturally - put into perspective their process leadership.