Monday, November 25th 2024
Lattice Semiconductor Explores Buying Intel's Altera Unit
Intel Altera's FPGA unit is attracting a lot of attention in the semiconductor industry according to a recent report by Bloomberg, Lattice Semiconductor emerging as a potential buyer for the entire division. Bloomberg reports that Lattice actively works with advisers and seeks private-sector backing to support their bid. However, Intel's preference appears to be leaning toward selling only a small portion of its Altera shares instead of selling everything and this can be a decisive factor in upcoming negotiations. The potential sale has attracted interest from many outside Lattice Semiconductor, including major private equity firms such as Francisco Partners, Bain Capital, and Silver Lake Management. Qualcomm has also expressed interest in acquiring parts of Intel's design business.
Bloomberg also reports that selling just a portion of Altera's shares would likely require complex financial arrangements, while private equity firms are considering investing about $3 billion through instruments. This could result in Intel's valuation being lower than the original purchase price. Intel CEO Pat Gelsinger has indicated plans to close the Altera transaction in early 2024, with the company valuing the nearly $16.7 billion Intel paid for Altera in 2015 at approximately $17 billion. Lattice's market value of $7.48 billion is certainly smaller and can challenge Lattice's ambitions for complete control of Altera. The Intel board discussed Altera's future last week and prefers to sell only a minority stake, with a decision expected soon.
Sources:
TrendForce, Bloomberg
Bloomberg also reports that selling just a portion of Altera's shares would likely require complex financial arrangements, while private equity firms are considering investing about $3 billion through instruments. This could result in Intel's valuation being lower than the original purchase price. Intel CEO Pat Gelsinger has indicated plans to close the Altera transaction in early 2024, with the company valuing the nearly $16.7 billion Intel paid for Altera in 2015 at approximately $17 billion. Lattice's market value of $7.48 billion is certainly smaller and can challenge Lattice's ambitions for complete control of Altera. The Intel board discussed Altera's future last week and prefers to sell only a minority stake, with a decision expected soon.
11 Comments on Lattice Semiconductor Explores Buying Intel's Altera Unit
AMD has done far better with xilinx in that aspect
2cents drunken citizen out.
Or is Patsy that far behind on his calendar/schedule ?
Anyway, this transaction would probably make their financial quagmire much worse than it already is, so probably not a good idea :D
But yeah, apart from this product (that I don't think got any significant traction) seems like they did fuck all with Altera.
Imagine with a FPGA array you could have HW decoders/encoders for whatever new codecs shows and software defined accelerators, but i guess that would make the people buy even less of your new shiny thing as they can reprogram what they have.
Intel had really no business buying altera, they operate in absolute different parts of the tech spectrum with zero overlap, nothing that altera brought was of use to intel being a low volume extremely expensive high-cost high-margin product with zero use for consumers. Absolutely ZERO of altera's IP made its way into intel core products (CPU/GPU as that's pretty much all they have left after they divested themselves of f everything else, they barely do networking).
PRetty much teh same applies to AMD buying xilinx, which itr even seems they bought out of panic/spite, as again absolutely nothing of xilinx made their way into AMD products, for example a epyc or ryzen cpu with a fpga die!, or a full FPGA IO die which would allow on-the-fly reconfiguration of IFOP lanes and allow them to support faster/different memory
As for integrating programmable logic into processors ... FPGAs are very inefficient area-wise and power-wise.That's from an older sourcefrom 2006 but FPGAs haven't fundamentally changed; well, they now include even larger fixed-function blocks such as CPU cores, PCIe controllers and DDR controllers.Again an older source.
At this point, we need a thorough rethink of the FPGA architecture. I imagine something like a large number of larger and smaller mostly-fixed-function blocks tied together by a small amount of programmable logic and interconnects. Could someone make that efficient enough (by die space and power consumption), yet universal enough?
Also, what is CPU microcode? It's binary data that (among other things) governs the operation of the instruction decoder to a large degree. At least it seems so but we don't even know any rough details. Therefore I assume that a significant part of the decoder is programmable logic. Lookup tables and similar stuff.
that's another thing they bungled see, they never bothered to integrate a powerful X86 core(heck put a couple of those shitty "atom" E-cores), since those cpu+fpga are used in almost 99% of digital oscilloscopes and test gear they could've enabled much better performance or reduce the BOM by not needing a separate application processor in some higher end units
FPGAs are fun, and they are great prototyping tools and for complex, low-volume designs. However they are very die area-inefficient and expensive to produce, and while configurability is a positive attribute, most end users don't need the level of configurability that a FPGA provides. If you are a large enough end user to need a specific capability from a SoC, you also probably have the scale for AMD to spin an actual custom die for you that provides that solution in a much cheaper and more area efficient manner. The only aspect is software, you could have a FPGA in a x86 SOC that can be configured to accelerate different things, but what API is software going to use to target this accelerator? Is this API configurable too? It is a struggle enough for the industry to use AI accelerators at the moment, despite how much marketing ans money is being poores into it, because software just isn't using the hardware available.
Microcode includes a number of things such as lookup tables, state machines and sequential programs run by embedded cores. The FPUs also use look up tables and I believe the Pentium FDIV bug was one of the main reasons Intel started making the microcode updatable (it used to be hard coded). That and the F00F bug. P5 was a fun architecture.I believe OpenCL supports FPGAs and has for a while.