China is on course to become the world's leading semiconductor manufacturing hub by the end of the decade. Market research firm Yole Group predicts that by 2030, China will account for 30% of global foundry capacity, a sharp increase from its 21% share in 2024. This growth will position China ahead of Taiwan, which currently holds a 23% market share. In recent years, Beijing has committed vast public and private resources to domestic chip production. Last year, Chinese fabs processed 8.85 million wafers per month, marking an annual increase of approximately 15%. That output will rise to 10.1 million wafers per month in 2025. Much of this expansion comes from the commissioning of 18 new fabs. For example, Huahong Semiconductor opened its 12‑inch facility in Wuxi and began volume production in the first quarter of 2025.

Despite strong capacity growth, China still faces significant issues. The United States is the world's largest wafer consumer, with 57% of global demand, yet it produces only about 10% of the total supply. As a result, American firms must import most of their chips from Asian foundries. Japan and Europe enjoy a more balanced situation by relying on domestic production to meet local needs. China's manufacturers also confront technological barriers. Export controls imposed by the United States limit their access to the most advanced lithography equipment and EDA software. To address this gap, Beijing has launched substantial initiatives to develop homegrown tools and software solutions. These efforts are crucial to closing the divide at cutting‑edge process nodes even as output volumes continue to grow. For now, China is emerging as the leader in mature node output, an area that the automotive sector is particularly interested in.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced a strategic collaboration with Siemens Digital Industries Software for semiconductor design and manufacturing processes for the 2 nm generation. Rapidus will collaborate with Siemens to jointly develop a process design kit based on the Calibre platform, the industry-standard verification solution that enables highly accurate and efficient physical verification, manufacturing optimization and reliability assessment from semiconductor design through to fabrication, while continuing to further its design and verification ecosystem.

This collaboration supports the manufacturing for design (MFD) concept advocated by Rapidus to achieve high yield and short turnaround time from the early stages of manufacturing. Further, Rapidus and Siemens EDA will build a reference flow that holistically supports design, verification and manufacturing from front-end to back-end. This reference flow provides a smooth development environment for Rapidus' Rapid and Unified Manufacturing Service (RUMS).

Texas Instruments (TI) today announced its plans to invest more than $60 billion across seven U.S. semiconductor fabs, making this the largest investment in foundational semiconductor manufacturing in U.S. history. Working with the Trump administration and building on the company's nearly 100-year legacy, TI is expanding its U.S. manufacturing capacity to supply the growing need for semiconductors that will advance critical innovations from vehicles to smartphones to data centers. Combined, TI's new manufacturing mega-sites in Texas and Utah will support more than 60,000 U.S. jobs.

"TI is building dependable, low-cost 300 mm capacity at scale to deliver the analog and embedded processing chips that are vital for nearly every type of electronic system," said Haviv Ilan, president and CEO of Texas Instruments. "Leading U.S. companies such as Apple, Ford, Medtronic, NVIDIA and SpaceX rely on TI's world-class technology and manufacturing expertise, and we are honored to work alongside them and the U.S. government to unleash what's next in American innovation."

Micron Technology, Inc. (Nasdaq: MU) and the Trump Administration today announced Micron's plans to expand its U.S. investments to approximately $150 billion in domestic memory manufacturing and $50 billion in R&D, creating an estimated 90,000 direct and indirect jobs. As part of today's announcement, Micron plans to invest an additional $30 billion beyond prior plans which includes building a second leading-edge memory fab in Boise, Idaho; expanding and modernizing its existing manufacturing facility in Manassas, Virginia; and bringing advanced packaging capabilities to the U.S. to enable long-term growth in High Bandwidth Memory (HBM), which is essential to the AI market. Additionally, Micron is announcing a planned $50 billion domestic R&D investment, reaffirming its long-term position as the global memory technology leader. As previously announced, Micron's investment includes its ongoing plans for a megafab in New York.

Micron's approximately $200 billion broader U.S. expansion vision includes two leading-edge high-volume fabs in Idaho, up to four leading-edge high-volume fabs in New York, the expansion and modernization of its existing manufacturing fab in Virginia, advanced HBM packaging capabilities and R&D to drive American innovation and technology leadership. These investments are designed to allow Micron to meet expected market demand, maintain share and support Micron's goal of producing 40% of its DRAM in the U.S. The co-location of these two Idaho fabs with Micron's Idaho R&D operations will drive economies of scale and faster time to market for leading-edge products, including HBM.

At the recent AI Semiconductor Forum in Seoul, Samsung Electronics revealed that it will adopt hybrid bonding in its upcoming HBM4 memory stacks. This decision is intended to reduce thermal resistance and enable an ultra‑wide memory interface, qualities that become ever more critical as artificial intelligence and high‑performance computing applications demand greater bandwidth and efficiency. Unlike current stacking methods that join DRAM dies with tiny solder microbumps and underfill materials, hybrid bonding bonds copper‑to‑copper and oxide‑to‑oxide surfaces directly, resulting in thinner, more thermally efficient 3D assemblies. High‑bandwidth memory works by stacking multiple DRAM dies on top of a base logic die, with through‑silicon vias carrying signals vertically through each layer. Traditionally, microbumps routed horizontal connections between dies, but as data rates increase and stack heights grow, these bumps introduce significant electrical and thermal limitations.

Hybrid bonding addresses those issues by allowing interconnect pitches below 10 micrometers, which lowers both resistance and capacitance and improves overall signal integrity. SK hynix has taken a different path. The company is enhancing its molded reflow underfill (MR‑MUF) process to produce 16‑Hi HBM4 stacks that comply with JEDEC's maximum height requirement of 775 micrometers. The company believes that if its advanced MR‑MUF technique can achieve performance on par with hybrid bonding, they will avoid the substantial capital investment needed for the specialized equipment that true 3D copper bonding requires. The cost and space demands of hybrid bonding equipment are significant. Specialized lithography and alignment tools occupy more clean‑room real estate, increasing capital expenditures. Samsung may mitigate some of these costs through Semes, its in‑house equipment subsidiary, but it remains uncertain whether Semes can deliver production‑ready hybrid bonding systems in time for mass production. If Samsung successfully qualifies its HBM4 stacks using hybrid bonding, which it plans to begin manufacturing in 2026, the company could gain a competitive edge over Micron and SK hynix.

NEO Semiconductor, a leading developer of innovative technologies for 3D NAND flash memory and 3D DRAM, announced today the latest advancement in its groundbreaking 3D X-DRAM technology family—the industry-first 1T1C- and 3T0C-based 3D X-DRAM cell, a transformative solution designed to deliver unprecedented density, power efficiency, and scalability for the most demanding data applications.

Built on a 3D NAND-like architecture and with proof-of-concept test chips expected in 2026, the new 1T1C and 3T0C designs combine the performance of DRAM with the manufacturability of NAND, enabling cost-effective, high-yield production with densities up to 512 Gb—a 10x improvement over conventional DRAM.
"With the introduction of the 1T1C and 3T0C 3D X-DRAM, we are redefining what's possible in memory technology," said Andy Hsu, Founder & CEO of NEO Semiconductor. "This innovation pushes past the scaling limitations of today's DRAM and positions NEO as a frontrunner in next-generation memory."

According to the Financial Times, gathering data from satellite images and industry intelligence, Huawei has endeavored to develop a domestic AI supply chain to bypass foreign tech restriction influence. In Guanlan, China, Huawei started developing a complete facility for manufacturing semiconductors on 7 nm technology for its custom processors. Out of frustration with SMIC's low output capacity, Huawei has secured the entire silicon production, from sourcing materials, chemicals, and wafer fab equipment to chip-making equipment to actual chip design. According to Dylan Patel of SemiAnalysis, "Huawei has embarked on an unprecedented effort to develop every part of the AI supply chain domestically from wafer fabrication equipment to model building," adding, "We have never seen one company attempt to do everything before."

It is also reported that Huawei's rivals in silicon manufacturing, SMIC and SMEE, have deployed engineers to help Huawei develop its own manufacturing flow. A few companies, all backed by Huawei with funding and research, are the backbone of this operation. SiCarrier, which we reported on back in March, supplies optical and X-ray inspection tools, atomic force microscopes, and alignment systems for metrology; gas-based and atomic layer deposition tools for film coating; plasma etchers for patterning; rapid thermal processors for material tuning; and electrical testing platforms for reliability screening. SwaySure and Fujian Jinhua supply memory chips, Si'En and Pehgjin supply power chips, and PWX and PST deal with logic.

The global semiconductor industry is experiencing notable shifts, largely influenced by the rapid expansion of the Mainland China market. From 2010 to 2024, China's share of global semiconductor equipment sales rose significantly, from just 6% in 2010 to 38% in 2024. On the other side McKinsey reports that market shares in Taiwan, Korea and Japan are declining. Taiwan has started to build semiconductor fabs in the US and Europe, while Japan has seen few new fab projects despite TSMC's upcoming Kumamoto plant. At the same time, the US and Europe, the Middle East, and Africa have kept their market shares steady.

Globalization helped the semiconductor industry grow from 2010 to 2019, during this time Chinese semiconductor companies expanded, with local firms growing by about 21% each year. But growth slowed from 2019 to 2023 because of US sanctions on Huawei which affected its chip division HiSilicon. Even without HiSilicon, China's semiconductor industry still grew by 9-10% in that period. Experts think this growth will continue in the future, a trend that the current US tariffs are only accentuating. China's growing importance in industries like electric vehicles (EVs) and commercial drones is pushing its semiconductor goals even further. In 2023, China accounted for 60% of all new EV registrations around the world. At the same time, political tensions between countries have made China more eager to build a self-reliant domestic semiconductor ecosystem. China is testing a domestic extreme ultraviolet (EUV) lithography system at Huawei's Dongguan facility. The system uses laser-induced discharge plasma technology and is scheduled for trial production in Q3 2025, with mass manufacturing planned for 2026.

LG unveiled the Dream Factory, a hub for the production of FC-BGAs (Flip Chip Ball Grid Arrays), the company's next-generation growth engine, to the media for the first time and announced it on the 30th April.

In 2022, LG Innotek announced its plans to launch a business producing FC-BGAs, high-value semiconductor substrates. To build the Dream Factory, the company acquired LG Electronics' Gumi 4 Factory and began full-scale mass production in February 2024.

Samsung Electronics today reported financial results for the first quarter ended March 31, 2025. The Company posted KRW 79.14 trillion in consolidated revenue, an all-time quarterly high, on the back of strong sales of flagship Galaxy S25 smartphones and high-value-added products. Operating profit increased to KRW 6.7 trillion despite headwinds for the DS Division, which experienced a decrease in quarterly revenue.

The Company has allocated its highest-ever annual R&D expenditure for 2024, and in the first quarter of this year, it has also increased its R&D expenditure by 16% compared to the same period last year, amounting to 9 trillion won. Despite the growing macroeconomic uncertainties due to recent global trade tensions and slowing global economic growth, making it difficult to predict future performance, the Company will continue to make various efforts to secure growth. Additionally, assuming that the uncertainties are diminished, it expects its performance to improve in the second half of the year.

Global semiconductor materials market revenue increased 3.8% to $67.5 billion in 2024, SEMI, the global industry association representing the electronics design and manufacturing supply chain, reported today in its Materials Market Data Subscription (MMDS). The recovery of the overall semiconductor market as well as the increasing demand for advanced materials for high-performance compute and high-bandwidth memory manufacturing supported 2024 materials revenue growth.

Wafer fabrication materials revenue increased 3.3% to $42.9 billion in 2024, while packaging materials revenue grew 4.7% to $24.6 billion last year. The chemical mechanical planarization (CMP), photoresist, and photoresist ancillaries segments experienced strong double-digit growth driven by increased complexity and number of processing steps required for advanced DRAM, 3D NAND flash and leading-edge logic integrated circuits (ICs). All semiconductor materials segments, except for silicon and silicon-on-insulator (SOI), registered year-on-year increases. The demand for silicon, particularly in the trailing edge segment, remained weak in 2024 as the industry continued to work through excess inventory, resulting in a 7.1% decline in silicon revenue in 2024.

OKI Circuit Technology, the OKI Group printed circuit board (PCB) company, has successfully developed 124-layer PCB technology for wafer inspection equipment designed for next-generation high bandwidth memory, such as HBM mounted on AI semiconductors. This is a roughly 15% increase in the number of layers over conventional 108-layer designs. OTC is seeking to establish mass production technology by October 2025 at its Joetsu Plant in Joetsu City, Niigata Prefecture, which has a proven track record and advanced development and production capabilities in the field of high multilayer, high-precision, large-format PCBs for semiconductor inspection equipment.

AI processing requires the transmission of vast data volumes between graphics processing unit (GPU) semiconductors and memory. As semiconductor performance increases, the memory installed is also required to have high-speed, high-frequency, and high-density data transfer capabilities. HBM features a stacked DRAM structure, requiring technology capable of fabricating wafers even more thinly and precisely. This configuration also requires that the PCBs used in inspection equipment meet even higher levels of performance and quality.

As the US works to bring more semiconductor manufacturing back home, the machines needed to turn silicon into the world's most advanced processors are becoming pricier and harder to get, thanks to tariffs. Foundries building new fabs report that the specialized equipment they rely on, everything from extreme ultraviolet (EUV) lithography steppers to chemical vapor deposition chambers, carries a roughly 15% premium compared with similar gear sold overseas. Several forces are at play. The raw materials, high‑grade quartz for vacuum enclosures, and exotic metal alloys for precision optics have climbed in price. At the same time, key components like ultra‑accurate motion stages and alignment sensors are in short supply, sometimes stretching lead times for critical subsystems well beyond 18 months. For a fab racing to move from a 7 nm to a 5 nm process, those delays can mean missing tight ramp‑up targets and pushing out product launches.

Smaller chipmakers feel the squeeze the hardest. With fewer orders to negotiate volume discounts, second‑tier foundries may see their capital budgets balloon by 20 percent or more. In response, some are taking a mixed approach, sourcing commoditized tools such as oxidation furnaces and rapid thermal processors from multiple suppliers while reserving single‑vendor deals for high‑stakes systems like EUV scanners. Government support through the CHIPS Act offers a partial safety net, helping to subsidize capital expenditures. Yet even with grants and tax credits, the challenges will remain. Success will hinge on tight coordination between fabs, equipment makers, and policymakers to tame rising costs, shorten delivery schedules, and keep America's chip renaissance on track.

Samsung's foundry business seems to be busying itself with the rumored refinement of a 2 nm GAA (SF2) manufacturing node process—for possible mass production by the end of 2025, but company leadership will very likely be considering longer term goals. Mid-way through last month, industry moles posited that the megacorporation's semiconductor branch was questioning the future of a further out 1.4 nm (SF1.4) production line. Officially published roadmaps have this advanced technology rolling out by 2027. Despite present day "turmoil," insiders believe that a new team has been established—tasked with the creation of a so-called "dream semiconductor process." According to a fresh Sedaily news article, this fledgling department has started development of a 1 nm foundry process.

Anonymous sources claim that Samsung executives are keeping a watchful eye on a main competitor—as stated in the latest South Korean report: "there is a realistic gap with Taiwan's TSMC in technologies that are close to mass production, such as the 2 nm process, the company plans to speed up the development of the 1 nm process, a future technology, to create an opportunity for a turnaround." A portion of the alleged "1 nm development chip team" reportedly consists of veteran researchers from prior-gen projects. Semiconductor industry watchdogs theorize that a canceled SF1.4 line could be replaced by an even more advanced process. Sedaily outlined necessary hardware upgrades: "the 1.0 nanometer process requires a new technology concept that breaks the mold of existing designs as well as the introduction of next-generation equipment such as high-NA EUV exposure equipment. The company is targeting mass production after 2029." Samsung's current Advanced Technology Roadmap does not extend beyond 2027—inside sources claim that the decision to roll with 1.0 nm was made at some point last month.

This week, IBM and Tokyo Electron (TEL) announced an extension of their agreement for the joint research and development of advanced semiconductor technologies. The new 5-year agreement will focus on the continued advancement of technology for next-generation semiconductor nodes and architectures to power the age of generative AI. This agreement builds on a more than two-decade partnership between IBM and TEL for joint research and development. Previously, the two companies have achieved several breakthroughs, including the development of a new laser debonding process for producing 300 mm silicon chip wafers for 3D chip stacking technology.

Now, bringing together IBM's expertise in semiconductor process integration and TEL's leading-edge equipment, they will explore technology for smaller nodes and chiplet architectures to achieve the performance and energy efficiency requirements for the future of generative AI. "The work IBM and TEL have done together over the last 20 years has helped to push the semiconductor technology innovation to provide many generations of chip performance and energy efficiency to the semiconductor industry," said Mukesh Khare, GM of IBM Semiconductors and VP of Hybrid Cloud, IBM. "We are thrilled to be continuing our work together at this critical time to accelerate chip innovations that can fuel the era of generative AI."

Yesterday, United States President Donald Trump announced a set of tariffs imposed on US trading partners, imposing a series of 10%+ tariffs on partners, calling it a "Liberation Day." Today, we are calculating how much these tariffs will impact consumers and what is most important at TechPowerUp: semiconductors powering our GPUs and CPUs. According to one of the top investment banks, Goldman Sachs, semiconductors are exempt from the reciprocal tariffs that Trump has imposed on Taiwan. However, the semiconductor manufacturing equipment used by makers like TSMC is not exempt and is expected to be hit with the 32% tariffs. This is only half of what Taiwan imposes on imports of US-made goods. For TSMC, the number one maker of GPUs and CPUs, tariffs can be tricky to navigate. While its existing manufacturing facilities use equipment sourced from Dutch ASML and a few US companies like Lam Research and KLA Corporation, it shouldn't be a problem to ship new silicon to the US.

However, if TSMC wants to expand its manufacturing facilities in any country that is not the US, it will have to deal with 32% tariffs on US-sourced silicon manufacturing equipment. For EU-based ASML, things are looking a little different. If over 20% of the equipment is made up of US content, a tariff exemption might apply, potentially reducing import costs. If more than one-fifth of a product's components or value originates from US sources, the equipment may be eligible for tariff relief. ASML's machines include some US components, so determining whether these machines meet the 20% threshold is crucial. If they do, the tariff exemption could help lower costs associated with importing these advanced machines, reaching up to $380 million. For non-US-injected goods, EU entities are subject to 20% tariffs.

Rapidus Corporation today announced that its plans and budget for fiscal year 2025 have been approved by Japan's New Energy and Industrial Technology Development Organization (NEDO). The approval covers two commissioned projects under NEDO's "Post-5G Information and Communication Systems Infrastructure Enhancement R&D Project / Development of Advanced Semiconductor Manufacturing Technology (Commissioned)." These projects are the "Research and Development of 2 nm-Generation Semiconductor Integration Technology and short TAT (turnaround time) Manufacturing Technology Based on Japan-U.S. Collaboration" and "Development of Chiplet, Package Design and Manufacturing Technology for 2 nm-Generation Semiconductors."

The first of these projects, focused on front-end processes, was launched in November 2022 as part of Japan's next-generation semiconductor R&D effort. Under this program, Rapidus has continued construction of the Innovative Integration for Manufacturing (IIM) facility in Chitose, Hokkaido, which will serve as its production base. It also sent engineers to IBM in the U.S. to jointly develop 2 nm logic semiconductor mass production technologies and continued to achieve target performance as planned. Furthermore, Rapidus has installed EUV lithography and other production equipment at the IIM facility, and started cleanroom operation. As a result of these efforts, the company achieved its performance targets for FY2024.

Ayar Labs, the leader in optical interconnect solutions for large-scale AI workloads, today announced the industry's first Universal Chiplet Interconnect Express (UCIe) optical interconnect chiplet to maximize AI infrastructure performance and efficiency while reducing latency and power consumption. By incorporating a UCIe electrical interface, this solution is designed to eliminate data bottlenecks and integrate easily into customer chip designs.

Capable of achieving 8 Tbps bandwidth, the TeraPHY optical I/O chiplet is powered by Ayar Labs' 16-wavelength SuperNova light source. The integration of a UCIe interface means this solution not only delivers high performance and efficiency but also enables interoperability among chiplets from different vendors. This compatibility with the UCIe standard creates a more accessible, cost-effective ecosystem, which streamlines the adoption of advanced optical technologies necessary for scaling AI workloads and overcoming the limitations of traditional copper interconnects.

According to a report produced by semiconductor industry analysts at Kiwoom Securities—a South Korean financial services firm—Semiconductor Manufacturing International Corporation (SMIC) is expected to complete the development of a 5 nm process at some point in 2025. Jukanlosreve summarized this projection in a recent social media post. SMIC is often considered to be China's flagship foundry business; the partially state-owned organization seems to heavily involved in the production of (rumored) next-gen Huawei Ascend 910 AI accelerators. SMIC foundry employees have reportedly struggled to break beyond a 7 nm manufacturing barrier, due to lack of readily accessible cutting-edge EUV equipment. As covered on TechPowerUp last month, leading lights within China's semiconductor industry are (allegedly) developing lithography solutions for cutting-edge 5 nm and 3 nm wafer production.

Huawei is reportedly evaluating an in-house developed laser-induced discharge plasma (LDP)-based machine, but finalized equipment will not be ready until 2026—at least for mass production purposes. Jukanlosreve's short interpretation of Kiwoom's report reads as follows: (SMIC) achieved mass production of the 7 nm (N+2) process without EUV and completed the development of the 5 nm process to support the mass production of the Huawei Ascend 910C. The cost of SMIC's 5 nm process is 40-50% higher than TSMC's, and its yield is roughly one-third." The nation's foundries are reliant on older ASML equipment, thus are unable to produce products that can compete with the advanced (volume and quality) output of "global" TSMC and Samsung chip manufacturing facilities. The fresh unveiling of SiCarrier's Color Mountain series has signalled a promising new era for China's foundry industry.

Yield Engineering Systems, Inc. (YES), a global leader in materials and interface engineering equipment solutions, proudly announces the shipment of the first commercial VeroTherm Formic Acid Reflow tool to a leading global semiconductor manufacturer from its Sulur, Coimbatore, manufacturing facility. This landmark achievement signifies a pivotal moment for YES and the burgeoning semiconductor ecosystem in India, as it represents the first equipment produced in India for advanced semiconductor applications like High Bandwidth Memory (HBM), which is critical for AI and High-Performance Computing (HPC) applications worldwide.

YES commenced operations in September 2024 at this state-of-the-art manufacturing facility in Sulur, Coimbatore, India, located at 96/3 Vadakku Sambala Thottam, Trichy Road, Kannampalayam, Sulur Taluk. This facility is integral to YES's strategic expansion plan, aimed at serving its global customers' operations in India and the world with greater efficiency.

Global fab equipment spending for front-end facilities in 2025 is anticipated to increase by 2% year-over-year (YoY) to $110 billion, marking the sixth consecutive year of growth since 2020, SEMI announced today in its latest quarterly World Fab Forecast report.

Fab equipment spending is projected to rise by 18% in the following year, reaching $130 billion. This growth in investment is driven not only by demand in the high-performance computing (HPC) and memory sectors to support data center expansions, but also by the increasing integration of artificial intelligence (AI), which is driving up the silicon content required for edge devices.

Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced that it signed a Memorandum of Cooperation with Quest Global Services PTE. Ltd. As part of the agreement, Rapidus will become Quest Global's new semiconductor foundry partner, enabling it to provide a wide range of solutions to its customers. Quest Global customers will be able to leverage Rapidus' 2 nm gate-all-around (GAA) manufacturing process to develop engineering design and manufacturing solutions that will support growing industry demand for low-power artificial intelligence (AI) semiconductors. Together, the two companies will deliver transformational silicon solutions as a virtual integrated device manufacturer (IDM) model for fabless companies.

The AI semiconductor industry is in its early stages, with applications just beginning to emerge and new entrants quickly coming to market. Customers will shift from general-purpose AI semiconductors to dedicated designs that reduce power consumption and maximize performance. To support these industry requirements, customers will engage design firms focused on providing custom solutions, such as Quest Global, while also collaborating with semiconductor foundries, like Rapidus, that can manufacture dedicated semiconductors with a short turnaround time.

Seeking to explore semiconductor policy measures that can strengthen the industrial policy in the European Union, SEMI and the European Semiconductor Industry Association (ESIA) have successfully held a high-level roundtable event in the European Parliament under the auspices of Members of the European Parliament (MEPs) Bart Groothuis (Renew Europe), Oliver Schenk (European People's Party) and Dan Nica (Socialists and Democrats Party).

The 2023 European Chips Act marked an important milestone for Europe's semiconductor industry and overall industrial ecosystem, providing concrete measures to enhance competitiveness and technological capabilities. In order to build on the success of the Chips Act, after the roundtable, MEPs signed a joint declaration to the European Commission's Executive Vice President for Tech Sovereignty, Security and Democracy, Henna Virkkunen, calling for an ambitious follow-up to the Chips Act that adds new research and development (R&D) funds, attracts new investments, and increases European competitiveness.

Vietnam's government has approved its first wafer fab facility, with an investment of 12.8 trillion VND (approximately $500 million). The first phase of the facility, scheduled for completion by 2030, is designed to manufacture specialized chips for defense, AI, and other high-tech applications. The project will receive government backing through direct funding—covering up to 30% of the total investment, capped at 10 trillion VND—and tax incentives. A special steering committee headed by the Prime Minister has been tasked with overseeing the project's execution and resource allocation. The new fab is a critical component of Vietnam's long-term semiconductor strategy, a phased approach toward building a domestic ecosystem for chip design, manufacturing, and testing. The current investment is modest compared to the typical costs of advanced wafer fabs, which can reach up to $50 billion.

Nonetheless, the project is a foundational, one-step-at-the-time move intended to spur further investments and technology transfer. Vietnamese officials have reportedly engaged in discussions with major international chip manufacturers—including US, South Korea, and Taiwan entities, such as GlobalFoundries and Powerchip Semiconductor Manufacturing Corp—to explore potential collaborative opportunities. Vietnam already hosts 174 semiconductor-related projects, predominantly focused on chip packaging and testing, in which global companies like Intel and Amkor have established significant operations. The second phase, from 2030-2040, envisions Vietnam emerging as a worldwide center for electronics and semiconductors. By expanding to at least 200 design companies, establishing two semiconductor chip manufacturing plants, and creating 15 packaging and testing facilities, the country intends to gradually develop independent semiconductor product design and production capabilities.

China's Ministry of Finance has allocated $55 billion (¥398.12 billion) for science and technology funding in 2025, marking a 10% increase from the previous year's $50 billion (¥361.9 billion). This expenditure now stands as the nation's third-largest budget item, following only national defense and debt interest payments. The 2024 allocation achieved a 97.6% implementation rate, indicating effective deployment of resources in the technology sector. The funding prioritizes initiatives under the "Science and Technology Innovation 2030" program, with significant investments targeting semiconductors, artificial intelligence, and quantum computing research. Rather than stimulating immediate breakthroughs, the incremental funding increase aims to strengthen existing projects and enhance technological self-reliance amid global competition.

This strategy shows some fiscal constraints imposed by China's economic slowdown while maintaining the country's long-term technological objectives. Supplementary measures bolster direct R&D investment, including enhanced support for fundamental research and specialized financing mechanisms for technology-focused enterprises. Tax reductions and targeted subsidies form part of a comprehensive policy framework designed to foster domestic innovation capabilities. While the funding increase shows commitment to technological advancement, effective project management and efficient resource allocation will be critical success factors, mainly as China competes more globally. Perhaps the most important milestone for this aid package will be supporting the development of advanced lithography tools to make sure that domestic companies can manufacture cutting-edge silicon.