In advance of Supercomputing '22 in Dallas, Intel Corporation has introduced the Intel Max Series product family with two leading-edge products for high performance computing (HPC) and artificial intelligence (AI): Intel Xeon CPU Max Series (code-named Sapphire Rapids HBM) and Intel Data Center GPU Max Series (code-named Ponte Vecchio). The new products will power the upcoming Aurora supercomputer at Argonne National Laboratory, with updates on its deployment shared today.

The Xeon Max CPU is the first and only x86-based processor with high bandwidth memory, accelerating many HPC workloads without the need for code changes. The Max Series GPU is Intel's highest density processor, packing over 100 billion transistors into a 47-tile package with up to 128 gigabytes (GB) of high bandwidth memory. The oneAPI open software ecosystem provides a single programming environment for both new processors. Intel's 2023 oneAPI and AI tools will deliver capabilities to enable the Intel Max Series products' advanced features.

Eliyan Corporation, credited for the invention of the semiconductor industry's highest-performance and most efficient chiplet interconnect, today announced two major milestones in the commercialization of its technology for multi-die chiplet integration: the close of its Series A $40M funding round, and the successful tapeout of its technology on an industry standard 5-nanometer (nm) process.

Eliyan's NuLink PHY and NuGear technologies address the critical need for a commercially viable approach to enabling high performance and cost-effectiveness in the connection of homogeneous and heterogenous architectures on a standard, organic chip substrate. It has proven to achieve similar bandwidth, power efficiency, and latency as die-to-die implementations using advanced packaging technologies, but without the other drawbacks of specialized approaches.

NVIDIA's high-performance computing hardware stack is now equipped with the top-of-the-line Hopper H100 GPU. It features 16896 or 14592 CUDA cores, developing if it comes in SXM5 of PCIe variant, with the former being more powerful. Both variants come with a 5120-bit interface, with the SXM5 version using HBM3 memory running at 3.0 Gbps speed and the PCIe version using HBM2E memory running at 2.0 Gbps. Both versions use the same capacity capped at 80 GBs. However, that could soon change with the latest rumor suggesting that NVIDIA could be preparing a PCIe version of Hopper H100 GPU with 120 GBs of an unknown type of memory installed.

According to the Chinese website "s-ss.cc" the 120 GB variant of the H100 PCIe card will feature an entire GH100 chip with everything unlocked. As the site suggests, this version will improve memory capacity and performance over the regular H100 PCIe SKU. With HPC workloads increasing in size and complexity, more significant memory allocation is needed for better performance. With the recent advances in Large Language Models (LLMs), AI workloads use trillions of parameters for tranining, most of which is done on GPUs like NVIDIA H100.

The Exascale supercomputing race is now well underway, as the US-based Frontier supercomputer got delivered, and now we wait to see the remaining systems join the race. Today, during 79th HPC User Forum at Oak Ridge National Laboratory (ORNL), Terri Quinn at Lawrence Livermore National Laboratory (LLNL) delivered a few insights into what El Capitan exascale machine will look like. And it seems like the new powerhouse will be based on AMD's Instinct MI300 APU. LLNL targets peak performance of over two exaFLOPs and a sustained performance of more than one exaFLOP, under 40 megawatts of power. This should require a very dense and efficient computing solution, just like the MI300 APU is.

As a reminder, the AMD Instinct MI300 is an APU that combines Zen 4 x86-64 CPU cores, CDNA3 compute-oriented graphics, large cache structures, and HBM memory used as DRAM on a single package. This is achieved using a multi-chip module design with 2.5D and 3D chiplet integration using Infinity architecture. The system will essentially utilize thousands of these APUs to become one large Linux cluster. It is slated for installation in 2023, with an operating lifespan from 2024 to 2030.

AMD in its 2022 Financial Analyst Day presentation unveiled its next-generation CDNA3 compute architecture, which will see something we've been expecting for a while—a compute accelerator that has a large number of compute units for scalar processing, and a large number of x86-64 CPU cores based on some future "Zen" microarchitecture, onto a single package. The presence of CPU cores on the package would eliminate the need for the system to have an EPYC or Xeon processor at its head, and clusters of Instinct CDNA3 processors could run themselves without the need for a CPU and its system memory.

The Instinct CDNA3 processor will feature an advanced packaging technology that brings various IP blocks together as chiplets, each based on a node most economical to it, without compromising on its function. The package features stacked HBM memory, and this memory is shared not just by the compute units and x86 cores, but also forms part of large shared memory pools accessible across packages. 4th Generation Infinity Fabric ties it all together.

Samsung Electronics and Red Hat today announced a broad collaboration on software technologies for next-generation memory solutions. The partnership will focus on the development and validation of open source software for existing and emerging memory and storage products, including NVMe SSDs; CXL memory; computational memory/storage (HBM-PIM, Smart SSDs) and fabrics — in building an expansive ecosystem for closely integrated memory hardware and software. The exponential growth of data driven by AI, AR and the fast-approaching metaverse is bringing disruptive changes to memory designs, requiring more sophisticated software technologies that better link with the latest hardware advancements.

"Samsung and Red Hat will make a concerted effort to define and standardize memory software solutions that embrace evolving server and memory hardware, while building a more robust memory ecosystem," said Yongcheol Bae, Executive Vice President and Head of the Memory Application Engineering Team at Samsung Electronics. "We will invite partners from across the IT industry to join us in expanding the software-hardware memory ecosystem to create greater customer value."

Today we got information that AMD's upcoming Instinct MI300 will be allegedly available as an Accelerated Processing Unit (APU). AMD APUs are processors that combine CPU and GPU into a single package. AdoredTV managed to get ahold of a slide that indicates that AMD Instinct MI300 accelerator will also come as an APU option that combines Zen4 CPU cores and CDNA3 GPU accelerator in a single, large package. With technologies like 3D stacking, MCM design, and HBM memory, these Instinct APUs are positioned to be a high-density compute the product. At least six HBM dies are going to be placed in a package, with the APU itself being a socketed design.

The leaked slide from AdoredTV indicates that the first tapeout is complete by the end of the month (presumably this month), with the first silicon hitting AMD's labs in Q3 of 2022. If the silicon turns out functional, we could see these APUs available sometime in the first half of 2023. Below, you can see an illustration of the AMD Instinct MI300 GPU. The APU version will potentially be of the same size with Zen4 and CDNA3 cores spread around the package. As Instinct MI300 accelerator is supposed to use eight compute tiles, we could see different combinations of CPU/GPU tiles offered. As we await the launch of the next-generation accelerators, we are yet to see what SKUs AMD will bring.

Intel has allowed the media to get a closer look at the next generation of silicon that will power millions of systems in years to come during its private Vision event. PC Watch, a Japanese tech media, managed to get some shots of the upcoming Meteor Lake, Sapphire Rapids, and Ponte Vecchio processors. Starting with Meteor Lake, Intel has displayed two packages for this processor family. The first one is the ultra-compact, high-density UP9 package used for highly compact mobile systems, and it is made out of silicon with minimal packaging to save space. The second one is a traditional design with more oversized packaging, designed for typical laptop/notebook configurations.

ServeTheHome, a tech media outlet focused on everything server/enterprise, posted an exclusive set of photos of NVIDIA's latest H100 "Hopper" accelerator. Being the fastest GPU NVIDIA ever created, H100 is made on TSMC's 4 nm manufacturing process and features over 80 billion transistors on an 814 mm² CoWoS package designed by TSMC. Complementing the massive die, we have 80 GB of HBM3 memory that sits close to the die. Pictured below, we have an SXM5 H100 module packed with VRM and power regulation. Given that the rated TDP for this GPU is 700 Watts, power regulation is a serious concern and NVIDIA managed to keep it in check.

On the back of the card, we see one short and one longer mezzanine connector that acts as a power delivery connector, different from the previous A100 GPU layout. This board model is labeled PG520 and is very close to the official renders that NVIDIA supplied us with on launch day.

SK hynix, was the only company that presented its HBM3, a high-end product known as the fastest DRAM in existence with the biggest capacity, at NVIDIA GTC (GPU Technology Conference) 2022, which took place on March 21~24. Known as the world's best-performing DRAM, HBM3 is the fourth generation of the HBM (High Bandwidth Memory) technology. SK hynix's HBM3 uses over 8,000 TSVs per stack (i.e. over 100,000 TSVs in a 12-Hi stack) and can feature up to 12-Hi stack, which is an upgrade from the previous HBM2E's 8-Hi stack. When fully stacked, it can offer up to 24 GB of capacity. With a 16-channel architecture, it runs at 6.4 Gbps, which is double that of HBM2E and which is the fastest in the world, expecting to further accelerate our digital life.

For instance, HBM has become a prerequisite for the Levels 4 and 5 of driving automation when it comes to autonomous vehicles, a topic that has garnered a great deal of attention nowadays. Also, HBM3 is expected to play an even bigger role along with the growth of High Performance Computing (HPC), Artificial Intelligence (AI), Machine Learning (ML), and Advanced Driver Assistance Systems (ADAS) markets fueled by the acceleration of digital transformation.

During the International Solid-State Circuits Conference (ISSCC) 2022, Intel gave us a more significant look at its upcoming Ponte Vecchio HPC accelerator and how it operates. So far, Intel convinced us that the company created Ponte Vecchio out of 47 tiles glued together in one package. However, the ISSCC presentation shows that the accelerator is structured rather interestingly. There are 63 tiles in total, where 16 are reserved for compute, eight are used for RAMBO cache, two are Foveros base tiles, two represent Xe-Link tiles, eight are HBM2E tiles, and EMIB connection takes up 11 tiles. This totals for about 47 tiles. However, an additional 16 thermal tiles used in Ponte Vecchio regulate the massive TDP output of this accelerator.

What is interesting is that Intel gave away details of the RAMBO cache. This novel SRAM technology uses four banks of 3.75 MB groups total of 15 MB per tile. They are connected to the fabric at 1.3 TB/s connection per chip. In contrast, compute tiles are connected at 2.6 TB/s speeds to the chip fabric. With eight RAMBO cache tiles, we get an additional 120 MB SRAM present. The base tile is a 646 mm² die manufactured in Intel 7 semiconductor process and contains 17 layers. It includes a memory controller, the Fully Integrated Voltage Regulators (FIVR), power management, 16-lane PCIe 5.0 connection, and CXL interface. The entire area of Ponte Vecchio is rather impressive, as 47 active tiles take up 2,330 mm², whereas when we include thermal dies, the total area jumps to 3,100 mm². And, of course, the entire package is much larger at 4,844 mm², connected to the system with 4,468 pins.

At Intel's 2022 Investor Meeting, Chief Executive Officer Pat Gelsinger and Intel's business leaders outlined key elements of the company's strategy and path for long-term growth. Intel's long-term plans will capitalize on transformative growth during an era of unprecedented demand for semiconductors. Among the presentations, Intel announced product roadmaps across its major business units and key execution milestones, including: Accelerated Computing Systems and Graphics, Intel Foundry Services, Software and Advanced Technology, Network and Edge, Technology Development, More: For more from Intel's Investor Meeting 2022, including the presentations and news, please visit the Intel Newsroom and Intel.com's Investor Meeting site.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of the next version of its High Bandwidth Memory (HBM) DRAM standard: JESD238 HBM3, available for download from the JEDEC website. HBM3 is an innovative approach to raising the data processing rate used in applications where higher bandwidth, lower power consumption and capacity per area are essential to a solution's market success, including graphics processing and high-performance computing and servers.

NVIDIA's Crypto Mining (CMP) series of graphics cards are made to work only for one purpose: mining cryptocurrency coins. Hence, their functionality is somewhat limited, and they can not be used for gaming as regular GPUs can. Today, Linus Tech Tips got ahold of NVIDIA's CMP 170HX mining card, which is not listed on the company website. According to the source, the card runs on NVIDIA's GA100-105F GPU, a version based on the regular GA100 SXM design used in data-center applications. Unlike its bigger brother, the GA100-105F SKU is a cut-down design with 4480 CUDA cores and 8 GB of HBM2E memory. The complete design has 6912 cores and 40/80 GB HBM2E memory configurations.

As far as the reason for choosing 8 GB HBM2E memory goes, we know that the Ethereum DAG file is under 5 GB, so the 8 GB memory buffer is sufficient for mining any coin out there. It is powered by an 8-pin CPU power connector and draws about 250 Watts of power. It can be adjusted to 200 Watts while retaining the 165 MH/s hash rate for Ethereum. This reference design is manufactured by NVIDIA and has no active cooling, as it is meant to be cooled in high-density server racks. Only a colossal heatsink is attached, meaning that the cooling needs to come from a third party. As far as pricing is concerned, Linus managed to get this card for $5000, making it a costly mining option.More images follow...

During Samsung's Tech Day 2021, the company presented some interesting insights about the future of system memory technologies and how it plans to execute its production. Starting with the latest DDR5 standard, the company intends to follow JEDEC documents and offer some overclocking modules that surpass the specification advised by JEDEC. While the DDR5 standard specifies memory modules with 6,400 MT/s, Samsung will develop modules capable of overclocking up to 8,400 MT/s. These are not yet confirmed as they are still in the development phase. However, we can expect to see them in the later life of DDR5 memory.

The company also talked about the DDR6 standard, which is supposedly twice as fast as DDR5. The new DDR6 standard is still in early development, and all we know so far is that the number of memory channels per module is seeing a twofold increase over DDR5 to four channels. The number of memory banks also increases to 64. In addition to DDR6 for desktop and server use cases, the company is also working on Low Power DDR6 (LPDDR6) for mobile applications. While the company's LPDDR5 memory goes into volume production using the 1a-nm process at the beginning of 2022, the LPDDR6 is still in early development. The base speed for DDR6 modules will allegedly arrive at 12,800 MT/s, while overclocking modules will join the party at up to 17,000 MT/s. Mobile-oriented LPDDR6 version is also supposed to come with up to 17,000 MT/s speeds.

Intel's Aurora supercomputer is a $500 million contract with the US Department of Energy to deliver an exascale supercomputer for Argonne National Laboratory. The project aims to build a machine capable of cranking over one ExaFLOP of computing at sustained workloads. The supercomputer aims to reach two ExaFLOPs of computing power once the installation system is completed and powered. The contract bound Intel to create accelerators that are powerful enough to achieve this magical number. However, they left Intel with room to do a little bit extra. With Ponte Vecchio GPU behind the project, it seems like the GPU is performing better than expected.

According to Intel's CEO, Pat Gelsinger, the system will reach over 2 ExaFLOPs at peak and a bit below in sustained workloads. As per preliminary calculations done by The Next Platform, the system's estimations point towards 2.43 ExaFLOPs peak and around 1.7 ExaFLOPs in sustained workloads at Double-precision floating-point format math, aka FP64. The system will utilize Intel Xeon Sapphire Rapids processors with HBM memory and the powerful Ponte Vecchio GPU with 47 tiles and over 100 billion transistors.

SK hynix Inc. announced that it has become the first in the industry to successfully develop the High Bandwidth Memory 3, the world's best-performing DRAM. HBM3, the fourth generation of the HBM technology with a combination of multiple DRAM chips vertically connected, is a high value product that innovatively raises the data processing rate.

The latest development, which follows the start of mass production of HBM2E in July last year, is expected to help consolidate the company's leadership in the market. SK hynix was also the first in the industry to start mass production of HBM2E. SK hynix's HBM3 is not only the fastest DRAM in the world, but also comes with the biggest capacity and significantly improved level of quality.

Synopsys, Inc. today announced the industry's first complete HBM3 IP solution, including controller, PHY, and verification IP for 2.5D multi-die package systems. HBM3 technology helps designers meet essential high-bandwidth and low-power memory requirements for system-on-chip (SoC) designs targeting high-performance computing, AI and graphics applications. Synopsys' DesignWare HBM3 Controller and PHY IP, built on silicon-proven HBM2E IP, leverage Synopsys' interposer expertise to provide a low-risk solution that enables high memory bandwidth at up to 921 GB/s.

The Synopsys verification solution, including Verification IP with built-in coverage and verification plans, off-the-shelf HBM3 memory models for ZeBu emulation, and HAPS prototyping system, accelerates verification from HBM3 IP to SoCs. To accelerate development of HBM3 system designs, Synopsys' 3DIC Compiler multi-die design platform provides a fully integrated architectural exploration, implementation and system-level analysis solution.

The Chinese Electronics company Jingjia Micro have recently completed the tapeout of their JM9 GPU series almost 2 years after they first announced the lineup. The JM9 series will consist of two GPUs with the entry-level JM9231 targeting GTX 1050 performance while the higher-end JM9271 aims for the GTX 1080. The JM9231 is stated to feature a clock speed above 1.5 GHz, 8 GB of GDDR5 memory, and will provide 2 TFLOPS of performance within a 150 W TDP through a PCIe Gen3 x16 interface. The JM9271 increases the clock speed to above 1.8 GHz and is paired with 16 GB of HBM memory which should offer 8 TFLOPS of single-precision performance to rival the GTX 1080. The card manages to do this within a TDP package of 200 W and also includes PCIe Gen4 x16 support. The two cards both support HDMI 2.0 in addition to DisplayPort 1.3 for the JM9231 and DisplayPort 1.4 for the JM9271.

While the JM9271 may target GTX 1080 performance it only features OpenGL and OpenCL API support lacking DirectX or Vulkan compatibility greatly reducing its use for gaming. The cards were originally expected to be available in 2020 but after various delays they are now ready to enter production. These products are highly unlikely to make their way outside of the Chinese mainland and if they did we wouldn't expect them to have much impact on the global market.

Intel and AMD released the first Radeon Software drivers for the exotic Radeon Vega M graphics found in Intel NUC8i7HNK and NUC8i7HVK, in over 16 months. The Intel Download Center just added version 21.10.03.11 of Radeon Software for the graphics solution, dated 09/09/2021. The previous drivers dated all the way back to February 2020, and were based on Adrenalin 20.2.

The drivers are based on a release candidate of Adrenalin 21.10, which is 21.10RC1, but does not include the security updates AMD could be bundling with the upcoming 21.10 drivers (October 2021). "Radeon RX Vega M Graphics Driver version 21.10.03.11, which is based on 21.10RC1, does not include the latest functional and security updates. An update is targeted to be released in March of 2022 and will include additional functional and security updates. Customers should update to the latest version as it becomes available," says Intel in the release notes of the drivers. The drivers do include optimization for the latest games, including "Metro Exodus" (DX12), and "Resident Evil Village," besides adding support for Microsoft PlayReady AV1 decode.

DOWNLOAD: AMD Radeon Vega M drivers for Intel NUC8i7HNK and NUC8i7HVK from Intel

While the server industry transitions to the latest generation of processors based on the x86 platform, the Intel Ice Lake and AMD Milan CPUs entered mass production earlier this year and were shipped to certain customers, such as North American CSPs and telecommunication companies, at a low volume in 1Q21, according to TrendForce's latest investigations. These processors are expected to begin seeing widespread adoption in the server market in 3Q21. TrendForce believes that Ice Lake represents a step-up in computing performance from the previous generation due to its higher scalability and support for more memory channels. On the other hand, the new normal that emerged in the post-pandemic era is expected to drive clients in the server sector to partially migrate to the Ice Lake platform, whose share in the server market is expected to surpass 30% in 4Q21.

Intel today, in its 2021 International Supercomputing Conference presentation, revealed that certain next-generation Xeon "Sapphire Rapids" SKUs come with on-package high-bandwidth memory (HBM). Given the context of its presentation, these could be special SKUs designed for high-density HPC setups, in which the processor package includes certain amount of "PMEM" (package memory), besides the processor's 8-channel DDR5 memory interface.

The size of the HBM PMEM, and its position in the memory hierarchy, were detailed, too. Given its high-density applications, PMEM may not serve as a victim cache for the processor, but rather be capable of serving as main memory, with none of the DDR5 DRAM channels populated with DIMMs. On machines with DIMMs, the PMEM will serve as a victim cache for the processor's on-die last-level cache, accelerating the memory I/O. "The next-generation of Intel Xeon Scalable processors (code-named "Sapphire Rapids) will offer integrated High Bandwidth Memory (HBM), providing a dramatic boost in memory bandwidth and a significant performance improvement for HPC applications that operate memory bandwidth-sensitive workloads. Users can power through workloads using just High Bandwidth Memory or in combination with DDR5," says Intel.

At the 2021 International Supercomputing Conference (ISC) Intel is showcasing how the company is extending its lead in high performance computing (HPC) with a range of technology disclosures, partnerships and customer adoptions. Intel processors are the most widely deployed compute architecture in the world's supercomputers, enabling global medical discoveries and scientific breakthroughs. Intel is announcing advances in its Xeon processor for HPC and AI as well as innovations in memory, software, exascale-class storage, and networking technologies for a range of HPC use cases.

"To maximize HPC performance we must leverage all the computer resources and technology advancements available to us," said Trish Damkroger, vice president and general manager of High Performance Computing at Intel. "Intel is the driving force behind the industry's move toward exascale computing, and the advancements we're delivering with our CPUs, XPUs, oneAPI Toolkits, exascale-class DAOS storage, and high-speed networking are pushing us closer toward that realization."

During this year's ISC 2021 event, as a part of the company's exhibition portfolio, NVIDIA has decided to launch an updated version of the A100 accelerator. A couple of months ago, in November, NVIDIA launched an 80 GB HBM2E version of the A100 accelerator, on the SXM2 proprietary form-factor. Today, we are getting the same upgraded GPU in the more standard dual-slot PCIe type of card. Featuring a GA100 GPU built on TSMC's 7 nm process, this SKU has 6192 CUDA cores present. To pair with the beefy amount of computing, the GPU needs appropriate memory. This time, there is as much as 80 GB of HBM2E memory. The memory achieves a bandwidth of 2039 GB/s, with memory dies running at an effective speed of 3186 Gbps. An important note is that the TDP of the GPU has been lowered to 250 Watts, compared to the 400 Watt SXM2 solution.

To pair with the new upgrade, NVIDIA made another announcement today and that is an enterprise version of Microsoft's DirectStorage, called NVIDIA GPUDirect Storage. It represents a way of allowing applications to access the massive memory pool built on the GPU, with 80 GB of super-fast HBM2E memory.

Today we've got the first genuine piece of information that confirms AMD's MCM approach to CDNA2, the next-gen compute architecture meant for ML/HPC/Exascale computing. This comes courtesy of a Linux kernel update, where AMD engineers annotated the latest Linux kernel patch with some considerations specific for their upcoming Aldebaran, CDNA2-based compute cards. Namely, the engineers clarify the existence of a "Die0" and a "Die1", where power data fetching should be allocated to Die0 of the accelerator card - and that the power limit shouldn't be set on the secondary die.

This confirms that Aldebaran will be made of at least two CDNA2 compute dies, and as (almost) always in computing, one seems to be tasked with general administration of both compute dies. It is unclear as of yet whether the HBM2 memory controller will be allocated to the primary die, or if there will be an external I/O die (much like in Zen) that AMD can leverage for off-chip communication. AMD's approach to CDNA2 will eventually find its way (in an updated form) for AMD's consumer-geared next-generation graphics architecture with RDNA3.