Intel today, in its 2021 International Supercomputing Conference presentation, revealed that certain next-generation Xeon "Sapphire Rapids" SKUs come with on-package high-bandwidth memory (HBM). Given the context of its presentation, these could be special SKUs designed for high-density HPC setups, in which the processor package includes certain amount of "PMEM" (package memory), besides the processor's 8-channel DDR5 memory interface.

The size of the HBM PMEM, and its position in the memory hierarchy, were detailed, too. Given its high-density applications, PMEM may not serve as a victim cache for the processor, but rather be capable of serving as main memory, with none of the DDR5 DRAM channels populated with DIMMs. On machines with DIMMs, the PMEM will serve as a victim cache for the processor's on-die last-level cache, accelerating the memory I/O. "The next-generation of Intel Xeon Scalable processors (code-named "Sapphire Rapids) will offer integrated High Bandwidth Memory (HBM), providing a dramatic boost in memory bandwidth and a significant performance improvement for HPC applications that operate memory bandwidth-sensitive workloads. Users can power through workloads using just High Bandwidth Memory or in combination with DDR5," says Intel.