Intel Foundry Announces Reference Workflows from Ansys, Cadence, Siemens, and Synopsys
Today marks a new milestone in the growth of Intel Foundry's design ecosystem as key partners Ansys, Cadence, Siemens, and Synopsys have announced the availability of reference flows for Intel's embedded multi-die interconnect bridge (EMIB) advanced packaging technology. This comes on the heels of recent announcements where those same partners declared readiness for Intel 18A designs. "Today's news shows how Intel Foundry continues to combine the best of Intel with the best of our ecosystem to help our customers realize their AI systems ambitions," said Suk Lee, vice president for Ecosystem Development, Intel Foundry.
The success of Intel Foundry is rooted in collaboration with a vibrant design ecosystem. This ensures customers can access our leading process and packaging technologies. Now, in collaboration with our ecosystem partners, we are making it as easy and as fast as possible for companies to optimize, fabricate and assemble their system-on-chip designs through our foundries, while enabling their designers with validated EDA tools, design flows and IP portfolios for silicon-through-package design. This systems foundry approach allows our customers to innovate at every layer of the stack so they can meet the complex computing demands of the AI era, where chip architectures increasingly rely on multiple CPUs, GPUs and NPUs in a package to achieve performance requirements.
The success of Intel Foundry is rooted in collaboration with a vibrant design ecosystem. This ensures customers can access our leading process and packaging technologies. Now, in collaboration with our ecosystem partners, we are making it as easy and as fast as possible for companies to optimize, fabricate and assemble their system-on-chip designs through our foundries, while enabling their designers with validated EDA tools, design flows and IP portfolios for silicon-through-package design. This systems foundry approach allows our customers to innovate at every layer of the stack so they can meet the complex computing demands of the AI era, where chip architectures increasingly rely on multiple CPUs, GPUs and NPUs in a package to achieve performance requirements.