Apple is reportedly considering diversifying its chip manufacturing strategy with a new silicon manufacturer: Intel. While the upcoming iPhone 17 series, expected next year, will likely feature A19 chips produced by TSMC, a recent rumor from Chinese leaker Fixed Focus Digital hints at a potential switch to Intel for the A20 chipsets powering the 2026 iPhone 18 series. The A18 and A18 Pro chipsets debuted alongside the iPhone 16 series in September 2024, manufactured using TSMC's N3E node. Apple's A19 chips are expected to upgrade to TSMC's N3P node. According to the source, Apple is seeking an Intel 20A node. However, since the A20 node is canceled in favor of 18A, Apple could be an Intel Foundry customer for either 18A or 14A nodes.

Despite the buzz, skepticism persists. Intel has historically struggled with process node transitions and even outsourced production of its Arrow Lake CPUs to TSMC, raising questions about its readiness to deliver on Apple's demands. On the other hand, alternative reports suggest Apple might stick with TSMC's yet-unnamed 2 nm node for the A20, maintaining continuity in its supply chain. As the iPhone 18 series remains two years away, much can change. For now, we are left speculating whether this rumored collaboration with Intel represents a new chapter in Apple's chipset innovation or just a rumor with little substance. If the US government mandates more domestic production, chip designers could be looking at some of the more local manufacturing options, like Intel does on US soil. That could force Apple, NVIDIA, AMD, and Qualcomm to look into Intel's offerings.

According to Taiwanese media Commercial Times, Intel is significantly increasing its outsourcing of "Arrow Lake" CPU production to TSMC, a strategic move as it grapples with persistent issues in its own foundry division. This decision to outsource a substantial portion of Arrow Lake's production is a significant shift in Intel's strategy, showing the company's rising reliance on external partners to meet quality and performance demands. The Arrow Lake Core Ultra 200 series is Intel's first major outsourcing initiative, in which Intel gave its core IP to third-party foundries, more specifically for a 3 nm node at TSMC. However, it clearly indicates the performance gaps in Intel's own Intel Foundry and the high demand expectations for the new CPUs. Originally intended to use Intel 20A node, Intel shifted focus of 18A node for its products and upcoming foundry customers.

Intel's recent orders with TSMC extend to its upcoming Lunar Lake chips and next-generation Falcon Shores AI GPUs, both of which will use TSMC's 3 nm process. Although Intel's 18A node remains promising, the company relies on current products to sustain its revenue streams, making TSMC's support crucial in ensuring timely shipments. This increased outsourcing reflects Intel's need to maintain competitive performance in the short term. Once its Foundry division meets performance and capacity targets, Intel aims to bring more CPU manufacturing back in-house. However, if anything goes wrong, Intel could face challenges securing sufficient volume from TSMC, as the foundry has longstanding commitments with major clients like Apple, NVIDIA, Qualcomm, and AMD.

Intel has announced the cancellation of its 20A node for Foundry customers, as well as shifting majority of Arrow Lake production to external foundries. The tech giant will instead focus its resources on the more advanced 18A node while relying on external partners for Arrow Lake production, likely tapping TSMC or Samsung for their 2 nm nodes. The decision follows Intel's successful release of the 18A Process Design Kit (PDK) 1.0 in July, which garnered positive feedback from the ecosystem, according to the company. Intel reports that the 18A node is already operational, booting operating systems and yielding well, keeping the company on track for a 2025 launch. This early success has enabled Intel to reallocate engineering resources from 20A to 18A sooner than anticipated. As a result, the "Arrow Lake processor family will be built primarily using external partners and packaged by Intel Foundry".

The 20A node, while now cancelled for Arrow Lake, has played a crucial role in Intel's journey towards 18A. It served as a testbed for new techniques, materials, and transistor architectures essential for advancing Moore's Law. The 20A node successfully integrated both RibbonFET gate-all-around transistor architecture and PowerVia backside power delivery for the first time, providing valuable insights that directly informed the development of 18A. Intel's decision to focus on 18A is also driven by economic factors. With the current 18A defect density already at D0 <0.40, the company sees an opportunity to optimize its engineering investments by transitioning now. However, challenges remain, as evidenced by recent reports of Broadcom's disappointment in the 18A node. Despite these hurdles, Intel remains optimistic about the future of its foundry services and the potential of its advanced manufacturing processes. The coming months will be crucial as the company works to demonstrate the capabilities of its 18A node and secure more partners for its foundry business.

Intel announced that it has postponed the 2024 edition of its Innovation event to 2025. Among other things, the first-party event showcases innovations from the company's various business units made in the preceding year, includes a few key product launches, and teasers for what's next. The Innovation 2024 was poised to be particularly important for the company, as it was expected to launch its next generation Core Ultra "Arrow Lake" processors not just for mobiles, but even the desktop platform. Other key product showcase items include Xeon 6 server processors, and Gaudi 3 AI accelerator, besides updates from the company's foundry business, particularly the Intel 20A and Intel 18A nodes.

Intel's postponement of Innovation 2024 can be seen as a move to demonstrate sincerity that the company working to meet its goal of cutting cost of revenue by $10 billion through FY 2024, something that will bear results by mid-2025. It would have probably felt inappropriate for the company to host a lavish product showcase event in light of this. That said, there's no word on how this affects launch of products such as Core Ultra "Arrow Lake," it's possible that the company may launch them in a low-key dedicated media presentation.

In a conversation with Intel's CEO Pat Gelsinger, industry analyst Patrick Moorhead revealed that Intel's Meteor Lake CPU platform suffers from some production issues. More specifically, Intel has been facing some yield and/or back-end production issues with its Meteor Lake platform, resulting in a negative impact on Intel's margins when producing the chip. The market is showing great demand for these chips, and Intel has been forced to run productions of "hot lots"-- batch production of silicon with the highest priority that gets moved to the front of the production line so they can get packaged as fast as possible. While this is a good sign that the demand is there, running hot lots increases production costs overall as some other wafers have to go back so Meteor Lake can pass.

The yield issues associated with Meteor Lake could be stemming from the only tile made by Intel in the MTL package: the compute tile made on the Intel 4 process. Intel 4 process is specific to Meteor Lake. No other Intel product uses it, not even the Xeon 6, which uses Intel 3, or any of the upcoming CPUs like Arrow Lake, which uses the Intel 20A node. So, Intel is doing multiple nodes for multiple generations of processors, further driving up costs as typical high-volume production with a single node for multiple processors yields lower costs. Additionally, the company is left with lots of "wafers to burn" with Intel 4 node, so even with Meteor Lake having yield issues, the production is ultimately fine, while the operating costs and margins take a hit.

Intel is rumored to be preparing to tease its Core Ultra 2-series "Arrow Lake" processor at the 2024 Computex, which gets underway this June. The series itself isn't expected to launch before Q4-2024, but Computex is the only major global event between June and January for Intel to unveil or tease its next-generation processor, so here we are. At this point we don't know which exact platform of "Arrow Lake" Intel is planning to tease—whether these are the mobile variants, or the Socket LGA1851 desktop "Arrow Lake-S." An unveiling of the latter would almost definitely entail PC motherboard vendors being allowed to show off their first compatible motherboards at Computex—the perfect platform for them to do so.

The Core Ultra "Arrow Lake" retains a Foveros Tiled (chiplet) construction of "Meteor Lake," but with advancements to the chip's Compute tile, which is built on the Intel 20A foundry node, and rocks new "Lion Cove" P-cores and "Skymont" E-cores; an updated I/O tile, and an iGPU based on the updated Xe-LPG+ graphics architecture. Since the processor now serves practically all PCH functions, the mobile "Arrow Lake" is a single-chip solution, whereas the desktop "Arrow Lake-S" is expected to remain 2-chip. There will be more I/O from the CPU, though, which is why the socket has 151 more pins than the LGA1700.

In a move that could intensify competition with Intel in the cutting-edge chip manufacturing space, Samsung Foundry has reportedly decided to rebrand its second-generation 3 nm-class fabrication technology, previously known as SF3, to a 2 nm-class manufacturing process called SF2. According to reports from ZDNet, the renaming of Samsung's SF3 to SF2 is likely an attempt by the South Korean tech giant to simplify its process nomenclature and better compete against Intel Foundry, at least visually. Intel is set to roll out its Intel 20A production node, a 2 nm-class technology, later this year. The reports suggest that Samsung has already notified its customers about the changes in its roadmap and the renaming of SF3 to SF2. Significantly, the company has reportedly gone as far as re-signing contracts with customers initially intended to use the SF3 production node.

"We were informed by Samsung Electronics that the 2nd generation 3 nm [name] is being changed to 2 nm," an unnamed source noted to ZDNet. "We had contracted Samsung Foundry for the 2nd generation 3 nm production last year, but we recently revised the contract to change the name to 2 nm." Despite the name change, Samsung's SF3, now called SF2, has not undergone any actual process technology alterations. This suggests that the renaming is primarily a marketing move, as using a different process technology would require customers to rework their chip designs entirely. Samsung intends to start manufacturing chips based on the newly named SF2 process in the second half of 2024. The SF2 technology, which employs gate-all-around (GAA) transistors that Samsung brands as Multi-Bridge-Channel Field Effect Transistors (MBCFET), does not feature a backside power delivery network (BSPDN), a significant advantage of Intel's 20A process. Samsung Foundry has not officially confirmed the renaming.

Over the weekend, there have been a series of leaks from sources such as Golden Pig Upgrade, and High Yield YT, surrounding Intel's next-generation desktop processor, the Core Ultra 2-series "Arrow Lake-S." The lineup is likely to continue the new client processor naming scheme Intel introduced with the Core Ultra 1-series "Meteor Lake" on the mobile platform. "Arrow Lake-S" is rumored to debut the new Socket LGA1851, which retains cooler-compatibility with LGA1700. Although Intel has nucleated all I/O functions of the traditional PCH to "Meteor Lake," making it a single-chip solution on the mobile platform; and although the mobile "Arrow Lake" will continue to be single-chip; the desktop "Arrow Lake-S" will be a 2-chip solution. This is mainly because the desktop platform demands a lot more PCIe lanes, for a larger number of NVMe storage devices, or high bandwidth devices such as Thunderbolt and USB4 hubs, etc.

Another key finding in this latest series of leaks, is that unlike "Meteor Lake," the desktop "Arrow Lake-S" will do away with low-power island E-cores located in the SoC tile of the processor. All CPU cores are located in the Compute tile, which is expected to be built in the Intel 20A foundry node—the company's first node to implement GAAFETs (nanosheets), with backside power delivery; as well as an advanced 2nd generation EUV lithography. Intel's 1st Gen EUV is used on the current FinFET-based Intel 4 and Intel 3 foundry nodes.

According to a Bloomberg report, Intel is seeking to raise at least $2 billion in equity funding from investors for expanding its fabrication facility in Leixlip, Ireland, known as Fab 34. The chipmaker has hired an advisor to find potential investors interested in providing capital for the project. Fab 34 is currently Intel's only chip plant in Europe that uses cutting-edge extreme ultraviolet (EUV) lithography. It produces processors on the Intel 4 process node, including compute tiles for Meteor Lake client CPUs and expected future Xeon data center chips. While $2 billion alone cannot finance the construction of an entirely new fab today, it can support meaningful expansion or upgrades of existing capacity. Intel likely aims to grow Fab 34's output and/or transition it to more advanced 3 nm-class technologies like Intel 3, Intel 20A, or Intel 18A.

Expanding production aligns with Intel's needs for its own products and its Intel Foundry Services business, providing contract manufacturing. Intel previously secured a $15 billion investment from Brookfield Infrastructure for its Arizona fabs in exchange for a 49% stake, demonstrating the company's willingness to partner to raise capital for manufacturing projects. The Brookfield deal also set a precedent of using outside financing to supplement Intel's own spending budget. It provided $15 billion in effectively free cash flow Intel can redirect to other priorities like new fabs without increasing debt. Intel's latest fundraising efforts for the Ireland site follow a similar equity investment model that leverages outside capital to support its manufacturing expansion plans. Acquiring High-NA EUV machinery for manufacturing is costly, as these machines can reach up to $380 million alone.

Intel in its 2024 International CES presentation, unveiled its two new upcoming client microarchitectures, "Arrow Lake" and "Lunar Lake." Michelle Johnston Holthaus, EVP and GM of Intel's client computing group (CCG), in her keynote address, held up a next-generation Core Ultra "Lunar Lake" chip. This is the Lunar Lake-MX package, with MOP (memory on package). You have a Foveros base tile resembling "Meteor Lake," with on-package LPDDR5x memory stacks. With "Lunar Lake," Intel is reorganizing components across its various Foveros tiles—the Compute and Graphics tiles are combined into a single tile built on an Intel foundry node that's possibly the Intel 20A (we have no confirmation); and a smaller SoC tile that has all of the components of the current "Meteor Lake" SoC tile, and is possibly built on a TSMC node, such as N3.

"Lunar Lake" will pick up the mantle from "Meteor Lake" in the U-segment and H-segment (that's ultraportables, and thin-and-light), when it comes out later this year (we predict in the second half of 2024), with Core Ultra 2-series branding. Intel also referenced "Arrow Lake," which could finally bring light to the sluggish pace of development in its desktop segment. When it comes out later this year, "Arrow Lake" will debut Socket LGA1851, "Arrow Lake" will bring the AI Boost NPU to the desktop, along with Arc Xe-LPG integrated graphics. The biggest upgrade of course will be its new Compute tile, with its "Lion Cove" P-cores, and "Skymont" E-cores, that possibly offer a large IPC uplift over the current combination of "Raptor Cove" and "Gracemont" cores on the "Raptor Lake" silicon. It's also possible that Intel will try to bring "Meteor Lake" with its 6P+8E Compute tile, Xe-LPG iGPU, and NPU, to the LGA1851 socket, as part of some mid-range processor models. 2024 will see a Intel desktop processor based on a new architecture, which is the big takeaway here.

Marking a milestone in Intel's ongoing manufacturing expansion in Arizona, the company today announced that the initial portion of the cleanroom is "weather tight" and the "blow down" phase has begun at the company's two new leading-edge chip factories on its Ocotillo campus in Chandler, Arizona. This milestone underscores Intel's dedication to advancing its presence in the state and fostering technological innovation.

"Our commitment to Arizona runs deep, and as we expand our operations, we remain dedicated to addressing the growing demand for semiconductors and helping the United States regain its leadership position in this vital industry. This milestone represents the result of great teamwork, proficient teams and exceptional craftsmanship of the tradespeople, and it's thanks to their hard work that we've made such significant progress on our site while keeping our culture of caring and the safety of all as our top priority." -Dan Doron, Intel vice president and general manager of Fab Construction Enterprise

Thanks to the 3D renders and technical drawings obtained by Igor's Lab, we have insights into the structure of Intel's next-generation LGA-1851 socket for Arrow Lake processors. Scheduled to arrive in mid-2024, the LGA-1851 socket was originally intended for Meteor Lake-S desktop processors. However, the socket is now awaiting Arrow Lake since Meteor Lake is now a mobile-only processor generation. The first notable thing about LGA-1851 is that it will directly connect a dedicated PCIe 5.0 x4 interface to the CPU, besides the x16 lanes going to the GPU. This results in native support for high-speed PCIe 5.0 NVMe SSDs that can achieve speeds of over 12 GB/s in both read and write workloads.

Intel Arrow Lake-S will be available with eight P-cores and 16 E-cores in SKUs with different combinations of the two. The accompanying 800 series chipset includes Z890, B860, and H810 models, with an evident absence of H870 SKU. There will be W880 and Q870 workstation-grade chipsets as well. It is worth pointing out that Arrow Lake will enable DRAM capacities of up to 48 GB per DIMM at 6400 MT/s. We expect to hear more about Arrow Lake-S as we near the 2024 launch date and we get to see the Intel 20A node being used in client products. Below, you can see the technical drawings of the Independent Loading Mechanism (ILM) and chipset 3D models.

Intel at the 2023 InnovatiON event surprised audiences with a live demo of a reference notebook powered by a Core "Lunar Lake" processor. What's surprising about this is that "Lunar Lake" won't come out until 2025 (at least), and succeeds not just the upcoming "Meteor Lake" architecture, but also its succeeding "Arrow Lake," which debuts in 2024. Intel is expected to debut "Meteor Lake" some time later this year. What's also surprising is that Intel has proven that the Intel 18A foundry node works. The Compute tile of "Lunar Lake" is expected to be based on Intel 18A, which is four generations ahead of the current Intel 7, which will be succeeded by Intel 4, Intel 3, and Intel 20A along the way.

The demo focused on the generative AI capabilities of Intel's third generation NPU, the hardware backend of AI Boost. Using a local session of a tool similar to Stable Diffusion, the processor was made to generate the image of a giraffe wearing a hat; and a GPT program was made to pen the lyrics of a song in the genre of Taylor Swift from scratch. Both tasks were completed on stage using the chip's NPU, and in timeframes you'd normally expect from discrete AI accelerators or cloud-based services.

Intel Corporation today reported second-quarter 2023 financial results. "Our Q2 results exceeded the high end of our guidance as we continue to execute on our strategic priorities, including building momentum with our foundry business and delivering on our product and process roadmaps," said Pat Gelsinger, Intel CEO. "We are also well-positioned to capitalize on the significant growth across the AI continuum by championing an open ecosystem and silicon solutions that optimize performance, cost and security to democratize AI from cloud to enterprise, edge and client."

David Zinsner, Intel CFO, said, "Strong execution, including progress towards our $3 billion in cost savings in 2023, contributed to the upside in the quarter. We remain focused on operational efficiencies and our Smart Capital strategy to support sustainable growth and financial discipline as we improve our margins and cash generation and drive shareholder value." In the second quarter, the company generated $2.8 billion in cash from operations and paid dividends of $0.5 billion.

Today, Intel announced a strategic collaboration agreement with Ericsson to utilize Intel's 18A process and manufacturing technology for Ericsson's future next-generation optimized 5G infrastructure. As part of the agreement, Intel will manufacture custom 5G SoCs (system-on-chip) for Ericsson to create highly differentiated leadership products for future 5G infrastructure. Additionally, the companies will expand their collaboration to optimize 4th Gen Intel Xeon Scalable processors with Intel vRAN Boost for Ericsson's Cloud RAN (radio access network) solutions to help communications service providers increase network capacity and energy efficiency while gaining greater flexibility and scalability.

"As our work together evolves, this is a significant milestone with Ericsson to partner broadly on their next-generation optimized 5G infrastructure. This agreement exemplifies our shared vision to innovate and transform network connectivity, and it reinforces the growing customer confidence in our process and manufacturing technology," said Sachin Katti, senior vice president and general manager of the Network and Edge group at Intel. "We look forward to working together with Ericsson, an industry leader, to build networks that are open, reliable and ready for the future."

Intel is about to turn chipmaking upside down with PowerVia, a new approach to delivering power that required a radical rethink to both how chips are made and how they are tested. For all the modern history of computer chips, they've been built like pizzas—from the bottom up, in layers. In the case of chips, you start with the tiniest features, the transistors, and then you build up increasingly less-tiny layers of wires that connect the transistors and different parts of the chip (these are called interconnects). Included among those top layers are the wires that bring in the power that makes the chip go.

When the chip is done, you flip it over, enclose it in packaging that provides connections to the outer world, and you're ready to put it in a computer. Unfortunately, this approach is running into problems. As they get smaller and denser, the layers that share interconnects and power connections have become an increasingly chaotic web that hinders the overall performance of each chip. Once an afterthought, "now they have a huge impact," says Ben Sell, vice president of Technology Development at Intel and part of the team that brought PowerVia to fruition. In short, power and signals fade, requiring workarounds or simply dumping more power in.

At VLSI Symposium 2023, scheduled to take place between June 11-16, Intel is set to demonstrate its PowerVia technology working efficiently on an E-Core chip built using the Intel 4 node. Conventional chips have power and signal interconnects distributed across multiple metal layers. PowerVia, on the other hand, dedicates specific layers for power delivery, effectively separating them from the signal routing layers. This approach allows for vertical power delivery through a set of power-specific Through-Silicon Vias (TSVs) or PowerVias, which are essentially vertical connections between the top and bottom surfaces of the chip. By delivering power directly from the backside of the chip, PowerVia reduces power supply noise and resistive losses, optimizing power distribution and improving overall energy efficiency. PowerVia is set to make a debut in 2024 with Intel 20A node.

For VLSI Symposium 2023 talk, the company has prepared a paper that highlights a design made using Intel 4 technology and implements E-Cores only in a test chip. The document states: "PowerVia Technology is a novel innovation to extend Process Scaling by having Power Delivery on the backside. This paper presents the pre and post silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of greater than 90 percent in large areas of the core while showing greater than 5 percent frequency benefit in silicon due reduced IR drop. Successful Post silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristics of the PowerVia testchip is inline with higher power densities expected from logic scaling."

Intel Corporation today reported first-quarter 2023 financial results. "We delivered solid first-quarter results, representing steady progress with our transformation," said Pat Gelsinger, Intel CEO. "We hit key execution milestones in our data center roadmap and demonstrated the health of the process technology underpinning it. While we remain cautious on the macroeconomic outlook, we are focused on what we can control as we deliver on IDM 2.0: driving consistent execution across process and product roadmaps and advancing our foundry business to best position us to capitalize on the $1 trillion market opportunity ahead."

David Zinsner, Intel CFO, said, "We exceeded our first-quarter expectations on the top and bottom line, and continued to be disciplined on expense management as part of our commitment to drive efficiencies and cost savings. At the same time, we are prioritizing the investments needed to advance our strategy and establish an internal foundry model, one of the most consequential steps we are taking to deliver on IDM 2.0."

Intel Foundry Services, the in-house semiconductor foundry of Intel, announced that its 2 nm-class Intel 20A and 1.8 nm-class Intel 18A foundry nodes have completed development, and are on course for mass-producing chips on their roadmap dates. Chips are expected to begin mass-production on the Intel 20A node in the first half of 2024, while those on the Intel 18A node are expected to begin in the second half of 2024. The completion of the development phase means that Intel has finalized the specifications and performance/power targets of the nodes, the tools and software required to make the chips, and can now begin ordering them to build the nodes. Intel has been testing these nodes through 2022, and with the specs being finalized, chip-designers can accordingly wrap up development of their products to align with what these nodes have to offer.

Intel 20A (or 20-angstrom, or 2 nm) node introduces gates-all-around (GAA) RibbonFET transistors with PowerVIAs (an interconnect innovation that contributes to transistor densities). The Intel 20A node is claimed to offer a 15% performance/Watt gain over its predecessor, the Intel 3 node (FinFET EUV, 3 nm-class), which by itself offers an 18% performance/Watt gain over Intel 4 (20% perf/Watt gain over the current Intel 7 node), the node that is entering mass-production very soon. The Intel 18A node is a further refinement of Intel 20A, and introduces a design improvement to the RibbonFET that increases transistor density at scale, and a claimed 10% performance/Watt improvement over Intel 20A.

Intel Corporation today reported fourth-quarter and full-year 2022 financial results. The company also announced that its board of directors has declared a quarterly dividend of $0.365 per share on the company's common stock, which will be payable on March 1, 2023, to shareholders of record as of February 7, 2023.

"Despite the economic and market headwinds, we continued to make good progress on our strategic transformation in Q4, including advancing our product roadmap and improving our operational structure and processes to drive efficiencies while delivering at the low-end of our guided range," said Pat Gelsinger, Intel CEO. "In 2023, we will continue to navigate the short-term challenges while striving to meet our long-term commitments, including delivering leadership products anchored on open and secure platforms, powered by at-scale manufacturing and supercharged by our incredible team."

Keeping up with the cadence of two generations of desktop processors per socket, Intel will turn the page of the current LGA1700, with the introduction of the new Socket LGA1851. The processor package will likely have the same dimensions as LGA1700, and the two sockets may share cooler compatibility. The first processor microarchitecture to debut on LGA1851 will be the 14th Gen Core "Meteor Lake-S." These chips will feature a generationally lower CPU core-count compared to "Raptor Lake," but significantly bump the IPC on both the P-cores and E-cores.

"Raptor Lake" is Intel's final monolithic silicon client processor before the company pivots to chiplets built on various foundry nodes, as part of its IDM 2.0 strategy. The client-desktop version of "Meteor Lake," dubbed "Meteor Lake-S," will have a maximum CPU core configuration of 6P+16E (that's 6 performance cores with 16 efficiency cores). The chip has 6 "Redwood Cove" P-cores, and 16 "Crestmont" E-cores. Both of these are expected to receive IPC uplifts, such that the processor will end up faster (and hopefully more efficient) than the top "Raptor Lake-S" part. Particularly, it should be able to overcome the deficit of 2 P-cores.

Intel Corporation today reported third-quarter 2022 financial results. "Despite the worsening economic conditions, we delivered solid results and made significant progress with our product and process execution during the quarter," said Pat Gelsinger, Intel CEO. "To position ourselves for this business cycle, we are aggressively addressing costs and driving efficiencies across the business to accelerate our IDM 2.0 flywheel for the digital future."

"As we usher in the next phase of IDM 2.0, we are focused on embracing an internal foundry model to allow our manufacturing group and business units to be more agile, make better decisions and establish a leadership cost structure," said David Zinsner, Intel CFO. "We remain committed to the strategy and long-term financial model communicated at our Investor Meeting."

The US Government has instituted a ban on supply of GAA-FET EDA software to China (the Chinese government and companies in China). Humans can no longer design every single circuit on chips with tens of billions of transistors, and so EDA (electronics design automation) software is used to micromanage design based broadly on what chip architects want. Synopsys, Cadence, and Siemens are major EDA software suppliers. Intel is rumored to use an in-house EDA software that it doesn't sell, although this could change with the company roping in third-party foundries, such as TSMC, for cutting-edge logic chips (which will need the software to make sense of Intel's designs).

GAA or "gates-all-around" technology is vital to building transistors in the 3 nm and 2 nm silicon fabrication nodes. Samsung is already using GAA for its 3 nm node, while TSMC intends to use it with its 2N (2 nm) node. Intel is expected to use it with its Intel 20A (20 angstrom, or 2 nanometers) node. Both Intel and TSMC will debut nodes powered by GAAFETs for mass-production in 2024. The US Government has already banned the sales of EUV lithography machines to China, as well as machines fabricating 3D NAND flash chips with greater than 128 layers or 14 nm. In the past, technology embargoes have totally stopped China from copying or reverse-engineering western tech, or luring Taiwanese engineers armed with industry secrets away on the promise of wealth and a comfortable life in the Mainland.

Le Comptoir du Hardware scored a die-shot of a 2P+8E core variant of the "Meteor Lake" compute tile, and Locuza annotated it. "Meteor Lake" will be Intel's first processor to implement the company's IDM 2.0 strategy to the fullest. The processor is a multi-chip module of various tiles (chiplets), each with a certain function, sitting on die made on a silicon fabrication node most suitable to that function. Under this strategy, for example, if Intel's chip-designers calculate that the iGPU will be the most power-hungry component on the processor, followed by the CPU cores, the graphics tile will be built on a more advanced process than the compute tile. Intel's "Meteor Lake" and "Arrow Lake" processors will implement chiplets built on the Intel 4, TSMC N3, and Intel 20A fabrication nodes, each with unique power and transistor-density characteristics. Learn more about the "Meteor Lake" MCM in our older article.

The 2P+8E (2 performance cores + 8 efficiency cores) compute tile is one among many variants of compute tiles Intel will develop for the various SKUs making up the next-generation Core mobile processor series. The die is annotated with the two large "Redwood Cove" P-cores and their cache slices taking up about 35% of the die area; and the two "Crestmount" E-core clusters (each with 4 E-cores), and their cache slices, taking up the rest. The two P-cores and two E-core clusters are interconnected by a Ring Bus, and share an L3 cache. The size of each L3 cache slice is either 2.5 MB or 3 MB. At 2.5 MB, the total L3 cache will be 10 MB, and at 3 MB, it will be 12 MB. As with all past generations, the L3 cache is fully accessible by all CPU cores in the compute tile.

Intel is designing a "Halo" SKU of a future generation of mobile processors with a goal to match Apple's in-house silicon of the time. Slated for tape-out some time in 2023, with mass-production expected in 2024, the 15th Generation Core "Arrow Lake-P Halo" processor is being designed specifically to compete with Apple's "premium 14-inch laptop" (presumably the MacBook Pro) that the company could have around 2024, based on an in-house Apple silicon. This is to essentially tell its notebook partners that they will have an SoC capable of making their devices in the class truly competitive. Apple relies on a highly scaled out Arm-based SoC based on in-house IP blocks, with a software that's closely optimized for it. Intel's effort appears to chase down its performance and efficiency.

The Core "Arrow Lake" microarchitecture succeeds the 14th Gen "Meteor Lake." It is a multi-chip module (MCM) of three distinct dies built on different fabrication nodes, in line with the company's IDM 2.0 strategy. These nodes are Intel 4 (comparable to TSMC N7 or N6), Intel 20A (comparable to TSMC N5), and an "external" 3 nm-class node that's just the TSMC N3. The compute tile, or the die which houses the CPU cores, combines a hybrid CPU setup of 6 P-cores, and 8 E-cores. The performance cores are likely successors of the "Redwood Cove" P-cores powering the "Meteor Lake" compute tiles. Intel appears to be using one kind of E-cores across two generations (eg: Gracemont across Alder Lake and Raptor Lake). If this is any indication, Arrow Lake could continue to use "Crestmont" E-cores. Things get interesting with the Graphics tile.