Intel's presentation at the VLSI Symposium in Japan offered a detailed look at the upcoming Intel 18A process, which is set to enter mass production in the second half of 2025. This node combines Gate-All-Around transistors with the PowerVia backside power delivery network, resulting in a completely new metal stack architecture. By routing power through the rear of the die, Intel has been able to tighten interconnect pitches on critical layers while relaxing spacing on the top layer, improving yield and simplifying fabrication. In standardized power, performance, and area tests on an Arm core sub-block, Intel 18A demonstrated roughly 15% higher performance at the same power draw compared to Intel 3. When operating at 1.1 volts, clock speeds increase by up to 25% without incurring additional energy costs, and at around 0.75 volts, performance can rise by 18%, or power consumption can drop by nearly 40%.

Under the hood, the process features significant cell height reductions: performance‑tuned cells measure 180 nanometers tall, while high‑density designs sit at 160 nanometers, both smaller than their predecessors. The front‑side metal layers have been reduced from between 12 and 19 on Intel 3 to between 11 and 16 on Intel 18A, with three additional rear metal layers added for PowerVia support. Pitches on layers M1 through M10 have been tightened from as much as 60 nanometers down to 32 nanometers before easing again in the upper layers. Low-NA EUV exposure is used on layers M0 through M4, cutting the number of masks required by 44% and simplifying the manufacturing flow. Intel plans to debut 18A in its low‑power "Panther Lake" compute chiplet and the efficiency‑core‑only Clearwater Forest Xeon 7 family. A cost-optimized 17-layer variant, a balanced 21-layer option, and a performance-focused 22-layer configuration will address different market segments.

TSMC has decided not to use High-NA EUV lithography for its upcoming angstrom-era A14 node. Instead, the world's largest contract chipmaker will stick with the field-proven 0.33-NA EUV tools. Senior Vice President at TSMC, Kevin Zhang, explained that the choice reflects TSMC's ongoing focus on keeping manufacturing steps straightforward and costs under control. Zhang noted that volume production of A14 chips is slated to begin in 2028, and the company believes it can hit its performance, yield, and density targets all the way through the two-nanometer generation without the need for High-NA equipment. He pointed out that by limiting the number of mask layers from one generation to the next, TSMC can offer customers more affordable solutions without sacrificing complexity where it counts.

This strategy places TSMC in step with Intel Foundry and several DRAM producers, who have already adopted High-NA selectively for their most critical layers. High-NA EUV scanners come with a steep sticker price of $380 million, and they require higher exposure doses and tend to run at lower throughput than standard tools. IBM researchers recently confirmed that a single High-NA exposure can cost up to 2.5 times more than a low-NA shot. Yet, when you compare a four-mask low-NA flow to a single High-NA pass, total wafer costs can drop by roughly 1.7 to 2.1 times. Despite those savings in complex multi-patterning scenarios, analysts at SemiAnalysis still expect full cost parity won't arrive until around 2030. So far, Intel is the only major foundry committed to High-NA for high-volume production. It has already processed over 30,000 trial wafers on its 14A node using ASML's Twinscan EXE:5000 High-NA tool.

Intel has successfully deployed two advanced ASML High-NA Twinscan EXE:5000 EUV lithography systems at its D1 development facility near Hillsboro, Oregon, processing approximately 30,000 wafers in a single quarter. The High-NA EUV systems, each reportedly valued at $380 million, represent a substantial improvement over previous lithography tools, achieving resolution down to 8 nm with a single exposure compared to the 13.5 nm resolution of current Low-NA systems. Early operational data indicates these machines are approximately twice as reliable as previous EUV generations, addressing reliability challenges that previously hampered Intel's manufacturing progress. The ability to accomplish with a single exposure what previously required three exposures and approximately 40 processing steps has been reduced to just "single digit" processing steps.

Intel has historically been an early adopter of high-NA EUV lithography, a much more aggressive strategy than its competitors like TSMC, which manufactures its advanced silicon using low-NA EUV tools. The company plans to utilize these systems for its upcoming 14A chip manufacturing process, though no specific mass production date has been announced. While ASML classifies these Twinscan EXE:5000 systems as pre-production tools not designed for high-volume manufacturing, Intel's extensive wafer processing is more of a test bed. The early adoption provides Intel with valuable development opportunities across various High-NA EUV manufacturing aspects, including photomask glass, pellicles, and specialized chemicals that could establish future industry standards. Intel's current 18A node is utilizing Low-NA lithography tools, where Intel is only exploring High-NA with it for testing, before moving on to 14A high-volume manufacturing with High-NA EUV.

Samsung Electronics is set to make a significant leap in semiconductor manufacturing technology with the introduction of its first High-NA 0.55 EUV lithography tool. The company plans to install the ASML Twinscan EXE:5000 system at its Hwaseong campus between Q4 2024 and Q1 2025, marking a crucial step in developing next-generation process technologies for logic and DRAM production. This move positions Samsung about a year behind Intel but ahead of rivals TSMC and SK Hynix in adopting High-NA EUV technology. The system is expected to be operational by mid-2025, primarily for research and development purposes. Samsung is not just focusing on the lithography equipment itself but is building a comprehensive ecosystem around High-NA EUV technology.

The company is collaborating with several key partners like Lasertec (developing inspection equipment for High-NA photomasks), JSR (working on advanced photoresists), Tokyo Electron (enhancing etching machines), and Synopsys (shifting to curvilinear patterns on photomasks for improved circuit precision). The High-NA EUV technology promises significant advancements in chip manufacturing. With an 8 nm resolution capability, it could make transistors about 1.7 times smaller and increase transistor density by nearly three times compared to current Low-NA EUV systems. However, the transition to High-NA EUV comes with challenges. The tools are more expensive, costing up to $380 million each, and have a smaller imaging field. Their larger size also requires chipmakers to reconsider fab layouts. Despite these hurdles, Samsung aims for commercial implementation of High-NA EUV by 2027.

ASML celebrated an important milestone last week—the company's social media account shared news about their third generation extreme ultraviolet (EUV) lithography tool reaching an unnamed customer: "chipmakers have a need for speed! The first Twinscan NXE:3800E is now being installed in a chip fab. 🔧 With its new wafer stages, the system will deliver leading edge productivity for printing advanced chips. We're pushing lithography to new limits." The post included a couple of snaps—ASML workers were gathered in front of a pair of climatized containers, and Peter Wennink (President and CEO) and Christophe Fouquet (EVP and CBO) thanked staff at company HQ.

The Twinscan NXE:3800E is ASML's latest platform from a series of 0.33 numerical aperture (Low-NA) lithography scanners. Information is scarce—the company has not yet published a 3800E product page. The preceding model—Twinscan NXE:3600D—supports EUV volume production at 3 and 5 nm. ASML roadmaps imply that the Twinscan NXE:3800E has been designed to produce chips on 2 and 3 nm-class technologies. The company's cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools (High-NA Twinscan EXE) are expected to cost around $380 million—reports from last month point to a possible $183 million price point for "existing Low-NA EUV lithography systems." Another Low-NA EUV machine is reported to be lined up for a possible 2026 release window—ASML's next-gen Twinscan NXE:4000F model will co-exist alongside emerging (pricier) High-NA solutions.

Chipmaking manufacturing equipment giant ASML has expressed concerns about staying in the Netherlands and considering expansion into other countries due to its home country's capped possibilities. On Wednesday, ASML executives met with Netherlands Prime Minister Mark Rutte to discuss the company's growth plans. The meeting, however, failed to fully resolve ASML's concerns surrounding the country's stance on skilled foreign labor, leaving uncertainty over the tech giant's expansion in its home market. Being one of the world's largest suppliers to chipmakers, ASML has said it needs to double its operations in the following decade to meet soaring demand. However, the company is hitting roadblocks in the Netherlands, including difficulty obtaining building permits, constraints on the electrical grid, transportation bottlenecks, and a need for supporting infrastructure like hospitals, schools, and housing. A key issue is the Netherlands' ability to attract scarce foreign engineering talent, with over 40% of ASML's Dutch workforce being non-Dutch. Recent parliamentary motions to cap international students and scrap a tax break for skilled migrants have met with criticism from ASML and other tech employers.

In an effort dubbed "Operation Beethoven," the Dutch government is scrambling to address ASML's concerns and prevent the company from expanding abroad, having already seen multinationals like Shell and Unilever leave their home country in recent years. However, ASML CEO Peter Wennink said that while the company prefers to grow in the Netherlands, it can do so elsewhere if needed. The situation comes amid pressure from the US for allies like the Netherlands to tighten restrictions on China's further access to semiconductor technology. As the sole producer of extreme ultraviolet (EUV) lithography machines crucial for advanced chipmaking, like High-NA and Low-NA, ASML holds strategic importance beyond just economics. With a new right-wing Dutch government being formed, whether a compromise can be reached to ensure ASML's continued growth in the Netherlands remains to be seen. The tech giant's decision could significantly affect the Dutch economy and its position in the global chip industry.

ASML has revealed that its cutting-edge High-NA extreme ultraviolet (EUV) chipmaking tools, called High-NA Twinscan EXE, will cost around $380 million each—over twice as much as its existing Low-NA EUV lithography systems that cost about $183 million. The company has taken 10-20 initial orders from the likes of Intel and SK Hynix and plans to manufacture 20 High-NA systems annually by 2028 to meet demand. The High-NA EUV technology represents a major breakthrough, enabling an improved 8 nm imprint resolution compared to 13 nm with current Low-NA EUV tools. This allows chipmakers to produce transistors that are nearly 1.7 times smaller, translating to a threefold increase in transistor density on chips. Attaining this level of precision is critical for manufacturing sub-3 nm chips, an industry goal for 2025-2026. It also eliminates the need for complex double patterning techniques required presently.

However, superior performance comes at a cost - literally and figuratively. The hefty $380 million price tag for each High-NA system introduces financial challenges for chipmakers. Additionally, the larger High-NA tools require completely reconfiguring chip fabrication facilities. Their halved imaging field also necessitates rethinking chip designs. As a result, adoption timelines differ across companies - Intel intends to deploy High-NA EUV at an advanced 1.8 nm (18A) node, while TSMC is taking a more conservative approach, potentially implementing it only in 2030 and not rushing the use of these lithography machines, as the company's nodes are already developing well and on time. Interestingly, the installation process of ASML's High-NA Twinscan EXE 150,000-kilogram system required 250 crates, 250 engineers, and six months to complete. So, production is as equally complex as the installation and operation of this delicate machinery.