The DDR PHY Interface (DFI) Group today released version 5.0 of the specification for interfaces between high-speed memory controllers and physical (PHY) interfaces to support the requirements of future mobile and server memory standards. The DFI specifications, widely adopted throughout the memory industry, enable greater interoperability.
The DFI Group included several interface improvements in this newest specification. The new version of the specification adds protocol support for the newest DDR and low-power memory technologies. Previous versions of the specification defined memory training across the interface between the memory controller and the PHY. The new specification completely transitions to PHY-independent training mode where the PHY trains the memory interface without involving the controller. Other interface improvements include lower power enhancements, providing a PHY-independent boot sequence, expanding frequency change support, and defining new controller-to-PHY interface interactions.
"The industry is beginning to embrace new low-power and DDR memory technologies, including high-performance devices such as servers, storage, and networking; autonomous vehicles; and low-power handheld devices and IoT," stated John MacLaren, DFI Group chairman and Cadence design engineering architect. "The DFI Group, consisting of experts from leading companies in the industry, is enthusiastic to contribute to enabling this transition with the latest release of the DFI specification. Beyond supporting the latest DDR and LPDDR memory technologies, we have introduced significant improvements to the interface to improve low power, interoperability, and interface interactions."