Silicon Motion's SM2508 was first revealed in August last year at the Flash Memory Summit 2023, but after that things went pretty quiet. However, the company was demoing the SM2508 up and running at Computex this past week and it's set to edge out Phison's E26 Max14um in the battle of fastest NVMe SSD controller. We're not talking about any massive gains here, but the reference drive from Silicon Motion was shown running CrystalDiskMark 8.0.4 at the show and if we do a rough comparison to a Phison E26 Max14um, the SM2508 beats Phison by about 800 MB/s in sequential read performance and 500 MB/s in sequential write performance.

This might not seem like a whole lot, but the SM2508 is built on TSMC's N6 node which results in a 3.5 Watt peak power consumption, or 7 Watts for the entire SSD at load. A typical Phison E26 based SSD draws in excess of 11 Watts of power at full load, which is a big difference in a mobile device. This should obviously also lead to lower thermals and we should finally see PCIe 5.0 drives that don't need massive heatsinks or active cooling. In fact, 7 Watts power draw is very similar to Phison's E18 PCIe 4.0 based SSDs. Silicon Motion is still working on fine tuning the firmware for the SM2508, so performance might yet improve to reach the promised 14 GB/s write performance. Currently the random performance is also looking a bit on the weak side compared to Phison. According to Tom's hardware, we should see the first drives with the Silicon Motion SM2508 appear in the market sometime in Q4 this year.

The rollout of SiPearl's much-anticipated Rhea processor for European supercomputers has been pushed back by a year to 2025, but the delay comes with a silver lining - a significant upgrade in core count and potential performance. Originally slated to arrive in 2024 with 72 cores, the homegrown high-performance chip will now pack 80 cores when it eventually launches. This decisive move by SiPearl and its partners is a strategic choice to ensure the utmost quality and capabilities for the flagship European processor. The additional 12 months will allow the engineering teams to further refine the chip's architecture, carry out extensive testing, and optimize software stacks to take full advantage of Rhea's computing power. Now called the Rhea1, the chip is a crucial component of the European Processor Initiative's mission to develop domestic high-performance computing technologies and reduce reliance on foreign processors. Supercomputer-scale simulations spanning climate science, drug discovery, energy research and more all require astonishing amounts of raw compute grunt.

By scaling up to 80 cores based on the latest Arm Neoverse V1, Rhea1 aims to go toe-to-toe with the world's most powerful processors optimized for supercomputing workloads. The SiPearl wants to utilize TSCM's N6 manufacturing process. The CPU will have 256-bit DDR5 memory connections, 104 PCIe 5.0 lanes, and four stacks of HBM2E memory. The roadmap shift also provides more time for the expansive European supercomputing ecosystem to prepare robust software stacks tailored for the upgraded Rhea silicon. Ensuring a smooth deployment with existing models and enabling future breakthroughs are top priorities. While the delay is a setback for SiPearl's launch schedule, the substantial upgrade could pay significant dividends for Europe's ambitions to join the elite ranks of worldwide supercomputer power. All eyes will be on Rhea's delivery in 2025, mainly from Europe's governments, which are funding the project.

TSMC today showcased its latest technology developments at its 2023 North America Technology Symposium, including progress in 2 nm technology and new members of its industry-leading 3 nm technology family, offering a range of processes tuned to meet diverse customer demands. These include N3P, an enhanced 3 nm process for better power, performance and density, N3X, a process tailored for high performance computing (HPC) applications, and N3AE, enabling early start of automotive applications on the most advanced silicon technology.

With more than 1,600 customers and partners registered to attend, the North America Technology Symposium in Santa Clara, California is the first of the TSMC's Technology Symposiums around the world in the coming months. The North America symposium also features an Innovation Zone spotlighting the exciting technologies of 18 emerging start-up customers.

Another quarter, another record breaking earnings report by TSMC, but it seems like the company has released that things are set to slow down sooner than initially expected and the company is hitting the brakes on some of its expansion projects. The company saw a 79.7 percent increase in profits compared to last year, with a profit of US$8.8 billion and a revenue of somewhere between US$19.9 to US$ 20.7 billion for the third quarter, which is a 47.9 percent bump compared to last year. TSMC's 5 nm nodes were the source for 28 percent of the revenues, followed by 26 percent for 7 nm nodes, 12 percent for 16 nm and 10 percent for 28 nm, with remaining nodes at 40 nm and larger making up for the remainder of the revenue. By platform, smartphone chips made up 41 percent, followed by High Performance Computing at 39 percent, IoT at 10 percent and automotive at five percent.

TSMC said it will cut back its CAPEX budget by around US$4 billion, to US$36 billion, compared to the earlier stated US$40 billion budget the company had set aside for expanding its fabs. Part of the reason for this is that TSMC is already seeing weaker demand for products manufactured using its N7 and N6 nodes, as the N7 node was meant to be a key part of the new fab in Kaohsiung in southern Taiwan. TSMC is expecting to start production on its first N3 node later this quarter and is expecting the capacity to be fully utilised for all of 2023. Supply is said to be exceeding demand, which TSMC said is partially to blame on tooling delivery issues. TSMC is expecting next year's revenue for its N3 node to be higher than its N5 node in 2020, although the revenue is said to be in the single digit percentage range. The N3E node is said to start production sometime in the second half of next year, or about a quarter earlier than expected. The N2 node isn't due to start production until 2025, but TSMC is already having very high customer engagement, so it doesn't look like TSMC is likely to suffer from a lack of business in the foreseeable future, as long as the company keeps delivering new nodes as planned.

The latest CFI-1202 series hardware revisions of the Sony PlayStation 5 entertainment system receive new "Oberon Plus" SoCs built on the TSMC N6 (6 nm) silicon fabrication node, and could include several new power-management features of the kind seen in AMD Ryzen 6000 mobile-processors, which could bring down the overall weight of the console as it could shed anywhere between 200-300 grams (6.25-6.5 percent) compared to older 2021 models. The CFI-1202B is the Digital-only variant that lacks an optical drive; while the CFI-1202A is the slightly heavier model that comes with a Blu-ray ROM drive. The 6% reduction in weight may not seem like much to the end-user, but has a cumulative effect for Sony to ship them by the thousands.

Intel's next-generation "Meteor Lake" processor is the first mass-production client processor to embody the company's IDM 2.0 manufacturing strategy—one of building processors with multiple logic tiles interconnected with Foveros and a base-tile (essentially an interposer). Each tile is built on a silicon fabrication process most suitable to it, so that the most advanced node could be reserved for the component that benefits from it the most. For example, while you need the SIMD components of the iGPU to be built on an advanced low-power node, you don't need its display controller and media engine to, and these could be relegated to a tile built on a less advanced node. This way Intel is able to maximize its use of wafers for the most advanced nodes in a graded fashion.

Japanese tech publication PC Watch has annotated the "Meteor Lake" SoC, and points out that the vast majority of the chip's tiles and logic die-area is manufactured on TSMC nodes. The MCM consists of four logic tiles—the CPU tile, the Graphics tile, the SoC tile, and the I/O tile. The four sit on a base tile that facilitates extreme-density microscopic wiring interconnecting the logic tiles. The base tile is built on the 22 nm HKMG silicon fabrication node. This tile lacks any logic, and only serves to interconnect the tiles. Intel has an active 22 nm node, and decided it has the right density for the job.

AMD formally launched the entry-level Radeon RX 6400 graphics card. At an MSRP of $159, this is the most affordable graphics card from the Radeon RX 6000 series. It is based on the same RDNA2 graphics architecture as the rest of the RX 6000 lineup, and the smallest silicon of them all, the "Navi 23." This chip is built on the TSMC N6 (6 nm) silicon fabrication process.

The RX 6400 shares the "Navi 23" silicon with the RX 6500 XT launched earlier this year. AMD enabled 12 out of 16 RDNA2 compute units on the silicon, resulting in 768 stream processors, 48 TMUs, 12 Ray Accelerators, and 32 ROPs. The memory configuration is similar to the RX 6500 XT, with 4 GB of GDDR6 memory across a 64-bit wide memory bus. This is the same 16 Gbps-rated memory, which means 128 GB/s bandwidth on tap. There's also 16 MB of Infinity Cache. The engine clocks (GPU clocks) are set at 2039 MHz (game) and 2321 MHz (boost). With its given specs, the RX 6400 has a typical graphics power (TGP) of just 53 W, and so cards can do without any power connectors.

Way back in January 2021, we heard a spectacular rumor about "Navi 31," the next-generation big GPU by AMD, being the company's first logic-MCM GPU (a GPU with more than one logic die). The company has a legacy of MCM GPUs, but those have been a single logic die surrounded by memory stacks. The RDNA3 graphics architecture that the "Navi 31" is based on, sees AMD fragment the logic die into smaller chiplets, with the goal of ensuring that only those specific components that benefit from the TSMC N5 node (6 nm), such as the number crunching machinery, are built on the node, while ancillary components, such as memory controllers, display controllers, or even media accelerators, are confined to chiplets built on an older node, such as the TSMC N6 (6 nm). AMD had taken this approach with its EPYC and Ryzen processors, where the chiplets with the CPU cores got the better node, and the other logic components got an older one.

Greymon55 predicts an interesting division of labor on the "Navi 31" MCM. Apparently, the number-crunching machinery is spread across two GCD (Graphics Complex Dies?). These dies pack the Shader Engines with their RDNA3 compute units (CU), Command Processor, Geometry Processor, Asynchronous Compute Engines (ACEs), Rendering Backends, etc. These are things that can benefit from the advanced 5 nm node, enabling AMD to the CUs at higher engine clocks. There's also sound logic behind building a big GPU with two such GCDs instead of a single large GCD, as smaller GPUs can be made with a single such GCD (exactly why we have two 8-core chiplets making up a 16-core Ryzen processors, and the one of these being used to create 8-core and 6-core SKUs). The smaller GCD would result in better yields per wafer, and minimize the need for separate wafer orders for a larger die (such as in the case of the Navi 21).

Intel's recently announced Arc "Alchemist" line of discrete gaming graphics processors consists of at least five mobile SKUs across the Arc 3, Arc 5, and Arc 7 lines; with desktop SKUs expected later this year. These are based on one of two ASICs—the DG2-128 (ACM-G11) and the DG2-512 (ACM-G10), both built on the TSMC N6 (6 nm) silicon fabrication process. Coelacanth's Dream discovered a third ASIC when digging through Intel Graphics Compiler code on GitHub, referred to as the "ACM-G12."

This silicon has exactly half the amount of number-crunching machinery as the DG2-512, and features 256 execution units (EU), or 16 Xe cores, working out to 2,048 unified shaders—double that of the DG2-128, but half that of the DG2-512. Interestingly, the Arc 5 A550M mobile GPU announced last week has specifications corresponding to this silicon, even though it was announced to be a heavily cut-down DG2-512. Intel probably figures that at some point making A550M GPUs using DG2-512 could mean cutting down perfectly functional silicon, and so it makes sense to manufacture physically smaller dies (more dies per wafer). There are no other known specs of the ACM-G12. It's quite likely given the rest of its alignment with the A550M's specs that it could feature a 128-bit wide GDDR6 memory interface.

A few days ago, Intel announced its first official discrete graphics card efforts, designed for laptops. Called the Arc Alchemist lineup, Intel has designed these SKUs to provide entry-level to high-end options covering a wide range of use cases. Today, AMD has responded with a rather exciting Tweet made by the company's @Radeon Twitter account. The company compared Intel's Arc Alchemist A370M GPU with AMD's Radeon RX 6500M mobile SKUs in the post. These GPUs are made on TSMC's N6 node, feature 4 GB GDDR6 64-bit memory, 1024 FP32 cores, and have the same configurable TDP range of 35-50 Watts.

Below, you can see AMD's benchmarks of the following select games: Hitman 3, Total War Saga: Troy, F1 2021, Strange Brigade (High), and Final Fantasy XIV. The Radeon RX 6500M GPU manages to win in all of these games, thus explaining AMD's "FTW" hashtag on Twitter. Remember that these are vendor-supplied benchmarks runs, so we have to wait for some media results to surface.

Some interesting technical specifications of the elusive two GPUs behind the Intel Arc "Alchemist" series surfaced. The larger DG2-512 silicon in particular, which forms the base for the Arc 5 and Arc 7 series, is interesting, in that it is larger in every way than the performance-segment ASICs from both NVIDIA and AMD. The table below compares the physical specs of the DG2-512, with the NVIDIA GA104, and the AMD Navi 22. This segment of GPUs has fairly powerful use-cases, including native 1440p gameplay, or playing at 4K with a performance enhancement—something Intel has, in the form of the XeSS.

The DG2-512 is built on the 6 nm TSMC N6 foundry node, the most advanced node among the three GPUs in this class. It has the highest transistor density of 53.4 mTr/mm², and the largest die-area of 406 mm², and the highest transistor-count of 21.7 billion. The Xe-HPG graphics architecture is designed for full DirectX 12 Ultimate feature support, and the DG2-512 dedicated hardware for ray tracing, as well as AI acceleration. The Arc A770M is the fastest product based on this silicon, however, it is a mobile GPU with aggressive power-management characteristic to the form-factor it serves. Here, the DG2-512 has an FP32 throughput of 13.5 TFLOPs, compared to 13.2 TFLOPs of the Navi 22 on the Radeon RX 6700 XT desktop graphics card, and the 21.7 TFLOPs of the GA104 that's maxed out on the GeForce RTX 3070 Ti desktop graphics card.

AMD is allegedly preparing to announce the Radeon RX 6000S mobile graphics card based on a refreshed RDNA 2 architecture. The new card will be manufactured on TSMC's N6 process which offers an 18% logic density improvement over the N7 process currently used for RDNA 2 products resulting in increased efficiency or performance. The switch to the IP compatible N6 node should also improve yields and shorten production cycles allowing AMD to remain competitive with new cards from NVIDIA and Intel. We have limited information on this alleged card except that it will likely be announced in early 2022 at CES and that AMD may also release discrete RX 6000S series desktop graphics cards.

In its 2021 Architecture Day presentation, Intel revealed that its first performance gaming GPU, the Arc "Alchemist," is built on the TSMC N6 silicon fabrication node (6 nm). A more advanced node than the N7 (7 nm) used by AMD for its current RDNA2 GPUs, TSMC N6 leverages EUV (extreme ultraviolet) lithography, and offers 18% higher transistor density, besides power improvements. "With N6, TSMC provides an optimal balance of performance, density, and power-efficiency that are ideal for modern GPUs," said Dr Kevin Zhang, SVP of Business Development at TSMC.

With working prototypes of "Alchemist" already internally circulating as the "DG2," Intel has beaten AMD to 6 nm. Team Red is reportedly planning optical-shrinks of its RDNA2-based "Navi 22" and "Navi 23" chips to TSMC N6, and assigning them mid-range SKUs in the Radeon RX 7000 series. The company will build two higher-segment RDNA3 GPUs on the more advanced TSMC N5 (5 nm) process, which will release in 2022, and power successors to the RX 6700 series and RX 6800/6900 series.

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced immediate availability of Cadence IP supporting the PCI Express (PCIe ) 5.0 specification on TSMC N5 process technology. The next follow-on version on TSMC N3 process technology is expected to be taped out in early 2022. Collaboration with major customers is ongoing for N5 SoC designs targeting hyperscale computing and networking applications. The Cadence IP for PCIe 5.0 technology consists of a PHY, companion controller and Verification IP (VIP) targeted at SoC designs for very high-bandwidth hyperscale computing, networking and storage applications. With Cadence's PHY and Controller Subsystem for PCIe 5.0 architecture, customers can design extremely power-efficient SoCs with accelerated time to market.

The Cadence IP for PCIe 5.0 architecture offers a highly power-efficient implementation of the standard, with several evaluations from leading customers indicating it provides industry best-in-class power at the maximum data transfer rate of 32GT/s and worst-case insertion loss. Leveraging Cadence's existing N7/N6 silicon validated offering, the N5 design provides a full 512GT/s (gigatransfers per second) power-optimized solution across the full range of operating conditions with a single clock lane.

It's not only graphics cards and CPUs that are best kept on the edge of manufacturing processes; in truth, one could even say that consoles have more to gain from these transitions when it comes to their manufacturers' financial outlooks. This happens because usually, consoles are subsidized by manufacturers in that their actual retail price is lower than manufacturing costs; this works as a way for console players to increase their platforms' attractiveness and user base, so they can then sell them games and subscription services, where the big bucks are actually made. We knew this already, but Microsoft's head of Xbox business development, Lori Wright confirmed it yesterday at the Apple vs Epic Games hearing. Lori Wright is quoted as answering "We don't; we sell the consoles at a loss" when asked whether Microsoft does or does not turn a profit on Xbox Series S | X hardware sales.

Considering the similarities between the Xbox Series X and PS5's SoC, it's very likely that Sony doesn't make a profit on console hardware sales either - or if it actually does, it's nothing actually meaningful. This is part of the reason why consoles are usually actually in the forefront of manufacturing processes' advancements, as it's a way for console players to quickly reduce the BoM (Bill of Materials) for their consoles. Since the specifications don't change within a console generation (discounting Pro models, which both companies have taken to launching some years into their generations), they choose to take advantage of process advancements due to the transistor density increases that allow for both lower silicon area for the SoC, and lower power consumption - which sometimes enables them to develop slim versions of their gaming consoles.

In a bid to show off its volume production prowess and technological edge (but mostly to rub it in to rival fabs), TSMC on Thursday announced that it shipped its 1 billionth chip fabricated on its 7 nm process. If these dies were combined into one big rectangular wafer, they would cover 13 New York City blocks. TSMC's 7 nm process debuted with its N7 node, which went into volume production in April 2018, over two years ago. The fab has since mass-produced 7 nm chips for the likes of Qualcomm, Apple, and AMD, among dozens of other clients. The company now looks to monetize refinements of N7, namely the N7e and N7P (DUV refinements), while executing its crucial EUV-based N7+ node, leading up to future nodelets such as N6. Much of TSMC's growth will be propelled by 5G modems, application processors, and its pivotal role in the growth of companies such as AMD.

TSMC is reportedly planning a stopgap between its 5 nm-class silicon fabrication nodes, and the 3 nm-class, called N4. According to the foundry's CEO, Liu Deyin, speaking at a shareholders meeting, N4 will be a 4 nm node, and an enhancement of N5P, the company's most advanced 5 nm-class node. N4 is slated for mass-production of contracted products in 2023, and could help TSMC's customers execute their product roadmaps of the time. From the looks of it, N4 is a repeat of the N6 story: a nodelet that's an enhancement of N7+, the company's most advanced 7 nm-class node that leverages EUV lithography.

Intel is rumored to be aligning its future-generation Xe GPU development with TSMC's node development cycle, with the company reportedly negotiating with the Taiwanese foundry for 6 nm and 3 nm allocation for its large Xe GPUs. Intel's first Xe discrete GPUs for the market, however, are reportedly built on the company's own 10 nm+ silicon fabrication process.

While Intel's fascination with TSMC 3 nm is understandable, seeking out TSMC's 6 nm node raises eyebrows. Internally referred to as "N6," the 6 nm silicon fabrication node at TSMC is expected to go live either towards the end of 2020 or early 2021, which is when Intel's 10 nm+ node is expected to pick up volume production, beginning with the company's "Tiger Lake" processors. Perhaps a decision has been made internally to ensure that Xe doesn't eat too much into Intel's own foundry capacities meant for processor manufacturing, and to instead outsource Xe manufacturing to third-party foundries like TSMC and Samsung eventually. Way back in April 2019 it was rumored that Intel was evaluating Samsung as a foundry partner for Xe.

European Processor Initiative (EPI) is a Europe's project to kickstart a homegrown development of custom processors tailored towards different usage models that the European Union might need. The first task of EPI is to create a custom processor for high-performance computing applications like machine learning, and the chip prototypes are already on their way. The EPI chairman of the board Jean-Marc Denis recently spoke to the Next Platform and confirmed some information regarding the processor design goals and the timeframe of launch.

Supposed to be manufactured on TSMC's 6 nm EUV (TSMC N6 EUV) technology, the EPI processor will tape-out at the end of 2020 or the beginning of 2021, and it is going to be heterogeneous. That means that on its 2.5D die, many different IPs will be present. The processor will use a custom ARM CPU, based on a "Zeus" iteration of Neoverese server core, meant for general-purpose computation tasks like running the OS. When it comes to the special-purpose chips, EPI will incorporate a chip named Titan - a RISC-V based processor that uses vector and tensor processing units to compute AI tasks. The Titan will use every new standard for AI processing, including FP32, FP64, INT8, and bfloat16. The system will use HBM memory allocated to the Titan processor, have DDR5 links for the CPU, and feature PCIe 5.0 for the inner connection.

TSMC vice chairman and CEO C.C. Wei announced the company's plans for 5 nm are on track, which means High Volume manufacturing (HVM) on the node is expected to be achieved by 2Q 2020. The company has increased expenditures in ramping up its various nodes from an initially projected $10 billion to something along the lines of $14 billion - 15 billion; the company is really banking on quick uptake and design wins on its most modern process technologies - and the increased demand that follows.

TSMC's 5 nm process (N5) will use extreme ultraviolet lithography (EUVL) in many more layers than its N7+ and N6 processes, with up to 14 layers being etched in the N5 silicon compared to five and six, respectively, for its "older" N7+ and N6 processes. As the company increases capital expenditure in acquiring EUVL-capable equipment that sets up its production nodes for the market they foresee will just gobble up the chips in 2020, the company is optimistic they can achieve growth in the 5-10% number.

TSMC today announced that its seven-nanometer plus (N7+), the industry's first commercially available Extreme Ultraviolet (EUV) lithography technology, is delivering customer products to market in high volume. The N7+ process with EUV technology is built on TSMC's successful 7 nm node and paves the way for 6 nm and more advanced technologies.

The N7+ volume production is one of the fastest on record. N7+, which began volume production in the second quarter of 2019, is matching yields similar to the original N7 process that has been in volume production for more than one year.

TSMC in its quarterly earnings call expressed confidence in that most of its 7 nm (N7) process production node customers would be looking to make the transition to their 6 nm (N6) process. In fact, the company expects that node to become the biggest target for volume ordering (and thus production) amongst its customers, since the new N6 fabrication technology will bring about a sort of "backwards compatibility" with design tools and semiconductor designs that manufacturers have already invested in for its N7 node, thus allowing for cost savings for its clients.

This is despite TSMC's N6 process being able to take advantage of extreme ultraviolet lithography (EUVL) to lower manufacturing complexity. This lowering is achieved by the fact that less exposures of the silicon are required for multi-patterning - which is needed today as TSMC's N7 uses solely deep ultraviolet (DUV) lithography. Interestingly, TSMC expects other clients to pick up its N7+ manufacturing node that aren't already using their 7nm node - the need to develop new tools and lesser design compatibility between its N7 and N7+ nodes compared no N7 and N6 being the justification. TSMC's N7+ will be the first node to leverage EUV, using up to four EUVL layers, while N6 expands it up to five layers, and the upcoming N5 cranks EUVL up to fourteen (allowing for 14 layers.)