xMEMS Labs, pioneers in solid-state, all-silicon micro speakers, today announced a revolutionary breakthrough in sound reproduction, changing the way mass-market, true wireless stereo (TWS) earbuds create ultra high-quality, high-resolution sound experiences across all audio frequencies.

With the introduction of its groundbreaking new Cypress solid-state MEMS speaker, xMEMS engineers have replaced legacy push-air sound reproduction with the company's ultrasonic amplitude modulation transduction principle. Ultrasonic modulation turns ultrasonic air pulses into rich, detailed, bass-heavy, high-fidelity sound, representing the first no-compromise alternative to the moving-coil concept for high-volume consumer active noise canceling (ANC) earbud micro speakers.

Jabil Inc., a global leader in design, manufacturing, and supply chain solutions, today announced it will take over the manufacture and sale of Intel's current Silicon Photonics-based pluggable optical transceiver ("module") product lines and the development of future generations of such modules.

"This deal better positions Jabil to cater to the needs of our valued customers in the data center industry, including hyperscale, next-wave clouds, and AI cloud data centers. These complex environments present unique challenges, and we are committed to tackling them head-on and delivering innovative solutions to support the evolving demands of the data center ecosystem," stated Matt Crowley, Senior Vice President of Cloud and Enterprise Infrastructure at Jabil. "This deal enables Jabil to expand its presence in the data center value chain."

The Chinese semiconductor industry is advancing, and interestingly, it is growing rapidly under sanctions, even with the blacklisting of companies by the US government. China's semiconductor industry is mainly represented by companies like Semiconductor Manufacturing International Corp (SMIC) and Huawei Technologies, who are leading the investment and progress in both chip manufacturing and chip design. According to the latest interview with Bloomberg, former TSMC Vice President Burn J. Lin said that the US government and its sanctions can not stop the advancement of Chinese semiconductor companies. Currently, Lin notes that SMIC and Huawei can use older machinery to produce more advanced chips.

Even so, SMIC could progress to 5 nm technology using existing equipment, particularly with scanners and other machinery from ASML. Development under sanctions would also force China to experiment with new materials and other chip packaging techniques that yield higher performance targets. SMIC has already developed a 7 nm semiconductor manufacturing node, which Huawei used for its latest Mate 60 Pro smartphone, based on Huawei's custom HiSilicon Kirin 9000S chip. Similarly, the transition is expected to happen to the 5 nm node as well, and it is only a matter of time before we see other nodes appear. "It is just not possible for the US to completely prevent China from improving its chip technology," noted Burn J. Lin.

Synopsys today announced it has expanded its collaboration with Arm to provide optimized IP and EDA solutions for the newest Arm technology, including the Arm Neoverse V2 platform and Arm Neoverse Compute Subsystem (CSS). Synopsys has joined Arm Total Design where Synopsys will leverage their deep design expertise, the Synopsys.ai full-stack AI-driven EDA suite, and Synopsys Interface, Security, and Silicon Lifecycle Management IP to help mutual customers speed development of their Arm-based CSS solutions. The expanded partnership builds on three decades of collaboration to enable mutual customers to quickly develop specialized silicon at lower cost, with less risk and faster time to market.

"With Arm Total Design, our aim is to enable rapid innovation on Arm Neoverse CSS and engage critical ecosystem expertise at every stage of SoC development," said Mohamed Awad, senior vice president and general manager, Infrastructure Line of Business at Arm. "Our deep technical collaboration with Synopsys to deliver pre-integrated and validated IP and EDA tools will help our mutual customers address the industry's most complex computing challenges with specialized compute."

Avicena, a privately held company headquartered in Sunnyvale, CA, is demonstrating its LightBundle multi-Tbps chip-to-chip interconnect technology at the European Conference for Optical Communications (ECOC) 2023 in Glasgow, Scotland (https://www.ecocexhibition.com/). Avicena's microLED-based LightBundle architecture breaks new ground by unlocking the performance of processors, memory and sensors, removing key bandwidth and proximity constraints while simultaneously offering class leading energy efficiency.

"As generative AI continues to evolve, the role of high bandwidth-density, low-power and low latency interconnects between xPUs and HBM modules cannot be overstated", says Chris Pfistner, VP Sales & Marketing of Avicena. "Avicena's innovative LightBundle interconnects have the potential to fundamentally change the way processors connect to each other and to memory because their inherent parallelism is well-matched to the internal wide and slow bus architecture within ICs. With a roadmap to multi-terabit per second capacity and sub-pJ/bit efficiency these interconnects are poised to enable the next era of AI innovation, paving the way for even more capable models and a wide range of AI applications that will shape the future."

As the world experiences a generational shift to artificial intelligence, each of us is participating in a new era of global expansion enabled by silicon. It's the "Siliconomy," where systems powered by AI are imbued with autonomy and agency, assisting us across both knowledge-based and physical-based tasks as part of our everyday environments.

At Intel Innovation, the company unveiled technologies to bring AI everywhere and to make it more accessible across all workloads - from client and edge to network and cloud. These include easy access to AI solutions in the cloud, better price performance for Intel data center AI accelerators than the competition offers, tens of millions of new AI-enabled Intel PCs shipping in 2024 and tools for securely powering AI deployments at the edge.

Taiwan's Economic Daily reckons that a freshly formed partnership between TSMC, Broadcom, and NVIDIA will result in the development of cutting-edge silicon photonics. The likes of IBM, Intel and various academic institutes are already deep into their own research and development processes, but the alleged new alliance is said to focus on advancing AI computer hardware. The report cites a significant allocation of—roughly 200—TSMC staffers onto R&D involving the integration of silicon photonic technologies into high performance computing (HPC) solutions. They are very likely hoping that the usage of optical interconnects (on a silicon medium) will result in greater data transfer rates between and within microchips. Other benefits include longer transmission distances and a lower consumption of power.

TSMC vice president Yu Zhenhua has placed emphasis on innovation, in a similar fashion to his boss, within the development process (industry-wide): "If we can provide a good silicon photonics integrated system, we can solve the two key issues of energy efficiency and AI computing power. This will be a new one...Paradigm shift. We may be at the beginning of a new era." The firm is facing unprecedented demand from its clients—it hopes to further expand its advanced chip packaging capacity to address these issues by late 2024. A shift away from the limitations of "conventional electric" data transmissions could bring next generation AI compute GPUs onto the market by 2025.

Worldwide silicon wafer shipments increased 2.0% quarter-over-quarter to 3,331 million square inches in the second quarter of 2023, down 10.1% from the 3,704 million square inches recorded during the same quarter last year, the SEMI Silicon Manufacturers Group (SMG) reported in its quarterly analysis of the silicon wafer industry.

"The semiconductor industry continues to work through excess inventory in various market segments, necessitating that fabs operate below full capacity," said Anna-Riikka Vuorikari-Antikainen, Chairman of SEMI SMG and Chief Commercial Officer at Okmetic. "As a result, silicon wafer shipments are lagging their 2022 peak. Second-quarter wafer shipments held steady quarter-on-quarter with 300 mm showing quarterly growth among all wafer sizes."

Somewhat out of the blue, Silicon Box has announced the opening of its US$2 billion semiconductor assembly plant in Singapore. The "startup" is founded by several of Marvell's founders, suggesting the company has the right pedigree to compete in what is sure to be a very competitive market over the next few years. Silicon Box is not a foundry and will at least at this point in time, not be involved in foundry services, but instead the company will focus on advanced chip packaging technologies, focusing on chiplets.

The company is promising "faster time-to-market, lower new device design cost" on its very rudimentary website, something the company has yet to prove to be capable of. However, its new plant in Singapore covers 73,000 square metres and is said to feature state of the art production equipment for turning chiplets into chips. The factory is said to create some 1,200 jobs in Singapore, suggesting that this is a company that means business. According to a comment by company founder and CEO BJ Han to Reuters, "customers had been lining up" since before the completion of the assembly plant. Silicon Box is expecting to have several AI chipset companies as its customers, including Tenstorrent, which so far is the only officially mentioned client. Time will tell if Silicon Box can compete with established chip packaging businesses and if they can deliver on their promise to be faster and cheaper than the competition.

TrendForce reports that explosive growth in generative AI applications like chatbots has spurred significant expansion in AI server development in 2023. Major CSPs including Microsoft, Google, AWS, as well as Chinese enterprises like Baidu and ByteDance, have invested heavily in high-end AI servers to continuously train and optimize their AI models. This reliance on high-end AI servers necessitates the use of high-end AI chips, which in turn will not only drive up demand for HBM during 2023~2024, but is also expected to boost growth in advanced packaging capacity by 30~40% in 2024.

TrendForce highlights that to augment the computational efficiency of AI servers and enhance memory transmission bandwidth, leading AI chip makers such as Nvidia, AMD, and Intel have opted to incorporate HBM. Presently, Nvidia's A100 and H100 chips each boast up to 80 GB of HBM2e and HBM3. In its latest integrated CPU and GPU, the Grace Hopper Superchip, Nvidia expanded a single chip's HBM capacity by 20%, hitting a mark of 96 GB. AMD's MI300 also uses HBM3, with the MI300A capacity remaining at 128 GB like its predecessor, while the more advanced MI300X has ramped up to 192 GB, marking a 50% increase. Google is expected to broaden its partnership with Broadcom in late 2023 to produce the AISC AI accelerator chip TPU, which will also incorporate HBM memory, in order to extend AI infrastructure.

Intel and the German federal government have signed a revised letter of intent for Intel's planned leading-edge wafer fabrication site in Magdeburg, the capital of Saxony-Anhalt state in Germany. The agreement encompasses Intel's expanded investment in the site, now expected to be more than 30 billion euros for two first-of-a-kind semiconductor facilities (also known as "fabs") in Europe, along with increased government support that includes incentives, reflecting the expanded scope and change in economic conditions since the site was first announced.

Intel acquired the land for the project in November 2022, and the first facility is expected to enter production in four to five years following the European Commission's approval of the incentive package. Given the current timeline and scale of the investment, Intel plans to deploy more advanced Angstrom-era technology in the facilities than originally envisioned. The Magdeburg site will serve Intel products and Intel Foundry Services customers.

Today, Intel announced the release of its newest quantum research chip, Tunnel Falls, a 12-qubit silicon chip, and it is making the chip available to the quantum research community. In addition, Intel is collaborating with the Laboratory for Physical Sciences (LPS) at the University of Maryland, College Park's Qubit Collaboratory (LQC), a national-level Quantum Information Sciences (QIS) Research Center, to advance quantum computing research.

"Tunnel Falls is Intel's most advanced silicon spin qubit chip to date and draws upon the company's decades of transistor design and manufacturing expertise. The release of the new chip is the next step in Intel's long-term strategy to build a full-stack commercial quantum computing system. While there are still fundamental questions and challenges that must be solved along the path to a fault-tolerant quantum computer, the academic community can now explore this technology and accelerate research development."—Jim Clarke, director of Quantum Hardware, Intel

Applied Materials, Inc. today announced a landmark investment to build the world's largest and most advanced facility for collaborative semiconductor process technology and manufacturing equipment research and development (R&D). The new Equipment and Process Innovation and Commercialization (EPIC) Center is planned as the heart of a high-velocity innovation platform designed to accelerate development and commercialization of the foundational technologies needed by the global semiconductor and computing industries.

To be located at an Applied campus in Silicon Valley, the multibillion-dollar facility is designed to provide a breadth and scale of capabilities that is unique in the industry, including more than 180,000 square feet - more than three American football fields - of state-of-the-art cleanroom for collaborative innovation with chipmakers, universities and ecosystem partners. Designed from the ground up to accelerate the pace of introducing new manufacturing innovations, the new EPIC Center is expected to reduce the time it takes the industry to bring a technology from concept to commercialization by several years, while simultaneously increasing the commercial success rate of new innovations and the return on R&D investments for the entire semiconductor ecosystem.

Following the news that Oppo is likely to pull out of the French market, it now appears that the company has closed its chip design unit named Zeku. According to the South China Morning Post, workers at Zeku got less than a day's notice that the company was shutting down, which was on Thursday last week. Employees weren't even allowed back into the office to collect their personal belongings. As recent as two weeks ago, Zeku was still looking for new hires, which makes the abrupt closure even more peculiar, especially as Zeku is said to have employed upwards of 3,000 people.

Considering that Oppo is ranked as the fourth largest smartphone maker in terms of globally shipped units in Q1, the way the company has handled the closure of its chip design unit reeks of desperation. It should be noted that Zeku wasn't designing chips to power Oppo's phones, but presumably Zeku was behind the MariSilicon X, which was Oppo's own imaging co-processor. In all fairness, Oppo is far from the only company to have closed down business units this year, but the company is also said to be suffering in terms of shipments of smartphones, as the company saw a drop of 22 percent in shipments last year, to 103 million units. This appears to be part of the reason behind the shutdown of Zeku, but Oppo hasn't provided much in terms of details behind the closure.

At VLSI Symposium 2023, scheduled to take place between June 11-16, Intel is set to demonstrate its PowerVia technology working efficiently on an E-Core chip built using the Intel 4 node. Conventional chips have power and signal interconnects distributed across multiple metal layers. PowerVia, on the other hand, dedicates specific layers for power delivery, effectively separating them from the signal routing layers. This approach allows for vertical power delivery through a set of power-specific Through-Silicon Vias (TSVs) or PowerVias, which are essentially vertical connections between the top and bottom surfaces of the chip. By delivering power directly from the backside of the chip, PowerVia reduces power supply noise and resistive losses, optimizing power distribution and improving overall energy efficiency. PowerVia is set to make a debut in 2024 with Intel 20A node.

For VLSI Symposium 2023 talk, the company has prepared a paper that highlights a design made using Intel 4 technology and implements E-Cores only in a test chip. The document states: "PowerVia Technology is a novel innovation to extend Process Scaling by having Power Delivery on the backside. This paper presents the pre and post silicon findings from implementing an Intel E-Core in PowerVia Technology. PowerVia enabled standard cell utilization of greater than 90 percent in large areas of the core while showing greater than 5 percent frequency benefit in silicon due reduced IR drop. Successful Post silicon debug is demonstrated with slightly higher but acceptable throughput times. The thermal characteristics of the PowerVia testchip is inline with higher power densities expected from logic scaling."

According to Tom's Hardware, Microsoft is busy hiring engineers to help the company design its own Arm based SoC for Windows 12. Based on job listings, Microsoft is adding people to its "Silicon team," which is currently involved in designing products for Microsoft's Azure, Xbox Surface and HoloLens products. That said, the specific job listings mentioned by Tom's Hardware mentions "optimizing Windows 12 for Silicon-ARM architecture" suggesting we're looking at a custom Arm SoC, with others mentioning "internally developed silicon components" and "building complex, state-of-the-art SOCs using leading silicon technology nodes and will collaborate closely with internal customers and partners."

That said, Microsoft is currently working with Qualcomm and the Microsoft SQ3 found in the Surface Pro 9 is the latest result of that partnership. This brings the question if Microsoft has decided to make its own chip to compete with the Apple M-series of silicon, or if Microsoft is simply looking at working closer with Qualcomm by hiring inhouse talent that can help tweak the Qualcomm silicon to better suit its needs. With Windows 12 scheduled for a 2024 release, it looks like we'll have to wait a while longer to find out what Microsoft is cooking up, but regardless of what it is, it looks like Windows on Arm isn't going anywhere.

MIT researchers have developed a groundbreaking technology that allows for the growth of 2D transition metal dichalcogenide (TMD) materials directly on fully fabricated silicon chips, enabling denser integrations. Conventional methods require temperatures of about 600°C, which can damage silicon transistors and circuits as they break down above 400°C. The MIT team overcame this challenge by creating a low-temperature growth process that preserves the chip's integrity, allowing 2D semiconductor transistors to be directly integrated on top of standard silicon circuits. The new approach grows a smooth, highly uniform layer across an entire 8-inch wafer, unlike previous methods that involved growing 2D materials elsewhere before transferring them to a chip or wafer. This process often led to imperfections that negatively impacted device and chip performance.

Additionally, the novel technology can grow a uniform layer of TMD material in less than an hour over 8-inch wafers, a significant improvement from previous methods that required over a day for a single layer. The enhanced speed and uniformity of this technology make it suitable for commercial applications, where 8-inch or larger wafers are essential. The researchers focused on molybdenum disulfide, a flexible, transparent 2D material with powerful electronic and photonic properties ideal for semiconductor transistors. They designed a new furnace for the metal-organic chemical vapor deposition process, which has separate low and high-temperature regions. The silicon wafer is placed in the low-temperature region while vaporized molybdenum and sulfur precursors flow into the furnace. Molybdenum remains in the low-temperature region, while the sulfur precursor decomposes in the high-temperature region before flowing back into the low-temperature region to grow molybdenum disulfide on the wafer surface.

Ansys and TSMC continue their long-standing technology collaboration to announce the certification of Ansys' power integrity software for TSMC's N2 process technology. The TSMC N2 process, which adopts nanosheet transistor structure, represents a major advancement in semiconductor technology with significant speed and power advantages for high performance computing (HPC), mobile chips, and 3D-IC chiplets. Both Ansys RedHawk-SC and Ansys Totem are certified for power integrity signoff on N2, including the effects of self-heat on long-term reliability of wires and transistors. This latest collaboration builds on the recent certification of the Ansys platform for TSMC's N4 and N3E FinFLEX processes.

"TSMC works closely with our Open Innovation Platform (OIP) ecosystem partners to help our mutual customers achieve the best design results with the full stack of design solutions on TSMC's most advanced N2 process," said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. "Our latest collaboration with Ansys RedHawk-SC and Totem analysis tools allows our customers to benefit from the significant power and performance improvements of our N2 technology while ensuring predictively accurate power and thermal signoff for the long-term reliability of their designs."

Marvell Technology, Inc., a leader in data infrastructure semiconductor solutions, announced today that it has selected Amazon Web Services, Inc. (AWS) as its cloud provider for electronic design automation (EDA). A cloud-first approach helps Marvell to rapidly and securely scale its service on the world's leading cloud, rise to the challenges brought by increasingly complex chip design processes, and deliver continuous innovation for the expanding needs across the automotive, carrier, data center, and enterprise infrastructure markets it serves. The work extends the longstanding relationship between the two companies—Marvell is also a key semiconductor supplier for AWS, helping the company support the design and rapid delivery of cloud services that best meet customers' demanding requirements.

EDA refers to the specialized and compute-intensive processes used in chip making and is a critical piece of Marvell's R&D. Over the years, the number of transistors on an integrated chip has increased exponentially. Each advance in chip design calls for a calculated application of software modules overseeing logic design, debugging, component placement, wire routing, optimization of time and power consumption, and verification. Due to the computationally intensive nature of EDA workloads, it is no longer cost-effective or timely to run EDA on premises. By powering its EDA with AWS, Marvell leverages an unmatched portfolio of services including secure, elastic, high-performance compute capacity in the cloud to solve challenges around speed, latency, security of IP, and data transfer.

Semiconductors are largely made using silicon, even though there are other types of substrates that can be used as well, such as gallium nitride or silicon carbide. However, most semiconductors today are made using silicon wafers, which in turn means that silicon wafers are a key material in the semiconductor industry. Over the past three years, the cost of silicon wafers have increased in pricing, due to higher demand, as there has been a higher demand for semiconductors. However, as there are a limited number of suppliers of silicon wafers, especially at the larger 12-inch size, the increased cost in materials has had an impact on the cost of the final semiconductors.

Reports out of Taiwan are suggesting that the price of 12-, 8- and 6-inch wafers are all starting to see a decline in price. We're talking single digit percentages here and it should be noted that these are spot prices, not contract prices, which are negotiated between the parties a long time before delivery. That said, the fact that the spot prices are point downwards also means that companies with not so great contract pricing are starting to want to renegotiate their contract pricing, as even a small saving here can lead to a bigger saving further down the line. Many IC manufacturers have also asked to pause their contract orders, as the utilisation rate of many foundry nodes are going down, which means the foundries aren't in need of as many wafers as they have ordered. Hopefully this will all lead to lower prices across the board when it comes to semiconductors this year, but it's too early to draw any real conclusions. It's also possible that the end customers won't see any direct benefits from lower costs to the manufacturers.

Apple's ongoing pursuit of leading performance in custom silicon packages continues with each new generation of Apple Silicon. Today, we have alleged Geekbench performance figures of the upcoming M2 Max chip, designed for the upcoming Mac devices. Featuring the same configuration with two E-cores and eight P-cores, the chip is rumored to utilize TSMC's 3 nm design. However, that is yet to be confirmed by Apple, so we don't have the exact information. In the GB5 single-thread test, the CPU set a single-core performance target of 1899 points, while the multi-core score was 8737. While last year's M1 Max chips can reach 1787 single-core and 12826 multi-core scores, these configurations are benchmarked in a Mac Studio, which has better cooling and allows for higher clocks to be achieved.

Apples to apples (pun intended) comparison with the M1 Max chip inside of a MacBook Pro version with presumably the same cooling capacity, which gets 1497 single-core and 11506 multi-core score, the new M2 Max chip is 19.4% faster in single-core results. Multi-core improvements should follow, and this M2 Max result should be different from the final product. We await more benchmarks to confirm this performance increase and the correct semiconductor manufacturing node.

Back in September 2021, reports about Intel working on something called SDSi or software defined silicon, started to appear. Now, over a year later, the company has finally launched its SDSi products under the Intel On Demand branding. Back then, we speculated about what features Intel would put behind a paywall and although we were somewhat off track, Intel has put some specific "instructions" behind the paywall on the supported Xeon processors. Specifically, some CPUs will have Quick Assist, Dynamic Load Balancer and Data Streaming Accelerator available as an On Demand feature. Additionally, Intel is also putting its Software Guard Extensions and In-Memory Analytics Accelerator behind the same pay wall.

It appears that these features will be offered as-a-service offering from some of Intel's service partners, but there's also a "one-time activation of select CPU accelerators and security features" according to the Intel On Demand website. It's unclear which Xeon SKUs will get Intel On Demand, but according to The Register, it'll be the upcoming Sapphire Rapids based Xeon processors which should be the first parts affected. Intel has listed partners like HP, Lenovo and SuperMicro, among others, that are involved with the Intel On Demand program. It will still be possible to buy next gen Xeon CPUs that are fully feature enabled like today, but it's unclear if the Intel On Demand Xeon SKUs will offer some kind of cost benefits to companies that don't need the additional features that are behind the paywall.

According to Dylan Patel of SemiAnalysis sources, Apple is moving its embedded cores from Arm to RISC-V. In Apple's Silicon designs, there are far more cores than the main ones that power the operating system and end-user applications. For example, embedded cores are present, and there are 30+ in M1 SoCs responsible for all kinds of workloads not related to the operating system. These tasks are usually associated with other functions such as WiFi/BlueTooth, ThunderBolt retiming, touchpad control, NAND chips having their own core, etc. They run their own firmware and power everything around the central cores that run the OS, so the whole SoC functions appropriately.

It appears that a lot of these cores are based on Arm M-series or lower-end A-series IP that Apple is currently looking to replace with RISC-V. Given that a large portion of software runs on the main big.LITTLE configuration, other secondary SoC tasks can migrate to a different ISA like RISC-V, with a small firmware adjustment. Given that these cores can be placed with custom IPs, Apple would save licensing fees if custom RISC-V cores were used. Additionally, developing firmware for these cores at an Apple engineering team size shouldn't be a problem. Of course, we have no information about when these custom cores will appear inside Apple Silicon. Even when they are used, no formal announcement is expected given that the main cores remain to be powered by Arm ISA, with everything else invisible to the end-user.

POINTek, Inc., a global leader and provider of high performance athermal AWGs, announced launching of new Application- Specific Optical Fiber Array Products, Silicon Photonics (SiPh) Fiber Arrays, which is capable of supporting the back-end packaging for Silicon Photonics Integrated Circuits (PIC). This new Silicon Photonics Fiber Arrays have the excellent characteristics of a fine fiber-end mirror-surface quality and an accurate fiber protrusion length uniformity to match with the prefabricated V-grooves on a Silicon PIC chip. The required fiber protrusion length is typically 5 mm with ≤ ±2 um length uniformity in an array. Both Single Mode (SM) Fiber Arrays and Polarization Maintaining (PM) Fiber Arrays are available with or without 12-channel MT ferrule termination.

"This new SiPh Fiber Array is designed to passively align the multiple optical fibers into the wafer-fabricated V-grooves on the Silicon PIC chip without the expensive and complicated active alignment equipment, and furthermore, the passive alignment of the Array can be accomplished without monitoring the optical power," according to Dr. Donald Yu, CMO of POINTek, operating from Los Angeles, California. Yu explains that the optical fiber array is a key component to efficiently assemble the PIC devices for coupling the multiple fibers into the multiple I/O waveguides on a PIC chip. In the conventional optical active alignment assembly process, the expensive automatic precision alignment equipment should be utilized while monitoring the optical power in the packaging process, and it often takes the long processing time. "However, for this new SiPh Fiber Array, the fibers can be precisely placed in the Silicon PIC's V-grooves with the minimal operation costs. Therefore, the passive alignment of Silicon PIC could result in the very affordable SiPh device price in the market," Yu adds.

Today, leading global fabless chipmaker MediaTek Inc., [joined by Indiana Governor Eric J. Holcomb, Deputy Secretary of Commerce Don Graves, Indiana Secretary of Commerce Bradley B. Chambers, and Purdue College of Engineering's Dr. Mung Chiang] announced their commitment to accept a state transition assistance package from the Indiana Economic Development Commission (IEDC) to support its very first Midwest semiconductor chip design center in West Lafayette, Indiana. MediaTek also shared its intention to create a new research partnership with Purdue to collaborate on engineering talent development and new research on next-generation computing and communications chip design. The news was shared with senior leaders, other international investors and policymakers assembled in National Harbor, Maryland for the 2022 SelectUSA Investment Summit.

This novel partnership in Indiana represents a new U.S. growth model for MediaTek USA; outside the traditional centers of gravity for chip design. "We believe strongly that being in Indiana means we'll have access to some of the best engineering talent in the world," said Dr. Kou-Hung Lawrence Loh, Corporate Senior Vice President of MediaTek Inc. and President of MediaTek USA, Inc. "Not just at Purdue, but West Lafayette is only four hours away from nearly a dozen of the top engineering schools in the country. In the post pandemic world, top candidates tell us they want to be closer to home, near family and they want to have a real house and great schools. Indiana offers all that and more."