Samsung stands as a technology giant in the industry, with tendrils stretching out towards almost every conceivable area of consumer, prosumer, and professional markets. It is also one of the companies which can actually bring up the fight to Intel when it comes to semiconductor manufacturing, with some analysts predicting the South Korean will dethrone Intel as the top chipmaker in Q2 of this year. Samsung scales from hyper-scale data centers to the internet-of-things, and is set to lead the industry with 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. The new Samsung roadmap shows how committed the company is (and the industry with it) towards enabling the highest performance possible from the depleting potential of the silicon medium. The 4 nm "post FinFET" structure process is set to be in risk production by 2020.

This announcement also marks Samsung's reiteration on the usage of EUV (Extreme Ultra Violet) tech towards wafer manufacturing, a technology that has long been hailed as the savior of denser processes, but has been ultimately pushed out of market adoption due to its complexity. Kelvin Low, senior director of foundry marketing at Samsung, said that the "magic number" for productivity (as in, with a sustainable investment/return ratio) with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry's first multi-node FD-SOI roadmap. Building on the success of its 22FDXTM offering, the company's next-generation 12FDXTM platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

As the world becomes more and more integrated through billions of connected devices, many emerging applications demand a new approach to semiconductor innovation. The chips that make these applications possible are evolving into mini-systems, with increased integration of intelligent components including wireless connectivity, non-volatile memory, and power management-all while driving ultra-low power consumption. GLOBALFOUNDRIES' new 12FDX technology is specifically architected to deliver these unprecedented levels of system integration, design flexibility, and power scaling.

Silicon Lottery at OCN got their hands on Intel's upcoming flagship high-end desktop (HEDT) processor, the Core i7-6950X. Based on the 14 nm "Broadwell-E" silicon, the processor offers a staggering 10 cores, with HyperThreading enabling 20 logical CPUs, 25 MB L3 cache, and a quad-channel DDR4 memory controller. The i7-6950X is expected to occupy a price point that's above the $999 traditionally reserved for the top-end HEDT chip. Silicon Lottery successfully overclocked the i7-6950X to 4.50 GHz, from its rumored stock frequency of 3.00 GHz, and compared it to a previous-generation Core i7-5960X 8-core processor. The common platform consisted of an ASUS Rampage V Extreme motherboard, 16 GB of quad-channel DDR4-3000 memory, and GeForce GTX 750 Ti graphics.

At its top overclock of 4.50 GHz, the i7-6950X achieved a Cinebench R15 score of 2327 points. At 4.00 GHz, it scored 1904 points, 19.5 percent higher than the i7-5960X at the same clocks (the i7-6950X features two extra cores). The two chips were also put through AIDA64 memory tests. The memory read speeds were nearly the same, but the memory write speeds were found to be a staggering 37 percent higher on the i7-6950X. The memory copy speeds, however, were 10.5 percent lower on the i7-6950X. Intel is expected to launch its next-generation Core i7 HEDT lineup, including two six-core, one eight-core, and one ten-core chips, in a few weeks from now.

NVIDIA's upcoming high-end single-GPU graphics card, based on the GM200 silicon, which debuted with the GTX TITAN X, will feature a silicon marked "GM200-310." The SKU will be named GeForce GTX 980 Ti, and is more likely to be priced around the $600-650 mark, than replacing the $550 GTX 980 off the shelves. Going by the way NVIDIA re-positioned the GTX 780 to $499 with the introduction of the GTX 780 Ti, we imagine something similar could happen to the GTX 980. From what we gathered so far, the GTX 980 Ti will be based on the GM200 silicon. Its CUDA core count is unknown, but it wouldn't surprise us if it's unchanged from the GTX TITAN X. Its different SKU numbering shouldn't be an indication of its CUDA core count. GTX 780 Ti and GTX TITAN Black had different numbering, but the same CUDA core counts of 2,880.

The card will feature 6 GB of GDDR5 memory across the chip's 384-bit wide memory interface. It will feature five display outputs, similar to that of the GTX 980. Unlike with the GTX TITAN X, NVIDIA partners will have the freedom to launch custom-design GTX 980 Ti products from day-one. There are two theories doing rounds on when NVIDIA plans to launch this card. One suggests that it could launch in mere weeks from now, probably even on the sidelines of Computex. The other suggests that it will launch towards the end of Summer, as NVIDIA wants to make the most cash from its existing GTX 980 inventory.

During her keynote at the Intel Developer Forum today in Beijing, Diane Bryant, senior vice president and general manager of Intel's Datacenter and Connected Systems Group, discussed how her company is helping users harness powerful new capabilities that will improve the lives of people by building smarter cities, healthier communities and thriving businesses.

Bryant unveiled details of upcoming technologies and products that show how Intel aims to transform the server, networking and storage capabilities of the datacenter. By addressing the full spectrum of workload demands and providing new levels of application optimized solutions for enterprise IT, technical computing and cloud service providers, unprecedented experiences can be delivered.

IBM announced today a major advance in the ability to use light instead of electrical signals to transmit information for future computing. The breakthrough technology - called "silicon nanophotonics" - allows the integration of different optical components side-by-side with electrical circuits on a single silicon chip using, for the first time, sub-100 nm semiconductor technology.

Silicon nanophotonics takes advantage of pulses of light for communication and provides a super highway for large volumes of data to move at rapid speeds between computer chips in servers, large datacenters, and supercomputers, thus alleviating the limitations of congested data traffic and high-cost traditional interconnects.

TSMC today announced that it has taped out the foundry segment's first CoWoS (Chip on Wafer on Substrate) test vehicle using JEDEC Solid State Technology Association's Wide I/O mobile DRAM interface. The milestone demonstrates the industry's system integration trend to achieve increased bandwidth, higher performance and superior energy efficiency.

This new generation of TSMC's CoWoS test vehicles added a silicon proof point demonstrating the integration of a logic SoC chip and DRAM into a single module using the Wide I/O interface. TSMC's CoWoS technology provides the front-end manufacturing through chip on wafer bonding process before forming the final component. Along with Wide I/O mobile DRAM, the integrated chips provide optimized system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth.

Intel Corporation today announced it has entered into a series of agreements with ASML Holding N.V. intended to accelerate the development of 450-millimeter (mm) wafer technology and extreme ultra-violet (EUV) lithography totaling €3.3 billion (approximately $4.1 billion). The objective is to shorten the schedule for deploying the lithography equipment supporting these technologies by as much as two years, resulting in significant cost savings and other productivity improvements for semiconductor manufacturers.

To achieve this, Intel is participating in a multi-party development program that includes a cash contribution by Intel to fund relevant ASML research and development (R&D) efforts as well as equity investments in ASML. The first phase of this program consists of Intel committing to R&D funding of €553 million (approximately $680 million) to assist ASML in accelerating the development and delivery of 450-mm manufacturing tools, as well as an equity investment of €1.7 billion (approximately $2.1 billion) for approximately 10 percent of ASML's pre-transaction issued shares. Intel will record the R&D investment as a combination of R&D expense and pre-payments on future tool deliveries.

Mentor Graphics Corp. today announced that GLOBALFOUNDRIES is helping its customers improve reliability checking by adding Calibre PERC to select 28nm bulk CMOS design enablement flows. Calibre PERC will give designers access to the new reliability verification rules developed by the IBM Semiconductor Development Alliance (ISDA), augmented with GLOBALFOUNDRIES specific checks to help prevent external latch-up. Using Calibre PERC's unique architecture, complex reliability rules that require the integration of logical (net list) and layout (GDS) information can be fully automated, eliminating manual spreadsheet-based efforts and reducing the chances of design errors.

"In the past, verification of latch-up immunity depended on manual layout checks and rough approximations of device and interconnect resistance using traditional mechanisms," said Bill Liu, vice president of design enablement at GLOBALFOUNDRIES. "Now our customers can perform accurate measurements and analysis automatically using Calibre PERC's data integration capability. For example, some of our customers are currently using PERC to accurately determine the resistance of the paths in complex output driver arrays as a function of device spacing. This allows them to easily and accurately detect points in the circuit where latch-up could be an issue and to make appropriate improvements."

GLOBALFOUNDRIES today announced a significant milestone on the road to enabling 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, NY, the company has begun installation of a special set of production tools to create Through-Silicon Vias (TSVs) in semiconductor wafers processed on the company's leading-edge 20nm technology platform. The TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding requirements of tomorrow's electronic devices.

Essentially vertical holes etched in silicon and filled with copper, TSVs enable communication between vertically stacked integrated circuits. For example, the technology could allow circuit designers to place stacks of memory chips on top of an application processor, which can dramatically increase memory bandwidth and reduce power consumption-a key challenge for designers of the next generation of mobile devices such as smartphones and tablets.

Biwin today announced the opening of Biwin America, Inc., in San Jose, California to develop and market new flash based SSD storage solutions for enterprise, embedded and client applications.

Biwin is already an established leader in OEM and ODM USB flash drives. The company boasts impressive manufacturing strength that includes die sorting and packaging, over 20 SMT lines, and sophisticated test and QC processes. The founding of Biwin America, Inc., in the heart of Silicon Valley, marks the company's expansion into the USA market with a focus on expanding their existing SSD product portfolio. The company will sell its products directly to OEMs as well as through distribution.

Common Platform, a consortium of three major silicon fabrication companies: IBM, Samsung, and GlobalFoundries, met at their 2012 Technology Forum, where they announced their intention to transition to FinFET 3D transistor technology, but only with the 14 nanometer (nm) silicon fabrication process. Chips on this process will be built in the 2014~2015 time-frame. 3D transistors is a technology pioneered by Intel, which provides space-optimized, energy-efficient transistors on a nano-scale.

FinFET transistors will be combined with Fully Depleted Silicon-On-Insulator (FD-SOI) to offer extremely high transistor densities, with lower chip power. FD-SOI overcomes the limitation of current partially-depleted SOI (PD-SOI) technology, of lower-yields due to the pressure required for SOI insulation, which nears the breaking-point of strained silicon transistors. FinFET tech will be combined with chip-stacking technology, which helps make devices with better use of available PCB footprint.

Cyclos Semiconductor, the inventor and only supplier of resonant clock mesh technology for commercial IC designs, today announced at the International Solid State Circuits Conference (ISSCC) in San Francisco, CA that AMD has successfully implemented Cyclos' low-power semiconductor intellectual property (IP) in the AMD x86 core destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP to reduce power consumption demonstrates the commitment AMD has made to provide its customers with not only class-leading APU performance but also with the lowest possible power consumption.

AMD's 4+ GHz x86-64 core code-named "Piledriver" employs resonant clocking to reduce clock distribution power up to 24% while maintaining the low clock-skew target required by high-performance processors. Fabricated in a 32nm CMOS process, Piledriver represents the first volume production-enabled implementation of resonant clock mesh technology. "We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule," said Samuel Naffziger, Corporate Fellow at AMD. "Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs."

Silicon Image (NASDAQ: SIMG), a leading provider of wireless and wired HD connectivity solutions, today announced the opening of its newest research and development (R&D) center in Hyderabad, India. Opened on January 27, 2012, the facility located in Hyderabad's technology hub, focuses on the design and development of semiconductor and IP core technologies for implementation in mobile, wireless and consumer electronics (CE) products from manufacturers across the globe.

"The technology innovation and growth occurring in Hyderabad made the location a natural fit for Silicon Image's expanding R&D portfolio," said Rashid Osmani, vice president of worldwide engineering at Silicon Image, Inc. "The expertise of Silicon Image's worldwide engineering team has been strengthened by the addition of the talented engineers in Hyderabad, who we foresee becoming an integral part of new product development."

News of quantum breakthroughs seem to be coming every few months now, edging ever closer towards the hallowed goal of building a quantum computer using quantum qubits rather than classical bits and bringing colossal improvements in computational power. This will eventually lead to applications that we can't even imagine now and possibly a true artificial intelligence of the kind one sees in the movies. Also, it would allow calculations that would normally take longer than the lifetime of the universe on a classical computer to be made in just a few seconds or minutes on a quantum one. A goal well worth striving for.

The latest breakthrough comes from the University of New South Wales, Melbourne University and Purdue University who have developed the smallest wire yet. It's a silicon nanowire, having the tiny dimensions of just one atom high and four atoms wide. This is a feat in itself, but the crucial part is that the wire is able to maintain its resistivity even at this atomic level, making it far easier for current to flow, thereby preventing the tiny wire from becoming useless. This will help with the continuation of Moore's Law, giving us ever more powerful computers at the present rate and opens the door to quantum computing within the next decade.

TechEYE has a more detailed article about this development. This is based on an ABC Radio interview with Michelle Simmons from the University of New South Wales and makes for fascinating listening.

NVIDIA announced today that it has named Rob Burgess, a veteran technology executive and independent consultant, to its board of directors. Burgess, age 53, served as chief executive officer of Macromedia, Inc., a provider of Internet and multimedia software, from 1996 to 2005, and as the company's chairman or executive chairman from 1998 to 2005, when it was acquired by Adobe Systems Inc. He has been a member of Adobe's board since then, and has served since 2010 as a director of IMRIS Inc., a provider of image-guided therapy solutions.

AMD (NYSE: AMD) announced today that Mark Papermaster, 50, has joined as the company's senior vice president and chief technology officer. He will report to President and Chief Executive Officer Rory Read and will oversee all of AMD's engineering, research and development (R&D), and product development functions as the head of the newly-formed Technology and Engineering Group. Papermaster, who was most recently vice president of Silicon Engineering at Cisco, will be responsible for establishing and executing the company's technology and product roadmaps, integrated hardware and software development, and overseeing the creation of all of AMD's products.

The advanced research and development team led by Senior Vice President of Research and Development Chekib Akrout, as well as the engineering teams residing in AMD's Products Group, will now report to Papermaster. Akrout, 53, will maintain responsibility for leading AMD's processor core development as well as system-on-a-chip (SoC) design methodology. In recognition of his ongoing technical and management contributions, Akrout will continue serving on AMD's senior leadership team responsible for key decision making and strategy setting.

Elpida Memory, Inc., Japan's leading global supplier of Dynamic Random Access Memory (DRAM), today announced that it had completed development of a 30nm process 2-gigabit DDR3 SDRAM. The new 2-gigabit DDR3 SDRAM used 30nm-level advanced process migration technology to create the DRAM industry's smallest-level 2-gigabit DDR3 SDRAM. It achieves 45% more chips per wafer compared with Elpida's 40nm process products. Also, the new process design developed by Elpida will help contain rising chip costs associated with process migration. As a result, the 2-gigabit DDR3 is slated to become an extremely cost-competitive product.

Elpida's new chip meets the JEDEC specs for the high-speed DDR3-1866 and 1.35V low-voltage, high-speed DDR3L-1600 memory chips, both expected to become mainstream industry products in 2011. Also, the 30nm DDR3 SDRAM is eco-friendly. As a DDR3 SDRAM it achieves one of the industry's lowest levels of electric current usage (approximately 15% less operating and approximately 10% less standby usage compared with Elpida's 40nm products), which contributes to lower PC and digital consumer electronics power consumption.

At next week's Design Automation Conference (DAC), GLOBALFOUNDRIES will unveil a new platform to spur innovation in semiconductor manufacturing and help deliver unparalleled service to chip designers. Called GLOBALSOLUTIONS, the new ecosystem combines the company's internal resources with a broad spectrum of partners to efficiently enable the fastest time-to-volume for foundry customers.

"As chip design grows in complexity and manufacturing partnerships become increasingly critical, foundry customer enablement needs to extend beyond process design kits and reference flows to include the full spectrum of the semiconductor value chain," said Jim Kupec, senior vice president of worldwide sales and marketing at GLOBALFOUNDRIES. "To this end, GLOBALSOLUTIONS includes ecosystem partners in all aspects of design enablement, turnkey services, design for manufacturability, optical proximity correction and mask operations, and will further expand our capabilities in advanced assembly solutions. This will allow our customers to unlock their innovation potential and differentiate at all levels of the design process, from the silicon and SoC level all the way up to the full system."

DisplayLink Corp. today celebrated reaching sales of more than one million USB graphics semiconductors. Embedded in more than thirty consumer and business products, DisplayLink chips - the DL-120 and DL-160 - make it possible for people to connect various visual computing devices to displays with an easy USB connection.

"DisplayLink has completely reinvented the way computers talk to displays. Our IC's make it possible to use standard plug and play USB to connect a laptop to one or more displsys, bringing the world a major step closer to the ideal "single world connector" status. Achieving sales of one million chips clearly shows the mainstream reach of our technology with customers and end-users who readily appreciate the simplicity of our approach and the productivity benefits of using multiple displays" said Hamid Farzaneh, president and CEO of DisplayLink.

Western Digital Corp., a world leader in hard drive storage for computing and consumer electronics applications, today announced that it has completed a $65 million cash acquisition of SiliconSystems, Inc., Aliso Viejo, Calif., a leading supplier of solid-state drives for the embedded systems market.

Since its inception in 2002, SiliconSystems has sold millions of SiliconDrive products to meet the high performance, high reliability and multi-year product lifecycle demands of the network-communications, industrial, embedded-computing, medical, military and aerospace markets. These markets accounted for approximately one third of worldwide solid-state drive revenues in 2008. SiliconSystems' product portfolio includes solid-state drives with SATA, EIDE, PC Card, USB and CF interfaces in 2.5-inch, 1.8-inch, CF and other form factors. SiliconSystems has developed extensive intellectual property to address the stringent embedded systems market requirements to ensure data integrity, eliminate unscheduled downtime, protect application data and software and provide for data security and protection through its patented and patent-pending PowerArmor, SiSMART, SolidStor and SiSecure technologies.

The SOI Industry Consortium has announced that NVIDIA has joined the organization. NVIDIA now joins a league of companies such as AMD, Applied Materials, ARM, Cadence Design Systems, CEA-Léti, Chartered Semiconductor Manufacturing, Freescale Semiconductor, IBM, Innovative Silicon, KLA-Tencor, Lam Research, Magma Design, Samsung, Semico, Soitec, SEH Europe, STMicroelectronics, Synopsys, Taiwan Semiconductor Manufacturing Company (TSMC), Tyndall Institute, UCL and United Microelectronics Corporation (UMC).

So what is SOI? Silicon on Insulator technology involves use of variable layered silicon-insulator-silicon substratum, used to minimize parasitic device capacitance and thereby improve performance.

US engineers at Princeton University have managed to develop a new method for producing computer chips using carbon instead of the silicon used in current chips. As silicon is now reaching its limit, researchers have been searching for an alternative material to use for the last few years. Graphene, which is a single layer of carbon atoms arranged in a honeycomb lattice, could potentially process information and produce radio transmissions ten times more efficiently than silicon, which makes it an ideal replacement. The problem until now has been that engineers believed that they would need graphene in the same form as silicon to make chips, which would require a single crystal 8" or 12" wide. Graphene crystals have only been made a couple of millimetres wide so far, which is not big enough to produce chips. However, the new technique involves using small crystals of graphene in the active part of the chip, which would not require a big wafer. This could help to fuel future chip development and allow for much faster computers.