According to the World Semiconductor Trade Statistics (WSTS) organization, the semiconductor manufacturing world has just seen one of the largest contractions in the last 35 years. The downturn on produced revenue for manufacturers for the month of March consolidated into a decline of 1.8% compared to February of this year, and a decline of 13% when compared to March 2018 - but quarter-reviewed revenues were even worse. In greenback terms, the semiconductor industry saw a decline from $114.7 billion in the previous quarter to "just" $96.8 billion.

The decline was across all semiconductor product categories, as John Neuffer, president and CEO of the Semiconductor Industry Association (SIA) trade group, said: "Sales in March decreased on a year-to-year basis across all major regional markets and semiconductor product categories, consistent with the cyclical trend the global market has experienced recently." Market analysis firm IC Insights says that the decline was more severe than the WSTS reports, and that it totaled a 17.1% reduction in revenue for the first quarter of this year, making it the fourth biggest decline since 1984. As IC Insights said in a statement, "The first quarter is usually the weakest quarter of the year for the IC market, averaging a sequential decline of 2.1% over the past 36 years, but the severity of the 1Q19/4Q18 IC market drop has started this year off at a very low level."

TSMC announced they've completed the infrastructure design for the 5 nm process, which is the next step in silicon evolution when it comes to density and performance. TSMC's 5 nm process will leverage the company's second implementation of EUV (Extreme Ultra Violet) technology (after it's integrated in their 7 nm process first), allowing for improved yields and performance benefits.

According to TSMC, the 5 nm process will enable up to 1.8x the logic density of their 7 nm process, a 15% clock speed gain due to process improvements alone on an example Arm Cortex-A72 core, as well as SRAM and analog circuit area reduction, which means higher number of chips per wafer. The process is being geared for mobile, internet, and high performance computing applications. TSMC also provides online tools for silicon design flow scenarios that are optimized for their 5 nm process. Risk production is already ongoing.

AMD's senior VP of AMD's datacentre group Forrest Norrod, at the Rice Oil and Gas HPC conference, said that while graphene does have incredible promise for the world of computing, it likely will take some ten years before such exotic material are actually taken advantage off. As Norrod puts it, silicon still has a pretty straightforward - if increasingly complex - path down to 3 nanometer densities. And according to him, at the rate manufacturers are being able to scale down their production nodes further, the average time between node transitions stands at some four or five years - which makes the jump to 5 nm and then 3 nm look exactly some 10 years from now, where Norrod expects to go through two additional shrinking nodes for the manufacturing process.

Of course, graphene is being hailed as the next best candidate for taking over silicon's place at the heart of our more complex, high-performance electronics, due, in part, to its high conductivity independent of temperature variation and its incredible switching resistance - it has been found to be able to operate at Terahertz switching speeds. It's a 2D material, which means that implementations of it will have to occur in deposited sheets of graphene across some other material.

The race for smaller fabrication processes has become more and more expensive, and the expenses in R&D and factory retooling only look to increase. This - alongside the expected increase in demand from silicon-embedded products, which are almost all of them - means that additional funding will be poured into chip manufacturing capabilities. A report from SEMI indicates that the 14% increased investment in 2018 to $62.8 billion will increase a further 7.5% next year, reaching capital expenditure of $67.5 billion in 2019.

3D NAND fabrication plants lead the charge in investment, even if the market is facing some issues stemming from oversupply. The demand growth is being taken into account for these new expansion plans, however, with denser and denser chips being required for all manner of products. This is part of the reason why 43% of this years' spending has been allotted to new NAND factories, but the ratio for 2019 is a much lower 19% increase.

Silicon Lottery is an online retailer that sells computer hardware its employees personally bin to pick out the best performing parts, at higher-than-MSRP prices. It listed its pricing for the upcoming Intel Core i9-9900K 8-core/16-thread processor, and the Core i7-9700K 8-core/8-thread part. The site currently reports both parts as "sold out" either because they've actually sold out all their pre-order inventory, or because they have't built inventories yet. Regardless, the i9-9900K is listed at USD $479.99, and the i7-9700K at $369.99.

We've been actively tracking down possible list prices of Intel's 9th generation Core processors. Our most recent article on the topic predicts the i9-9900K to be priced around $450, the i7-9700K at $350, and the i5-9600K at $250. Either Silicon Lottery's listings don't include any premiums, or Intel could surprise us with prices lower than our predictions.

With Moore's Law being pronounced as within its death throes, historic monolithic die designs are becoming increasingly expensive to manufacture. It's no secret that both AMD and NVIDIA have been exploring an MCM (Multi-Chip-Module) approach towards diverting from monolithic die designs over to a much more manageable, "chiplet" design. Essentially, AMD has achieved this in different ways with its Zen line of CPUs (two CPU modules of four cores each linked via the company's Infinity Fabric interconnect), and their own R9 and Vega graphics cards, which take another approach in packaging memory and the graphics processing die in the same silicon base - an interposer.

Silicon wafers are definitely the best kind of wafers for us tech enthusiasts, but as we all know, required financial resources for the development and production of these is among the most intensive in development costs and R&D. It's not just about the cost of employing enough (and crucially, good enough) engineers that can employ the right tools and knowledge to design the processing miracles that are etched onto wafers; there's also the cost of good, old production as well. Extreme Ultraviolet Lithography Systems that are used for the production of silicon wafers are about the size of a city bus, and typically cost more than 100 million euros ($115.3 million) each. ASML, a Dutch company that specializes in this kind of equipment, announced this year it was expecting to see a 25% revenue growth for 2017. Increased demand for these systems - and added cost of development of ever increasingly small and complex etchings in wafers - means this sector is seeing strong growth. But where there is strong growth, there is usually high demand, and high demand means higher strain on supply, which may sometimes not be able to keep up with the market's needs.

This is seemingly the case for wafer pricing; as demand for wafer production has been increasing, so to are prices. Faced with increased demand, companies are usually faced with a tough question to answer in regards to the correct course of action. Usually, it goes like this: higher demand at the same supply level means higher pricing. However, if supply isn't enough to satisfy demand, manufacturers are losing out on potential increased sales. This leads most companies to increase supply relative to demand, but always with lower projected output than demand requires, so they can bask in both increased ASP (Average Sale Price) and higher number of sales. This has been the case with DRAM memory production for some time now: and is happening with 300 mm silicon wafers as well.

Graphene has been hailed for some time now as the next natural successor to silicon, today's most used medium for semiconductor technology. However, even before such more exotic solutions to current semiconductor technology are employed (and we are still way off that future, at least when it comes to mass production), engineers and researchers seem to be increasing their focus in one specific part of computing: internal communication between components.

Typically, communication between a computer's Central Processing Unit (CPU) and a system's memory (usually DRAM) have occurred through a bus, which is essentially a communication highway between data stored in the DRAM, and the data that the CPU needs to process/has just finished processing. The fastest CPU and RAM is still only as fast as the bus, and recent workloads have been increasing the amount of data to be processed (and thus transferred) by orders of magnitude. As such, engineers have been trying to figure out ways of increasing communication speed between the CPU and the memory subsystem, as it is looking increasingly likely that the next bottlenecks in HPC will come not through lack of CPU speed or memory throughput, but from a bottleneck in communication between those two.

Samsung stands as a technology giant in the industry, with tendrils stretching out towards almost every conceivable area of consumer, prosumer, and professional markets. It is also one of the companies which can actually bring up the fight to Intel when it comes to semiconductor manufacturing, with some analysts predicting the South Korean will dethrone Intel as the top chipmaker in Q2 of this year. Samsung scales from hyper-scale data centers to the internet-of-things, and is set to lead the industry with 8nm, 7nm, 6nm, 5nm, 4nm and 18nm FD-SOI in its newest process technology roadmap. The new Samsung roadmap shows how committed the company is (and the industry with it) towards enabling the highest performance possible from the depleting potential of the silicon medium. The 4 nm "post FinFET" structure process is set to be in risk production by 2020.

This announcement also marks Samsung's reiteration on the usage of EUV (Extreme Ultra Violet) tech towards wafer manufacturing, a technology that has long been hailed as the savior of denser processes, but has been ultimately pushed out of market adoption due to its complexity. Kelvin Low, senior director of foundry marketing at Samsung, said that the "magic number" for productivity (as in, with a sustainable investment/return ratio) with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable.

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry's first multi-node FD-SOI roadmap. Building on the success of its 22FDXTM offering, the company's next-generation 12FDXTM platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

As the world becomes more and more integrated through billions of connected devices, many emerging applications demand a new approach to semiconductor innovation. The chips that make these applications possible are evolving into mini-systems, with increased integration of intelligent components including wireless connectivity, non-volatile memory, and power management-all while driving ultra-low power consumption. GLOBALFOUNDRIES' new 12FDX technology is specifically architected to deliver these unprecedented levels of system integration, design flexibility, and power scaling.

Silicon Lottery at OCN got their hands on Intel's upcoming flagship high-end desktop (HEDT) processor, the Core i7-6950X. Based on the 14 nm "Broadwell-E" silicon, the processor offers a staggering 10 cores, with HyperThreading enabling 20 logical CPUs, 25 MB L3 cache, and a quad-channel DDR4 memory controller. The i7-6950X is expected to occupy a price point that's above the $999 traditionally reserved for the top-end HEDT chip. Silicon Lottery successfully overclocked the i7-6950X to 4.50 GHz, from its rumored stock frequency of 3.00 GHz, and compared it to a previous-generation Core i7-5960X 8-core processor. The common platform consisted of an ASUS Rampage V Extreme motherboard, 16 GB of quad-channel DDR4-3000 memory, and GeForce GTX 750 Ti graphics.

At its top overclock of 4.50 GHz, the i7-6950X achieved a Cinebench R15 score of 2327 points. At 4.00 GHz, it scored 1904 points, 19.5 percent higher than the i7-5960X at the same clocks (the i7-6950X features two extra cores). The two chips were also put through AIDA64 memory tests. The memory read speeds were nearly the same, but the memory write speeds were found to be a staggering 37 percent higher on the i7-6950X. The memory copy speeds, however, were 10.5 percent lower on the i7-6950X. Intel is expected to launch its next-generation Core i7 HEDT lineup, including two six-core, one eight-core, and one ten-core chips, in a few weeks from now.

NVIDIA's upcoming high-end single-GPU graphics card, based on the GM200 silicon, which debuted with the GTX TITAN X, will feature a silicon marked "GM200-310." The SKU will be named GeForce GTX 980 Ti, and is more likely to be priced around the $600-650 mark, than replacing the $550 GTX 980 off the shelves. Going by the way NVIDIA re-positioned the GTX 780 to $499 with the introduction of the GTX 780 Ti, we imagine something similar could happen to the GTX 980. From what we gathered so far, the GTX 980 Ti will be based on the GM200 silicon. Its CUDA core count is unknown, but it wouldn't surprise us if it's unchanged from the GTX TITAN X. Its different SKU numbering shouldn't be an indication of its CUDA core count. GTX 780 Ti and GTX TITAN Black had different numbering, but the same CUDA core counts of 2,880.

The card will feature 6 GB of GDDR5 memory across the chip's 384-bit wide memory interface. It will feature five display outputs, similar to that of the GTX 980. Unlike with the GTX TITAN X, NVIDIA partners will have the freedom to launch custom-design GTX 980 Ti products from day-one. There are two theories doing rounds on when NVIDIA plans to launch this card. One suggests that it could launch in mere weeks from now, probably even on the sidelines of Computex. The other suggests that it will launch towards the end of Summer, as NVIDIA wants to make the most cash from its existing GTX 980 inventory.

During her keynote at the Intel Developer Forum today in Beijing, Diane Bryant, senior vice president and general manager of Intel's Datacenter and Connected Systems Group, discussed how her company is helping users harness powerful new capabilities that will improve the lives of people by building smarter cities, healthier communities and thriving businesses.

Bryant unveiled details of upcoming technologies and products that show how Intel aims to transform the server, networking and storage capabilities of the datacenter. By addressing the full spectrum of workload demands and providing new levels of application optimized solutions for enterprise IT, technical computing and cloud service providers, unprecedented experiences can be delivered.

IBM announced today a major advance in the ability to use light instead of electrical signals to transmit information for future computing. The breakthrough technology - called "silicon nanophotonics" - allows the integration of different optical components side-by-side with electrical circuits on a single silicon chip using, for the first time, sub-100 nm semiconductor technology.

Silicon nanophotonics takes advantage of pulses of light for communication and provides a super highway for large volumes of data to move at rapid speeds between computer chips in servers, large datacenters, and supercomputers, thus alleviating the limitations of congested data traffic and high-cost traditional interconnects.

TSMC today announced that it has taped out the foundry segment's first CoWoS (Chip on Wafer on Substrate) test vehicle using JEDEC Solid State Technology Association's Wide I/O mobile DRAM interface. The milestone demonstrates the industry's system integration trend to achieve increased bandwidth, higher performance and superior energy efficiency.

This new generation of TSMC's CoWoS test vehicles added a silicon proof point demonstrating the integration of a logic SoC chip and DRAM into a single module using the Wide I/O interface. TSMC's CoWoS technology provides the front-end manufacturing through chip on wafer bonding process before forming the final component. Along with Wide I/O mobile DRAM, the integrated chips provide optimized system performance and a smaller form factor with significantly improved die-to-die connectivity bandwidth.

Intel Corporation today announced it has entered into a series of agreements with ASML Holding N.V. intended to accelerate the development of 450-millimeter (mm) wafer technology and extreme ultra-violet (EUV) lithography totaling €3.3 billion (approximately $4.1 billion). The objective is to shorten the schedule for deploying the lithography equipment supporting these technologies by as much as two years, resulting in significant cost savings and other productivity improvements for semiconductor manufacturers.

To achieve this, Intel is participating in a multi-party development program that includes a cash contribution by Intel to fund relevant ASML research and development (R&D) efforts as well as equity investments in ASML. The first phase of this program consists of Intel committing to R&D funding of €553 million (approximately $680 million) to assist ASML in accelerating the development and delivery of 450-mm manufacturing tools, as well as an equity investment of €1.7 billion (approximately $2.1 billion) for approximately 10 percent of ASML's pre-transaction issued shares. Intel will record the R&D investment as a combination of R&D expense and pre-payments on future tool deliveries.

Mentor Graphics Corp. today announced that GLOBALFOUNDRIES is helping its customers improve reliability checking by adding Calibre PERC to select 28nm bulk CMOS design enablement flows. Calibre PERC will give designers access to the new reliability verification rules developed by the IBM Semiconductor Development Alliance (ISDA), augmented with GLOBALFOUNDRIES specific checks to help prevent external latch-up. Using Calibre PERC's unique architecture, complex reliability rules that require the integration of logical (net list) and layout (GDS) information can be fully automated, eliminating manual spreadsheet-based efforts and reducing the chances of design errors.

"In the past, verification of latch-up immunity depended on manual layout checks and rough approximations of device and interconnect resistance using traditional mechanisms," said Bill Liu, vice president of design enablement at GLOBALFOUNDRIES. "Now our customers can perform accurate measurements and analysis automatically using Calibre PERC's data integration capability. For example, some of our customers are currently using PERC to accurately determine the resistance of the paths in complex output driver arrays as a function of device spacing. This allows them to easily and accurately detect points in the circuit where latch-up could be an issue and to make appropriate improvements."

GLOBALFOUNDRIES today announced a significant milestone on the road to enabling 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, NY, the company has begun installation of a special set of production tools to create Through-Silicon Vias (TSVs) in semiconductor wafers processed on the company's leading-edge 20nm technology platform. The TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding requirements of tomorrow's electronic devices.

Essentially vertical holes etched in silicon and filled with copper, TSVs enable communication between vertically stacked integrated circuits. For example, the technology could allow circuit designers to place stacks of memory chips on top of an application processor, which can dramatically increase memory bandwidth and reduce power consumption-a key challenge for designers of the next generation of mobile devices such as smartphones and tablets.

Biwin today announced the opening of Biwin America, Inc., in San Jose, California to develop and market new flash based SSD storage solutions for enterprise, embedded and client applications.

Biwin is already an established leader in OEM and ODM USB flash drives. The company boasts impressive manufacturing strength that includes die sorting and packaging, over 20 SMT lines, and sophisticated test and QC processes. The founding of Biwin America, Inc., in the heart of Silicon Valley, marks the company's expansion into the USA market with a focus on expanding their existing SSD product portfolio. The company will sell its products directly to OEMs as well as through distribution.

Common Platform, a consortium of three major silicon fabrication companies: IBM, Samsung, and GlobalFoundries, met at their 2012 Technology Forum, where they announced their intention to transition to FinFET 3D transistor technology, but only with the 14 nanometer (nm) silicon fabrication process. Chips on this process will be built in the 2014~2015 time-frame. 3D transistors is a technology pioneered by Intel, which provides space-optimized, energy-efficient transistors on a nano-scale.

FinFET transistors will be combined with Fully Depleted Silicon-On-Insulator (FD-SOI) to offer extremely high transistor densities, with lower chip power. FD-SOI overcomes the limitation of current partially-depleted SOI (PD-SOI) technology, of lower-yields due to the pressure required for SOI insulation, which nears the breaking-point of strained silicon transistors. FinFET tech will be combined with chip-stacking technology, which helps make devices with better use of available PCB footprint.

Cyclos Semiconductor, the inventor and only supplier of resonant clock mesh technology for commercial IC designs, today announced at the International Solid State Circuits Conference (ISSCC) in San Francisco, CA that AMD has successfully implemented Cyclos' low-power semiconductor intellectual property (IP) in the AMD x86 core destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). The adoption of the Cyclos resonant clock mesh IP to reduce power consumption demonstrates the commitment AMD has made to provide its customers with not only class-leading APU performance but also with the lowest possible power consumption.

AMD's 4+ GHz x86-64 core code-named "Piledriver" employs resonant clocking to reduce clock distribution power up to 24% while maintaining the low clock-skew target required by high-performance processors. Fabricated in a 32nm CMOS process, Piledriver represents the first volume production-enabled implementation of resonant clock mesh technology. "We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule," said Samuel Naffziger, Corporate Fellow at AMD. "Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs."

Silicon Image (NASDAQ: SIMG), a leading provider of wireless and wired HD connectivity solutions, today announced the opening of its newest research and development (R&D) center in Hyderabad, India. Opened on January 27, 2012, the facility located in Hyderabad's technology hub, focuses on the design and development of semiconductor and IP core technologies for implementation in mobile, wireless and consumer electronics (CE) products from manufacturers across the globe.

"The technology innovation and growth occurring in Hyderabad made the location a natural fit for Silicon Image's expanding R&D portfolio," said Rashid Osmani, vice president of worldwide engineering at Silicon Image, Inc. "The expertise of Silicon Image's worldwide engineering team has been strengthened by the addition of the talented engineers in Hyderabad, who we foresee becoming an integral part of new product development."

News of quantum breakthroughs seem to be coming every few months now, edging ever closer towards the hallowed goal of building a quantum computer using quantum qubits rather than classical bits and bringing colossal improvements in computational power. This will eventually lead to applications that we can't even imagine now and possibly a true artificial intelligence of the kind one sees in the movies. Also, it would allow calculations that would normally take longer than the lifetime of the universe on a classical computer to be made in just a few seconds or minutes on a quantum one. A goal well worth striving for.

The latest breakthrough comes from the University of New South Wales, Melbourne University and Purdue University who have developed the smallest wire yet. It's a silicon nanowire, having the tiny dimensions of just one atom high and four atoms wide. This is a feat in itself, but the crucial part is that the wire is able to maintain its resistivity even at this atomic level, making it far easier for current to flow, thereby preventing the tiny wire from becoming useless. This will help with the continuation of Moore's Law, giving us ever more powerful computers at the present rate and opens the door to quantum computing within the next decade.

TechEYE has a more detailed article about this development. This is based on an ABC Radio interview with Michelle Simmons from the University of New South Wales and makes for fascinating listening.

NVIDIA announced today that it has named Rob Burgess, a veteran technology executive and independent consultant, to its board of directors. Burgess, age 53, served as chief executive officer of Macromedia, Inc., a provider of Internet and multimedia software, from 1996 to 2005, and as the company's chairman or executive chairman from 1998 to 2005, when it was acquired by Adobe Systems Inc. He has been a member of Adobe's board since then, and has served since 2010 as a director of IMRIS Inc., a provider of image-guided therapy solutions.

AMD (NYSE: AMD) announced today that Mark Papermaster, 50, has joined as the company's senior vice president and chief technology officer. He will report to President and Chief Executive Officer Rory Read and will oversee all of AMD's engineering, research and development (R&D), and product development functions as the head of the newly-formed Technology and Engineering Group. Papermaster, who was most recently vice president of Silicon Engineering at Cisco, will be responsible for establishing and executing the company's technology and product roadmaps, integrated hardware and software development, and overseeing the creation of all of AMD's products.

The advanced research and development team led by Senior Vice President of Research and Development Chekib Akrout, as well as the engineering teams residing in AMD's Products Group, will now report to Papermaster. Akrout, 53, will maintain responsibility for leading AMD's processor core development as well as system-on-a-chip (SoC) design methodology. In recognition of his ongoing technical and management contributions, Akrout will continue serving on AMD's senior leadership team responsible for key decision making and strategy setting.