AMD in its 2nd generation EPYC processor launch event announced that it has completed the design phase of its next-generation "Zen 3" CPU microarchitecture, and is currently working on its successor, the "Zen 4." AMD debuted its "Zen 2" microarchitecture with the client-segment 3rd generation Ryzen desktop processor family, it made its enterprise debut with the 2nd generation EPYC. This is the first x86 CPU microarchitecture designed for the 7 nanometer silicon fabrication process, and is being built on a 7 nm DUV (deep ultraviolet) node at TSMC. It brings about double-digit percentage IPC improvements over "Zen+."

The "Zen 3" microarchitecture is designed for the next big process technology change within 7 nm, EUV (extreme ultraviolet), which allows significant increases in transistor densities, and could facilitate big improvements in energy-efficiency that could be leveraged to increase clock-speeds and performance. It could also feature new ISA instruction-sets. With "Zen 3" passing design phase, AMD will work on prototyping and testing it. The first "Zen 3" products could debut in 2020. "Zen 4" is being designed for a different era.

During our disassembly of the GeForce RTX 2060 Super, we noticed a shocking detail. The 12 nm "TU106" GPU on which it is based, has the marking "Korea." We know for a fact that TSMC does not have any fabs there. The only Korean semiconductor manufacturer capable of contract-manufacturing a piece of silicon as complex as a GPU, for a designer with the energy-efficiency OCD as NVIDIA, is Samsung.

What makes this interesting is that Samsung does not officially have a 12 nm FinFET process. It has 14 nm, and the 11LPP, a 11 nm nodelet, which the company designed to compete with TSMC 12 nm. It would hence be really interesting to hear from NVIDIA on whether they've scaled out the "TU106" to 14LPP, or down to 11LPP at Samsung. It's interesting to note that the shrink in transistor sizes in these nodelets doesn't affect die-sizes. We hence see no die-size difference between these Korea-marked chips, and those marked "Taiwan." We've reached out to NVIDIA for comment.

Update July 3rd: NVIDIA got back to us

NVIDIAThe answer is really simple and these markings are not new. Other Turing GPUs have had these markings in the past. The chip is made at TSMC, but packaged in various locations. This one was done in Korea, hence why his says "Korea".

On an unrelated note: We already use both TSMC and Samsung, and qualify each of them for every process node. We can't comment in any further detail on future plans, but both remain terrific partners.

Today an article was posted on Intel's internal employee-only portal called "Circuit News". The post, titled "AMD competitive profile: Where we go toe-to-toe, why they are resurgent, which chips of ours beat theirs" goes into detail about the recent history of AMD and how the company achieved its tremendous growth in recent years. Further, Intel talks about where they see the biggest challenges with AMD's new products, and what the company's "secret sauce" is to fight against these improvements.The full article follows:

Apparently, AMD isn't celebrating its 50th anniversary in all parts of the globe, judging from recent reports regarding its AMD Radeon RX 5700 XT 50th Anniversary Edition. Apparently, the exclusive, limited-edition graphics card will only be available for US and China customers - two of the biggest worldwide markets, for sure. This is a strange decision from AMD, since a sold unit is a sold unit; however, this may be a sign of really limited availability of the graphics card and the hardware powering it.

AMD CEO Dr. Lisa Su at her 2019 Computex keynote address announced the 3rd generation Ryzen desktop processor family, which leverages the company's Zen 2 microarchitecture, and are built on the 7 nm silicon fabrication process at TSMC. Designed for the AM4 CPU socket, with backwards compatibility for older AMD 300-series and 400-series chipset motherboards, these processors are multi-chip modules of up to two 8-core "Zen 2" CPU chiplets, and a 14 nm I/O controller die that packs the dual-channel DDR4 memory controller and PCI-Express gen 4.0 root complex, along with some SoC connectivity. AMD claims an IPC increase of 15 percent over Zen 1, and higher clock speeds leveraging 7 nm, which add up to significantly higher performance over the current generation. AMD bolstered the core's FPU (floating-point unit), and doubled the cache sizes.

AMD unveiled three high-end SKUs for now, the $329 Ryzen 7 3700X, the $399 Ryzen 7 3800X, and the $499 Ryzen 9 3900X. The 3700X and 3800X are 8-core/16-thread parts with a single CPU chiplet. The 3700X is clocked at 3.60 GHz with 4.40 GHz maximum boost frequency, just 65 Watts TDP and will be beat Intel's Core i7-9700K both at gaming and productivity. The 3800X tops that with 3.90 GHz nominal, 4.50 GHz boost, 105W TDP, and beat the Core i9-9900K at gaming and productivity. AMD went a step further at launched the new Ryzen 9 brand with the 3900X, which is a 12-core/24-thread processor clocked at 3.80 GHz, which 4.60 boost, 72 MB of total cache, 105W TDP, and performance that not only beats the i9-9900K, but also the i9-9920X 12-core/24-thread HEDT processor despite two fewer memory channels. AMD focused on gaming performance with Zen 2, with wider FPU, improved branch prediction, and several micro-architectural improvements contributing to a per-core performance that's higher than Intel's. The processors go on sale on 7/7/2019.

During AMD's annual shareholder meeting today, AMD president and CEO Dr. Lisa Su confirmed the launch of next-generation AMD Ryzen, EPYC CPUs and Navi GPUs for the third quarter of this year. The expected products are going to be manufactured on TSMC's 7 nm process and will be using new and improved architectures.

Ryzen 3000 series CPUs are rumored to have up to as much as 16 cores in Ryzen 9 SKUs, 12 cores in Ryzen 7 SKUs and 8 cores in Ryzen 5 SKUs. EPYC server CPUs will be available in models up to 64 cores. All of the new CPUs will be using AMD "Zen 2" architecture that will offer better IPC performance and, as rumors suggest for consumer models, are OC beasts. Navi GPUs are the new 7 nm GPUs that are expected to be very competitive both price and performance wise to NVIDIA's Turing series, hopefully integrating new technologies such as dedicated Ray Tracing cores for higher frame rates in Ray Tracing enabled games. No next generation ThreadRipper launch date was mentioned, so we don't yet know when and if that will that land.

Intel's semiconductor manufacturing business has had a terrible past 5 years as it struggled to execute its 10 nanometer roadmap forcing the company's processor designers to re-hash the "Skylake" microarchitecture for 5 generations of Core processors, including the upcoming "Comet Lake." Its truly next-generation microarchitecture, codenamed "Ice Lake," which features a new CPU core design called "Sunny Cove," comes out toward the end of 2019, with desktop rollouts expected 2020. It turns out that the 10 nm process it's designed for, will have a rather short reign at Intel's fabs. Speaking at an investor's summit on Wednesday, Intel put out its silicon fabrication roadmap that sees an accelerated roll-out of Intel's own 7 nm process.

When it goes live and fit for mass production some time in 2021, Intel's 7 nm process will be a staggering 3 years behind TSMC, which fired up its 7 nm node in 2018. AMD is already mass-producing CPUs and GPUs on this node. Unlike TSMC, Intel will implement EUV (extreme ultraviolet) lithography straightaway. TSMC began 7 nm with DUV (deep ultraviolet) in 2018, and its EUV node went live in March. Samsung's 7 nm EUV node went up last October. Intel's roadmap doesn't show a leap from its current 10 nm node to 7 nm EUV, though. Intel will refine the 10 nm node to squeeze out energy-efficiency, with a refreshed 10 nm+ node that goes live some time in 2020.

We've all taken a look at AMD's March 2019 product roadmap, which showed us the upcoming 2019 tech the company would be bringing to the table in its "non-stop product momentum". However, it seems that this non-stop product momentum might be coming to an unexpected twist of fate that might delay it from entering the last station - the Zen 2-based Threadripper. In the company's latest May earnings call roadmap, the company silently removed the Zen 2 Threadripper from its product roadmap - where it used to sit right after the launch of Zen 2-based Ryzen products for consumers, is now just a big crop of the space it occupied.

This might mean many things, and a mistake on someone's part while cropping the PowerPoint slide could be the only thing going on here. However, the best and most plausible speculation that can be entertained when one considers this is simple - a supply problem. With the 7 nm node being the newest, most dense fabrication process possible, and with AMD having to share TSMC's 7 nm wafer production with a number of high profile companies - such as Qualcomm, for instance - may mean that supply is simply too tight to support Zen 2-based products across so many product stacks - Ryzen and Epyc - at the same time.

TSMC in its quarterly earnings call expressed confidence in that most of its 7 nm (N7) process production node customers would be looking to make the transition to their 6 nm (N6) process. In fact, the company expects that node to become the biggest target for volume ordering (and thus production) amongst its customers, since the new N6 fabrication technology will bring about a sort of "backwards compatibility" with design tools and semiconductor designs that manufacturers have already invested in for its N7 node, thus allowing for cost savings for its clients.

This is despite TSMC's N6 process being able to take advantage of extreme ultraviolet lithography (EUVL) to lower manufacturing complexity. This lowering is achieved by the fact that less exposures of the silicon are required for multi-patterning - which is needed today as TSMC's N7 uses solely deep ultraviolet (DUV) lithography. Interestingly, TSMC expects other clients to pick up its N7+ manufacturing node that aren't already using their 7nm node - the need to develop new tools and lesser design compatibility between its N7 and N7+ nodes compared no N7 and N6 being the justification. TSMC's N7+ will be the first node to leverage EUV, using up to four EUVL layers, while N6 expands it up to five layers, and the upcoming N5 cranks EUVL up to fourteen (allowing for 14 layers.)

TSMC today announced its 6-nanometer (N6) process, which provides a significant enhancement of its industry-leading N7 technology and offers customers a highly competitive performance-to-cost advantage as well as fast time-to-market with direct migration from N7-based designs. By leveraging the new capabilities in extreme ultraviolet (EUV) lithography gained from the N7+ technology currently in risk production, TSMC's N6 process delivers 18% higher logic density over the N7 process. At the same time, its design rules are fully compatible with TSMC's proven N7 technology, allowing its comprehensive design ecosystem to be reused. As a result, it offers a seamless migration path with a fast design cycle time with very limited engineering resources for customers to achieve the product benefits from the new technology offering.

Scheduled for risk production in the first quarter of 2020, TSMC's N6 technology provides customers with additional cost-effective benefits while extending the industry-leading power and performance from the 7nm family for a broad array of applications, ranging from high-to-mid end mobile, consumer applications, AI, networking, 5G infrastructure, GPU, and high-performance computing.

AMD "Zen 3" microarchitecture could be designed for the enhanced 7 nm+ EUV (extreme ultraviolet) silicon fabrication node at TSMC, which promises a significant 20 percent increase in transistor densities compared to the 7 nm DUV (deep ultraviolet) node on which its "Zen 2" processors are being built. In addition, the node will also reduce power consumption by up to 10 percent at the same operational load. In a late-2018 interview, CTO Mark Papermaster stated AMD's design goal with "Zen 3" would be to prioritize energy-efficiency, and that it would present "modest" performance improvements (read: IPC improvements) over "Zen 2." AMD made it clear that it won't drag 7 nm DUV over more than one microarchitecture (Zen 2), and that "Zen 3" will debut in 2020 on 7 nm+ EUV.

TSMC announced they've completed the infrastructure design for the 5 nm process, which is the next step in silicon evolution when it comes to density and performance. TSMC's 5 nm process will leverage the company's second implementation of EUV (Extreme Ultra Violet) technology (after it's integrated in their 7 nm process first), allowing for improved yields and performance benefits.

According to TSMC, the 5 nm process will enable up to 1.8x the logic density of their 7 nm process, a 15% clock speed gain due to process improvements alone on an example Arm Cortex-A72 core, as well as SRAM and analog circuit area reduction, which means higher number of chips per wafer. The process is being geared for mobile, internet, and high performance computing applications. TSMC also provides online tools for silicon design flow scenarios that are optimized for their 5 nm process. Risk production is already ongoing.

AMD will launch its 3rd generation Ryzen 3000 Socket AM4 desktop processors in 2019, with a product unveiling expected mid-year, likely on the sidelines of Computex 2019. AMD is keeping its promise of making these chips backwards compatible with existing Socket AM4 motherboards. To that effect, motherboard vendors such as ASUS and MSI began rolling out BIOS updates with AGESA-Combo 0.0.7.x microcode, which adds initial support for the platform to run and validate engineering samples of the upcoming "Zen 2" chips.

At CES 2019, AMD unveiled more technical details and a prototype of a 3rd generation Ryzen socket AM4 processor. The company confirmed that it will implement a multi-chip module (MCM) design even for their mainstream-desktop processor, in which it will use one or two 7 nm "Zen 2" CPU core chiplets, which talk to a 14 nm I/O controller die over Infinity Fabric. The two biggest components of the IO die are the PCI-Express root complex, and the all-important dual-channel DDR4 memory controller. We bring you never before reported details of this memory controller.

GlobalFoundries is looking to be sold lock-stock-and-barrel by its investors, after heavily downsizing and parting with some of its Singapore-based assets recently. Once promising to lead the market with 7 nm and 5 nm advancements, the company crashed out of the sub-10 nm race, making AMD, its biggest customer, look for 7 nm supplies from TSMC. GlobalFoundries is the world's third largest semiconductor foundry service provider, with an 8.4 percent market share, behind TSMC and Samsung. Intel doesn't offer manufacturing services, as its fabs are fully dedicated to manufacturing its own products.

GlobalFoundries's main investor is Abu Dhabi-based Mubadala Technology, which holds a 90 percent stake in the company. Korean semiconductor companies Samsung and SK Hynix are reportedly in the foray to buy out GlobalFoundries, as it would give them a turnkey presence in the US, with its Upstate New York facilities. The company is unlikely to entertain bids from Chinese companies, as CFIUS would likely block the sale. "Global Foundries is unlikely to be bought by a Chinese company such as SMIC in that the U.S. government is keeping China in check in various industries," said an industry insider, adding, "The most potential candidates include South Korean companies such as Samsung Electronics and SK Hynix, and Samsung Electronics can increase its share in the market to 23 percent at once if it takes over Global Foundries."

TSMC has revised its financial outlook following the recent contamination of its 14 B Gigafab, which saw between 10,000 and 30,000 wafers affected. It seems that TSMC has needed to scrap a higher number of wafers than it had initially calculated (no word on where exactly on those 10,000-30,000 spectrum that number is). This has resulted in an expected, lowered first-quarter 2019 revenues by about US$550 million, gross margin by 2.6%, operating margin by 3.2%, and EPS (Earnings Per Share) by NT$0.42, the foundry house said.

TSMC said it expects to deliver these chips in the second quarter, making up for most of the lost revenue - it's not so much of a loss, but more of a delay in earnings. As it comes to the actual, final impact of the event on TSMC's operating profits, the company estimates a reduced gross margin by 0.2%, operating margin by 0.2%, and EPS by NT$0.08. TSMC said that it has been in constant conversation with customers, and has already scheduled replacement deliveries - surprising absolutely no one.

TSMC is giving final touches to set its flagship 7 nanometer EUV (extreme ultraviolet lithography) silicon fabrication node at its highest state of readiness for business, called mass-production. At this state, the node can mass-produce products for TSMC's customers. TSMC had taped out its first 7 nm EUV chips in October 2018. The company will also begin risk-production of the more advanced 5 nm node in April, staying on schedule. Mass production of 5 nm chips could commence in the first half of 2020.

The 7 nm EUV node augments TSMC's 7 nm DUV (deep ultraviolet lithography) node that's been already active since April 2018, and producing chips for AMD, Apple, HiSilicon, and Xilinx. At the turn of the year, 7 nm DUV made up 9 percent of TSMC's shipments. With the new node going online, 7 nm (DUV + EUV) could make up 25 percent of TSMC's output by the end of 2019.

AMD "Navi" is the company's next-generation graphics architecture succeeding "Vega" and will leverage the 7 nm silicon fabrication process. It was originally slated to launch mid-2019, with probable unveiling on the sidelines of Computex (early-June). Cowcotland reports that AMD has delayed its plans to launch "Navi" all the way to October (Q4-2019). The delay probably has something to do with AMD's 7 nm foundry allocation for the year.

AMD is now fully reliant on TSMC to execute its 7 nm product roadmap, which includes its entire 2nd generation EPYC and 3rd generation Ryzen processors based on the "Zen 2" architecture, and to a smaller extent, GPUs based on its 2nd generation "Vega" architecture, such as the recently launched Radeon VII. We expect the first "Navi" discrete GPU to be a lean, fast-moving product that succeeds "Polaris 30." In addition to 7 nm, it could incorporate faster SIMD units, higher clock-speeds, and a relatively cost-effective memory solution, such as GDDR6.

AMD in its Q4-2018 Earnings Report disclosed that it has amended its Wafer Supply Agreement (WSA) with GlobalFoundries that frees it from paying a "7 nanometer tax." Under the older version of WSA, AMD would have had to pay a penalty to GlobalFoundries if it sourced processors from any other semiconductor foundry. The company got preferential pricing in return for the exclusivity. With GlobalFoundries discontinuing development of cutting-edge processes such as 7 nm and 5 nm, it makes sense for AMD to seek out other foundry partners, such as TSMC, and an amendment to the WSA was needed. With this amendment in place, AMD can go ahead and source 7 nm dies from TSMC without paying penalties to GlobalFoundries (GloFo).

With its "Zen 2" microarchitecture, AMD is going big on multi-chip modules, in which only those components that can tangibly benefit from the switch to the 7 nm node, namely the CPU cores, would be built on 7 nm dies, called "CPU chiplets," while components that don't need the miniaturization just yet, such as the processor's memory controller, PCIe root-complex, etc., will be built on separate dies called "I/O controllers." These dies will continue to be 14 nm, and likely supplied by GloFo. Final packaging of 7 nm CPU chiplets from TSMC, and 14 nm I/O controllers from GloFo, will happen at GloFo's facilities in China or Malaysia. AMD in its amendment committed to purchasing 14 nm and 12 nm chips from GloFo between 2019 and 2021, which means the MCM approach to processors is here to stay.

TSMC's Fab 14 B has been affected with a chemical contamination that has put a considerable number of wafers in suspend mode. Fab 14 B essentially produces 12 and 16 nm, 300 mm wafers for 14 companies, including NVIDIA, MEDIATEK, Huawei and Hisilicon. Reportedly, between 10,000 and 30,000 wafers have been affected (though not scrapped, so there might be salvageable bits and pieces here and there). Of course, every wafer will have to go through a thorough certification process, and the fab will have to go down for the company to purge any remains of these botched chemical compounds.

To put things into perspective, though, Fab 14 B is one of TSMC's Gigafabs, which have a rated monthly output of 100k wafers - so production worth between three and ten days could be affected already, with the additional downtime accruing lost potential fabrication. This event isn't expected to significantly affect availability of any of the products for any of the companies, but these are becoming, at the very least, late inventory - this could well play into some speculative increases in pricing from some players in the market.

TSMC's introduction of its 7 nm fabrication technology has essentially propelled the company to silicon manufacturing heights. Every company - particularly in the mobile space - is after the most minute increase in transistor density and power consumption improvements the latest and greatest can bring. AMD themselves have become a major TSMC partner in pursuit of its newfound competitiveness against Intel, and has apparently leveraged the 7 nm process as a way to keep its high-performance GPU offering minimally competitive with NVIDIA's solution - at a much lesser die area requirement, if the Radeon VII vs RTX 2080 estimates are something to go by.

As a consequence of the market interest for the 7 nm process, it has rapidly become TSMC's biggest revenue generator as soon as 4Q18. The company said that 7 nm already generated 10% of the company's entire 2018 revenue, despite the process only having been ramped up in June of the same year. Other less dense technologies still generate a lot of revenue for the company, and are likely much higher volume. However, TSMC is most likely riding on much increased ASP for 7 nm wafers than for other technologies.

A report via Tom's Hardware.de says that AMD's plans for the upcoming Radeon VII are somewhat one-dimensional, in that only reference designs will be available for this particular rendition of the Vega architecture. And this doesn't mean"initial availability" only on reference cards, like NVIDIA has been doing with their Founder's editions; the report claims that at no point in time will there actually be a custom-designed Radeon VII. The quantity of Radeon VII GPUs will apparently be "strictly limited" come launch - a likely result of the decision to make use of TSMC's 7 nm process, which will have to serve not only AMD's Ryzen 3000 and Epyc CPUs when those are actually launched, but all of TSMC's other clients.

This is in contrast with AMD CEO Lisa Su's words during her CES keynote, who said that Radeon VII would be available from "several leading add-in board partners plan to offer the cards". According to a Tom's Hardware.de Taiwanese source, "You cannot leak anything that does not exist" in regards to third-party designs. And another Chinese source said "the quantity of Radeon VII is strictly limited… not sure if AMD wants to open AIB to have an own design later".

AMD pulled off a surprise at its CES 2019 keynote address, with the announcement of the Radeon VII client-segment graphics card targeted at gamers. We went hands-on with the card earlier this week. The company revealed a few more technical details of the card in its press-deck for the card. To begin with, the company talks about the immediate dividends of switching from 14 nm to 7 nm, with a reduction in die-size from 495 mm² on the "Vega 10" silicon to 331 mm² on the new "Vega 20" silicon. The company has reworked the die to feature a 4096-bit wide HBM2 memory interface, the "Vega 20" MCM now features four 32 Gbit HBM2 memory stacks, which make up the card's 16 GB of memory. The memory clock has been dialed up to 1000 MHz from 945 MHz on the RX Vega 64, which when coupled with the doubled bus-width, works out to a phenomenal 1 TB/s memory bandwidth.

We know from AMD's late-2018 announcement of the Radeon Instinct MI60 machine-learning accelerator based on the same silicon that "Vega 20" features a total of 64 NGCUs (next-generation compute units). To carve out the Radeon VII, AMD disabled 4 of these, resulting in an NGCU count of 60, which is halfway between the RX Vega 56 and RX Vega 64, resulting in a stream-processor count of 3,840. The reduced NGCU count could help AMD harvest the TSMC-built 7 nm GPU die better. AMD is attempting to make up the vast 44 percent performance gap between the RX Vega 64 and the GeForce RTX 2080 with a combination of factors.

NVIDIA will implement the 7 nanometer EUV (extreme ultraviolet) lithography to build its future generation of GPUs slated for 2020, according to Japanese publication MyNavi.jp. The GPU giant could be among the first customers besides IBM, to contract Samsung for 7 nm EUV mass-production of GPUs. IBM will use the Korean semiconductor giant for manufacturing Z-series processors and FPGAs. Samsung announced in October 2018 that it will begin risk-production on its 7 nm EUV node in early-2019.

An earlier report from 2018 also forecast NVIDIA implementing 7 nm DUV (deep ultraviolet) node of TSMC for its 2019 GPU lineup. With news of the company now working with Samsung on 7 nm EUV for 2020, this seems less likely. It's possible that NVIDIA could somehow split its next generation GPU lineup between TSMC 7 nm DUV and Samsung 7 nm EUV, with the latter being used for chips with higher transistor-counts, taking advantage of the node's higher deliverable transistor densities.

The world's largest contract semiconductor manufacturing company, TSMC, has been cleared to commence construction of a new 3 nm chip factory at the Southern Taiwan Science Park in Tainan. The new factory is expected to use 20 percent renewable energy and 50 percent recycled water.

The factory's environmental impact assessment was accepted by the Environmental Protection Administration (EPA) on Dec. 19, after concerns were raised about use of water and power sources. TSMC is expected to invest NT$600 million (US$19.45 million) in the project, with construction to begin in 2022. Production is planned to start in late 2022 or early 2023. At the same site, TSMC is also building a 5 nm chip factory, which is expected to be up and running in late 2019 or early 2020.

DigiTimes, citing a Chinese-language Commercial Times report, cites TSMC's 7 nm foundry capacity as likely being underutilized in 2019. After TSMC announced it expected cutting-edge 7 nm designs to correspond to around 20% of the company's revenues in 2019, the company will likely have to review those projections, as lower demand from smartphone chip manufacturers will likely leave TSMC with less actual output than that which it can churn out.

Due to a cutback in orders placed by Apple, HiSilicon and Qualcomm, concerns regarding TSMC's ability to be the sole 7 nm chip fabrication tech for the industry can likely be laid to rest. That the smartphone market is reaching saturation is a well-known quantity - it's becoming harder and harder to cram new technologies that justify the yearly smartphone upgrade that most companies vie for - and one of the reasons for the launch of various brand-specific smartphone subscription services. The difference isn't scandalous - TSMC will still be making use of 80-90% of its total 7nm process capacity during the first half of 2019, the report quoted industry sources as saying.