TSMC, Taiwan's flagship manufacturer of silicon, has seen a substantial increase in demand for Chip-on-Wafer-on-Substrate (CoWoS) packaging technology, according to the report from DigiTimes. CoWoS is a multi-chip packaging technology that gives an option to build silicon like LEGO, allowing for dies to be placed side by side on interposer that is providing high interconnect density and performance. You can see more about CoWoS in detail here. Some of the examples of CoWoS are NVIDIA's P100 and V100 dies that integrate logic (computing elements), and memory (in the form of HBM) on a single die.

Recently, TSMC updated its CoWoS technology, where this new second-generation parts could scale far larger than the first-generation implementation - up to 1700 squared millimeters of die space, allowing for some very creative solutions to be implemented. This may be the reason that the demand in Q2 has risen so substantially and that TSMC's production lines are now running at full capacity, trying to meet the demand for this packaging technology.

AMD's 4th generation Ryzen desktop processors are expected to launch around September 2020, sources in the motherboard industry tell DigiTimes. Codenamed "Vermeer," successor to "Matisse," these processors will be socket AM4 multi-chip modules of up to two CPU complex dies based on the "Zen 3" microarchitecture, combined with an I/O controller die. The "Zen 3" chiplets are expected to be fabricated on a newer 7 nm-class process by TSMC, either N7P or N7+. The biggest design change with "Zen 3" is the doing away of CCX arrangement of CPU cores, with each chiplet holding a common block of cores sharing a last-level cache. This, along with clock speed headroom gains from the new node are expected to yield generational price-performance increases.

The "Zen 2" based 8-core "Renoir" die is also expected to make its socket AM4 debut within 2020, succeeding the "Picasso" based quad-core Ryzen 3000-series APUs. This is a particularly important product for AMD, as it is expected to compete with Intel's 10th generation Core i5 6-core/12-thread processors in terms of pricing, while offering more cores (8-core/16-thread) and a faster iGPU. The 4th gen Ryzen socket AM4 processor lineup will launch alongside AMD's 600-series motherboard chipset, with forwards- and backwards-compatibility (i.e., "Vermeer" and "Renoir" working with older chipsets, and older AM4 processors working on 600-series chipset motherboards). AMD was originally expected to unveil these processors at the 2020 Computex trade-show in June, but Computex itself is rescheduled to late-September.

China's state-backed SMIC (Semiconductor Manufacturing International Corporation) has set an ambitious target of Q4-2020 for its 7 nanometer-class N+1 foundry node to go live, achieving "small scale production," according to a cnTechPost report. The company has a lot of weight on its shoulders as geopolitical hostility between the U.S. and China threatens to derail the country's plans to dominate 5G technology markets around the world. The SMIC N+1 node is designed to improve performance by 20%, reduce chip power consumption by 57%, reduce logic area by 63%, and reduce SoC area by 55%, in comparison to the SMIC's 14 nm FinFET node, Chinese press reports citing a statement from SMIC's co-CEO Dr. Liang Mengsong.

Dr. Liang confirmed that the N+1 7 nm node and its immediate successor will not use EUV lithography. N+1 will receive a refinement in the form of N+2, with modest chip power consumption improvement goals compared to N+1. This is similar to SMIC's 12 nm FinFET node being a refinement of its 14 nm FinFET node. Later down its lifecycle, once the company has got a handle of its EUV lithography equipment, N+2 could receive various photomasks, including a switch to EUV at scale.

The U.S. government announced advanced measures that make it harder for foreign companies, such as Taiwan's TSMC, to supply chips to Chinese telecom hardware giant Huawei. Foreign companies that use American chipmaking equipment, are required to obtain a license from the U.S. before supplying certain chips to Huawei. Sources comment that the new rule was tailor-made to curb TSMC fabricating smartphone SoCs for Huawei's HiSilicon subsidiary.

Mainland Chinese semiconductor companies are still behind Samsung and TSMC in 7 nm-class fab technologies, forcing HiSilicon to source from the latter. 7 nm fabrication is a key requirement for SoCs and modem chips capable of 5G. The high data transceiving rates of 5G requires a certain amount of compute power that can fit into smartphone-level power-envelopes only with the help of 7 nm, at least for premium smartphone form-factors. Same applies to 5G infrastructure equipment. This is hence perceived as a means for the U.S. to clamp brakes on Huawei's plans of playing a big role in 5G tech rollouts around the world, buying western 5G tech suppliers such as Nokia time to catch up. Huawei has been a flashpoint for a bitter political spat between the U.S. and China, with the Chinese press even threatening that the matter could hamper medical supplies to the U.S. to fight the COVID-19 pandemic.

A WikiChip analysis of TSMC's next-generation 5 nanometer N5P silicon fabrication node estimates a massive 84-87% increase in transistor densities on offer compared to the company's first commercial 7 nm-class node, the N7 (7 nm DUV). The report estimates an 87% transistor-density increase, even though TSMC's own figure is slightly modest, at 84%. TSMC N5P node is expected to commence production later this year. Its precursor, TSMC N5, began risk production earlier this year, with production on the node commencing in April or May, unless derailed by the COVID-19 pandemic. The N5P node provides transistor densities of an estimated 171.3 million transistors per mm² die area, compared to 91.2 mTr/mm² of N7. Apple is expected to be the node's biggest customer in 2020, with the company building its A14-series SoC on it.

TSMC will be doing good on their previous expectations for a H2 2020 ramp-up for high volume production (HVM) on their 5 nm manufacturing process. The new 5 nm fabrication process is an Extreme Ultraviolet lithography (EUV) one, with up to 14 layers being etchable onto the silicon wafers, as opposed to five and six, respectively, for TSMC's N7+ and N6 processes.

Volume production will start with Apple's A14 SoC, meant to be driving next-generation iPhones that should hit shelves by September this year (should the COVID-19 pandemic let it be so). Apple is using two thirds of TSMC's capacity for 5 nm as is with this SoC; it's currently unclear which client (or clients) are getting the leftover one third capacity. TSMC announced back in December that they were seeing yields upwards of 80% in 5 nm EUV fabrication, so now it's "just" a matter of monetizing the process until their 3 nm iteration comes online, expectedly, in 2022.

Xilinx, Inc. today announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry's highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the industry's first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.

Intel is rumored to be aligning its future-generation Xe GPU development with TSMC's node development cycle, with the company reportedly negotiating with the Taiwanese foundry for 6 nm and 3 nm allocation for its large Xe GPUs. Intel's first Xe discrete GPUs for the market, however, are reportedly built on the company's own 10 nm+ silicon fabrication process.

While Intel's fascination with TSMC 3 nm is understandable, seeking out TSMC's 6 nm node raises eyebrows. Internally referred to as "N6," the 6 nm silicon fabrication node at TSMC is expected to go live either towards the end of 2020 or early 2021, which is when Intel's 10 nm+ node is expected to pick up volume production, beginning with the company's "Tiger Lake" processors. Perhaps a decision has been made internally to ensure that Xe doesn't eat too much into Intel's own foundry capacities meant for processor manufacturing, and to instead outsource Xe manufacturing to third-party foundries like TSMC and Samsung eventually. Way back in April 2019 it was rumored that Intel was evaluating Samsung as a foundry partner for Xe.

AMD at its Financial Analyst Day 2020 presentation made a major clarification about its silicon fabrication process. It was previously believed that the company's upcoming "Zen 3" CPU microarchitecture and RDNA2 graphics architectures were based on TSMC's N7+ (7 nm EUV) silicon fabrication process because AMD would mark the two as "7 nm+" in its marketing slides. Throughout its Financial Analyst Day presentation, however, AMD avoided using that marker, and resorted to an amorphous "7 nm" marker, prompting one of the financial analysts to seek a clarification. At the time, AMD responded that they were aligning their marketing with that of TSMC, and hence chose to use "7 nm" in its new slides.

It turns out that the next step to TSMC N7, the company's current-generation 7 nm DUV silicon fabrication node, isn't N7+ (7 nm EUV), but rather it has a nodelet along the way, which the foundry refers to as N7P. This is a generational refinement of N7, but does not use EUV lithography, which means it may not offer the 15-20 percent gains in transistor densities offered by N7+ over N7. AMD clarified that "7 nm+" in its past presentations did not intend to signify N7+, and that the "+" merely denoted an improvement over N7. At the same time, it won't specify whether "Zen 3" and RDNA2 are based on N7P or N7+, so the company doesn't rule out N7+, either. We'll probably learn more as we near the late-2020 launch of "Zen 3" as EPYC "Milan."

AMD Financial Analyst Day presents an opportunity for AMD to talk straight with the finance industry about the company's current financial health, and a taste of what's to come. Guidance and product teasers made during this time are usually very accurate due to the nature of the audience. In this live blog, we will post information from the Financial Analyst Day 2020 as it unfolds.20:59 UTC: The event has started as of 1 PM PST. CEO Dr Lisa Su takes stage.

Ampere Computing, a startup focusing on making HPC and processors from cloud applications based on Arm Instruction Set Architecture, today announced the release of a first 80 core "cloud-native" processor based on the Arm ISA. The new Ampere Altra CPU is the company's first 80 core CPU meant for hyper scalers like Amazon AWS, Microsoft Azure, and Google Cloud. Being built on TSMC's 7 nm semiconductor manufacturing process, the Altra is a CPU that is utilizing a monolithic die to achieve maximum performance. Using Arm's v8.2+ instruction set, the CPU is using the Neoverse N1 platform as its core, to be ready for any data center workload needed. It also borrows a few security features from v8.3 and v8.5, namely the hardware mitigations of speculative attacks.

When it comes to the core itself, the CPU is running at 3.0 GHz frequency and has some very interesting specifications. The design of the core is such that it is 4-wide superscalar Out of Order Execution (OoOE), which Ampere refers to as "aggressive" meaning that there is a lot of data throughput going on. The cache levels are structured in a way that there is 64 KB of L1D and L1I cache per core, along with 1 MB of L2 cache per core as well. For system-level cache, there is 32 MB of L3 available to the SoC. All of the caches have Error-correcting code (ECC) built-in, giving the CPU a much-needed feature. There are two 128-bit wide Single Instruction Multiple Data (SIMD) units, which are there to do parallel processing if needed. There is no mention if they implement Arm's Scalable Vector Extensions (SVE) or not.

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.

TSMC is set to hire about 4000 new staff members to gain a workforce for its development of next-generation semiconductor manufacturing nodes. The goal of the company is to gather talent so it can develop the world's leading semiconductor nodes, like 3 nm and below. With 15 billion USD planned for R&D purposes alone this year, TSMC is investing a big part of its capital back into development on new and improved technology. Markets such as 5G and High-Performance Computing are leading the charge and require smaller, faster, and more efficient semiconductor nodes, which TSMC plans to deliver. To gather talent, TSMC started job listing using recruitment website TaiwanJobs and started campaigns on university campuses to attract grad students.

Apple is currently designing a custom series of CPUs, for its Macbook laptop lineup, based on the Arm Instruction Set Architecture. Having designed some of the most powerful mobile processors that are inside the iPhone series of devices, Apple is preparing to make a jump to an even more powerful device lineup by bringing custom CPUs for MacBook. Tired of the speed by which Intel replaces and upgrades its Core lineup of CPUs, Apple decided to take the matter in its own hands and rumors about the switch to a custom solution have been going on for a while. However, we now have some information about when to expect the first wave of Arm-powered Macs.

According to the analyst Ming-Chi Kuo, who is a well-known insider in the Apple industry, we can expect the first wave of the Arm-powered Macbook in the next 18 months, precisely in the first half of 2021. Supposedly, the first chips for these new Macs are going to be manufactured on a 5 nm manufacturing process, possibly over at TSMC since Apple had a long-lasting history of manufacturing its chips at TSMC foundries. In the meantime, we can expect to see Apple providing developers with tools to transition their x86-64 software to the new Arm ISA. Without a software ecosystem, the hardware platform is essentially worthless. And Apple knows this. We will see how they plan to play it and will report as soon as there is more information.

With a 2.4-liter volume, a conventional black plastic body, and essential connectivity, the Ruijie RG-CT7800 may come across as a run-of-the-mill mini-PCs for small businesses or those who do precious little offline, except what's under the hood. This humble compact desktop is among the first design wins of China's ambitious effort at having an x86 processor built entirely on Chinese soil, the Zhaoxin KaiXian. This processor is making its way to products, and was recently pictured on an embedded motherboard. The KaiXian, along with the notebooks, motherboards, micro-servers, and mini-PCs that implement it, form the tip of China's 3-5-2 policy, an ambitious plan to rid all state- and state-owned institutions of "foreign hardware."

The numerals in "3-5-2" are supposed to correspond to foreign hardware replacement targets set by the country's Central Government - 30% by the end of 2020, an additional 50% by the end of 2021, and the remaining 20% by the end of 2022. To support this plan, the Chinese electronics industry, flush with state investment, has indigenized several key components of the modern PC, including DRAM, NAND flash, and now CPU. The country already dominates the global electronic components market. The RG-CT7800 implements The KaiXian KX-U6780A SoC that sports eight x64 CPU cores running at 2.70 GHz. Interestingly, the chip is manufactured on TSMC's 16 nm FinFET node (a de facto "foreign" source, but one that's de jure China from Beijing's perspective). Ruijie is equipping the RG-CT7800 with 8 GB of DDR4 memory, and 256 GB of SSD-based storage. One can make out industry-standard USB, Ethernet, 3.5 mm audio jacks, etc., from the pictures. The box will be compatible with UOS and NeoKylin (Linux distros built under scrutiny of the Chinese Government). With state institutions being on the clock to implement their 3-5-2 targets, it's possible that the first volumes of RG-CT7800 will be sold exclusively to state customers.

US Government, precisely the Trump administration, is considering placing a ban on chip export from TSMC to Huawei. With Huawei being in the middle between the US and China fight for global technology dominance, the Trump administration is seeking to limit the progress of foreign forces trying to match or beat US technology. There were previous efforts by the US government to influence Huawei's fate, with them claiming that Huawei 5G equipment is capable of supplying China with intelligence, meaning that China tries to spy on US citizens. While those claims were later disregarded by Huawei, the Trump administration managed to do some damage to the face of the company.

The TSMC representative who spoke to Reuters about the potential ban said that the company (TSMC) does not answer hypothetical questions and that they don't talk about their customers. To achieve more control over the China semiconductor manufacturing, the US government plans to place a licensing model on all of their US-made semiconductor equipment, meaning that all the production lines are possibly in danger if the US doesn't approve shipments of their machines to other countries.

VIA's CenTaur division sprung an unexpected surprise in the CPU industry with its new CHA x86-64 microarchitecture and an on-die NCORE AI co-processor. This would be the first globally-targeted x86 processor launch by a company other than Intel and AMD in close to 7 years, and VIA's first socketed processor in over 15 years. SemiAccurate scored a look at mock-up of the CenTaur CHA NCORE 8-core processor and it turns out that the chip is indeed socketed.

Pictured below, the processor is a flip-chip LGA. We deduce it is socketed looking at its alignment notches and traces for ancillaries on the reverse-side (something BGAs tend to lack). On the other hand, the "contact points" of the package appear to cast shadows, and resemble balls on a BGA package. Topside, we see an integrated heatspreader (IHS), and underneath is a single square die. CenTaur built the CHA NCORE on TSMC's 16 nm FinFET process. The package appears to have quite a high pin-count for a die this size, but that's probably because of its HEDT-rivaling I/O, which includes a quad-channel DDR4 memory interface and 44 PCI-Express gen 3.0 lanes.

TSMC is working hard to ensure its number one spot in the semiconductor manufacturing industry, and it has the funds to back it up. Yesterday TSMC's Board of Directors approved the company budget for another semiconductor fab expansion. With a budget totaling 6.74 billion US dollars allocated, TSMC has "Approved capital appropriations of approximately US$6,742.1 million (approximately NT$200.9 billion) for purposes including: 1) Fab construction, and installation of fab facility systems; 2) Installation and upgrade of advanced technology capacity; 3) Installation of specialty technology capacity; 4) Installation of advanced packaging capacity; 5) Second quarter 2020 R&D capital investments and sustaining capital expenditures."

Zhaoxin is a brand that makes multi-core 64-bit x86 processors primarily for use in Chinese state IT infrastructure. It's part of the Chinese Government's ambitious plan to make its IT hardware completely indigenous. Zhaoxin's x86-64 CPU cores are co-developed by licensee VIA, specifically its CenTaur subsidiary that's making NCORE AI-enabled x86 processors. The company's KaiXian KX-6780A processor is now commercially available in China to the DIY market in the form of motherboards with embedded processors.

The KaiXian KX-6780A features an 8-core/8-thread x86-64 CPU clocked up to 2.70 GHz, 8 MB of last-level cache, a dual-channel DDR4-3200 integrated memory controller, a PCI-Express gen 3.0 root-complex, and an iGPU possibly designed by VIA's S3 Graphics division, which supports basic display and DirectX 11.1 readiness. The CPU features modern ISA, with instruction sets that include AVX, AES-NI, SHA-NI, and VT-x comparable virtualization extensions. The chip has been fabricated on TSMC 16 nm FinFET process.

AMD CEO Dr Lisa Su, in her Q4-2019 and FY-2019 earnings call, confirmed that the company debut its second-generation RDNA graphics architecture in 2020. "In 2019 we launched our new architecture in GPUs, it's the RDNA architecture, and that was the Navi-based products. You should expect those will be refreshed in 2020, and we will have our new next-generation RDNA architecture that will be part our 2020 lineup."

Second-gen RDNA, or RDNA2, is expected to leverage the new 7 nm+ (EUV) silicon fabrication process at TSMC, to dial up transistor-counts, clock-speeds, and performance. Among the two anticipated feature additions are VRS (variable rate shading) and possibly ray-tracing. The fabled "big Navi" silicon, a GPU larger than "Navi 10," is also on the cards, according to an earlier statement by Dr Su. More details about these upcoming graphics cards are expected to be put out in March, at the 2020 AMD Investor Day conference.

European Processor Initiative (EPI) is a Europe's project to kickstart a homegrown development of custom processors tailored towards different usage models that the European Union might need. The first task of EPI is to create a custom processor for high-performance computing applications like machine learning, and the chip prototypes are already on their way. The EPI chairman of the board Jean-Marc Denis recently spoke to the Next Platform and confirmed some information regarding the processor design goals and the timeframe of launch.

Supposed to be manufactured on TSMC's 6 nm EUV (TSMC N6 EUV) technology, the EPI processor will tape-out at the end of 2020 or the beginning of 2021, and it is going to be heterogeneous. That means that on its 2.5D die, many different IPs will be present. The processor will use a custom ARM CPU, based on a "Zeus" iteration of Neoverese server core, meant for general-purpose computation tasks like running the OS. When it comes to the special-purpose chips, EPI will incorporate a chip named Titan - a RISC-V based processor that uses vector and tensor processing units to compute AI tasks. The Titan will use every new standard for AI processing, including FP32, FP64, INT8, and bfloat16. The system will use HBM memory allocated to the Titan processor, have DDR5 links for the CPU, and feature PCIe 5.0 for the inner connection.

As we approach the release of NVIDIA's Ampere GPUs, which are rumored to launch in the second half of this year, more rumors and information about the upcoming graphics cards are appearing. Today, according to the latest report made by Taipei Times, NVIDIA's next-generation of graphics cards based on "Ampere" architecture is rumored to have as much as 50% performance uplift compared to the previous generations of Turing GPUs, while using having half the power consumption.

Built using Samsung's 7 nm manufacturing node, Ampere is poised to be the new king among all future GPUs. The rumored 50% performance increase is not impossible, due to features and improvements that the new 7 nm manufacturing node brings. If utilizing the density alone, NVIDIA can extract at least 50% extra performance that is due to the use of a smaller node. However, performance should increase even further because Ampere will bring new architecture as well. Combining a new manufacturing node and new microarchitecture, Ampere will reduce power consumption in half, making for a very efficient GPU solution. We still don't know if the performance will increase mostly for ray tracing applications, or will NVIDIA put the focus on general graphics performance.

AMD in the second half of 2020 could outpace Apple as the biggest foundry customer of TSMC for its 7 nm silicon fabrication nodes (DUV and EUV combined). There are two key factors contributing to this: AMD significantly increasing its orders for the year; and Apple transitioning to TSMC's 5 nm node for its A14 SoC, freeing up some 7 nm allocation, which AMD grabbed. AMD is currently tapping into 7 nm DUV for its "Zen 2" chiplet, "Navi 10," and "Navi 14" GPU dies. The company could continue to order 7 nm DUV until these products reach EOL; while also introducing the new "Renoir" APU die on the process. The foundry's new 7 nm+ (EUV) node will be utilized for "Zen 3" chiplets and "Navi 2#" GPU dies in 2020.

Currently, the top-5 customers for TSMC 7 nm are Apple, HiSilicon, Qualcomm, AMD, and MediaTek. Barring AMD, the others in the top-5 build mobile SoCs or 4G/5G modem chips on the node. AMD is expected to top the list as it scales up orders with TSMC. In the first half of 2020, TSMC's monthly output for 7 nm is expected to grow to 110,000 wafers per month (wpm). Apple's migration to 5 nm in 2H-2020, coupled with capacity-addition could take TSMC's 7 nm output to 140,000 wpm. AMD has reportedly booked the entire capacity-addition for 30,000 wpm, taking its allocation up to 21% in 2H-2020. Qualcomm is switching to Samsung for its next-generation SoCs and modems designed for 7 nm EUV. NVIDIA, too, is expected to built its next-gen 7 nm EUV GPUs on Samsung instead of TSMC. These moves by big players could free up significant foundry allocation at TSMC for AMD's volumes to grow in 2020.

AMD's "Zen 4" CPU microarchitecture is on track for a 2021 launch as its principal foundry partner, TSMC, is optimistic about early yields of its 5 nm silicon fabrication node. TSMC supports the 5 nm product roadmaps of not just AMD, but also Apple and HiSilicon. "Zen 4" is particularly important for AMD, as it will release its next enterprise platform, codenamed "Genoa," along with the new SP5 socket. The new socket will present AMD with the opportunity to significantly change the processor's I/O, such as support for a new memory standard, a new PCIe generation, more memory channels, more PCIe lanes, etc. As early as 2019, the foundry is seeing yields of over 50 percent for the 5 nm node (possibly risk production designed to test the node), which is very encouraging for its customers.

AMD's roadmap for 2020 sees the introduction of "Zen 3" on the 7 nm EUV process (dubbed 7 nm+). AMD recently commented that the performance uplift of "Zen 3" versus "Zen 2" will be "right in line with what you would expect from an entirely new architecture." The 7 nm EUV node provides a significant 20 percent increase in transistor-density compared to the current 7 nm DUV node "Zen 2" chiplets and the company's "Navi" family of GPUs are built on. "Zen 3" could see the company do away with the CCX (quad-core CPU complex), and make chiplets monolithic blocks of CPU cores without sub-divisions. For the client-segment, 5 is a recurring number in 2021. It will see the introduction of the 5th generation Ryzen processors (5000-series), built on the 5 nm process, supporting DDR5 memory, PCI-Express gen 5, and the new AM5 client-segment CPU socket.

TSMC is delivering record results day after day, with a 5 nm manufacturing process starting High Volume Manufacturing (HVM) in Q2 next year, 7 nm process getting plenty of orders and the fact that TSMC just became the biggest company publicly trading in Asia. Continuing with the goal to match or even beat the famous Moore's Law, TSMC is already planning for future 3 nm node manufacturing, promised to start HVM as soon as 2022 arrives, according to JK Wang, TSMC's senior vice president of fab operations. Delivering 3 nm a whole year before originally planned in 2023, TSMC is working hard, with fab construction work doing quite well, judging by all the news that the company is releasing recently.

We can hope to see the first wave of products built using 3 nm manufacturing process sometime around end of year 2022, when the holiday season arrives. Usual customers like Apple and HiSilicon will surely utilize the new node and deliver their smartphones with 3 nm processors inside as soon as the process is ready for HVM.