TSMC has reportedly secured orders from NVIDIA for chips based on its 7 nm and 5 nm silicon fabrication nodes, sources tell DigiTimes. If true, it could confirm rumors of NVIDIA splitting its next-generation GPU manufacturing between TSMC and Samsung. The Korean semiconductor giant is commencing 5 nm EUV mass production within Q2-2020, and NVIDIA is expected to be one of its customers. NVIDIA is expected to shed light on its next-gen graphics architecture at the GTC 2020 online event held later this month. With its "Turing" architecture approaching six quarters of market presence, it's likely that the decks are being cleared for a new architecture not just in HPC/AI compute product segment, but also GeForce and Quadro consumer graphics cards. Splitting manufacturing between TSMC and Samsung would help NVIDIA disperse any yield issue arriving from either foundry's EUV node, and give it greater bargaining power with both.

Silicon Valley startup Tachyum, founded in 2016, is ready with its crowning product, the Tachyum Prodigy. The startup recently received an investment from the Slovak government in hopes of job-creation in the country. The Prodigy is what its makers call "a universal processor," which "outperforms the fastest Xeon at 10X lower power." The company won't mention what machine architecture it uses (whether it's Arm or MIPS, or its own architecture). Its data-sheet is otherwise full of specs that scream at you.

To begin with, its top trim, the Prodigy T16128, packs 128 cores on a single package, complete with 64-bit address space, 512-bit vector extensions, matrix multiplication fixed-function hardware that accelerate AI/ML, and 4 IPC at up to 4.00 GHz core clock. Tachyum began the processor's software-side support, with an FPGA emulator in December 2019 (so you can emulate the processor on an FPGA and begin developing for it), C/C++ and Fortran compilers; debuggers and profilers, tensorflow compilers, and a Linux distribution that's optimized it. The I/O capabilities of this chip are something else.

A report via DigiTimes places TSMC as having announced to its investors that exploratory studies and R&D for the development of the 2 nm process node have commenced. As today's leading semiconductor fabrication company, TSMC doesn't seem to be one resting on its laurels. Their 7 nm process and derivatives have already achieved a 30% weight on the company's semiconductor orders, and their 5 nm node (which will include EUV litography) is set to hit HVM (High Volume Manufacturing) in Q2 of this year. Apart from that, not much more is known on 2 nm.

After 5 nm, which is expected to boats of an 84-87% transistor density gain over the current 7nm node, the plans are to go 3nm, with TSMC expecting that node to hit mass production come 2022. Interestingly, TSMC is planning to still use FinFET technology for its 3 nm manufacturing node, though in a new GAAFET (gate-all-around field-effect transistor) technology. TSMC's plans to deploy FinFET in under 5nm manufacturing is something that many industry analysts and specialist thought extremely difficult to achieve, with expectations for these sub-5nm nodes to require more exotic materials and transistor designs than TSMC's apparent plans

According to the report of DigiTimes, which talked about TSMC's 5 nm silicon manufacturing node, they have reported that NVIDIA is also going to be a customer for it and they could use it in the near future. And that is very interesting information, knowing that these chips will not go in the next generation of GPUs. Why is that? Because we know that NVIDIA will utilize both TSMC and Samsung for their 7 nm manufacturing nodes for its next-generation Ampere GPUs that will end up in designs like GeForce RTX 3070 and RTX 3080 graphics cards. These designs are not what NVIDIA needs 5 nm for.

Being that NVIDIA already has a product in its pipeline that will satisfy the demand for the high-performance graphics market, maybe they are planning something that will end up being a surprise to everyone. No one knows what it is, however, the speculation (which you should take with a huge grain of salt) would be that NVIDIA is updating its Tegra SoC with the latest node. That Tegra SoC could be used in a range of mobile devices, like the Nintendo Switch, so could NVIDIA be preparing a new chip for Nintendo Switch 2?

In a recent report by Bloomberg it was revealed that Apple is planning to start selling Mac computers featuring their upcoming in-house A14 ARM chip which will power the next generation iPhone & iPad in 2021. According to sources familiar with the matter Apple is developing three new processors based on the A14 to power some 2021 Mac products, these chips will be manufactured on TSMCs 5 nm process. One of these new processors is expected to be more powerful then the iPhone version.

This marks a significant move for Apple as they shift from x86 to in-house ARM designs across their entire product lineup, we have an editorial on the rise of ARM here. This development is part of Apple's plan to increase control over their products in an attempt to fully unify the Apple ecosystem and reduce reliance on Intel who has struggled to offer significant performance increases in recent years, this will come as a major blow to Intel who benefited greatly from Apple's demand. Apple will need to adapt MacOS for an ARM based design and ensure their is compatibility for third party x86 applications. The first processor is expected to feature 8 "Firestorm" cores and at least four energy-efficient "Icestorm" cores, Apple is also exploring options for up to 12 core processors based on the same design for use in future Macs.

Imagine being able to shrink a Pentium 4 processor die to the size of a pin-head (if you can figure out how to place 478 bumps on it). TSMC revealed that its future 3 nanometer silicon fabrication node has a development target of 250 million transistors per mm². Called N3, the next-generation silicon fabrication node succeeds TSMC's N5 family of 5 nm-class nodes (that's N5 and any possible refinements).

TSMC CEO CC Wei confirmed that development of the 3 nm node is on-track, with risk production scheduled for 2021 and volume production commencing in the second half of 2022. Perhaps the most startling revelation is that TSMC has decided to stick with FinFETs for N3 owing to the maturity of the technology. Experts are of the opinion that sub-5 nm nodes will require major innovations with materials and structures. TSMC claims that N3 will provide a 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed, compared to N5.

TSMC (TWSE: 2330, NYSE: TSM) today announced consolidated revenue of NT$310.60 billion, net income of NT$116.99 billion, and diluted earnings per share of NT$4.51 (US$0.75 per ADR unit) for the first quarter ended March 31, 2020. Year-over-year, first quarter revenue increased 42.0% while net income and diluted EPS both increased 90.6%. Compared to fourth quarter 2019, first quarter results represented a 2.1% decrease in revenue and a 0.8% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, first quarter revenue was $10.31 billion, which increased 45.2% year-over-year and decreased 0.8% from the previous quarter. Gross margin for the quarter was 51.8%, operating margin was 41.4%, and net profit margin was 37.7%. In the first quarter, shipments of 7-nanometer accounted for 35% of total wafer revenue and 10-nanometer process technology contributed 0.5% while 16-nanometer accounted for 19%. Advanced technologies, defined as 16-nanometer and more advanced technologies, accounted for 55% of total wafer revenue.

With Mainland Chinese tech giant Huawei being effectively cut off from contracting Taiwanese TSMC to manufacture its next-generation HiSilicon 5G mobile SoCs, and NVIDIA switching to Samsung for its next-generation GPUs, TSMC is looking to hold on to large high-volume customers besides Apple and Qualcomm, so as to not let them dictate pricing. AMD is at the receiving end of the newfound affection, with the semiconductor firm reportedly developing a new refinement of its 5 nm node specially for AMD, possibly to make Sunnyvale lock in on TSMC for its future chip architectures. A ChainNews report decoded by @chiakokhua sheds light on this development.

AMD is developing its "Zen 4" CPU microarchitecture for a 5 nm-class silicon fabrication node, although the company doesn't appear to have zeroed in on a node for its RDNA3 graphics architecture and CDNA2 scalar compute architecture. In its recent public reveal of the two, AMD chose not to specify the foundry node for the two, which come out roughly around the same time as "Zen 4." It wouldn't be far fetched to predict that AMD and TSMC were waiting on certainty for the new 5 nm-class node's development. There are no technical details of this new node. AMD's demand for TSMC is expected to be at least 20,000 12-inch wafers per month.

With an introduction of new iPad Pro tablets, Apple has brought another new silicon to its offerings in the form of A12Z SoC. Following the previous king in tablet space, the A12X SoC, Apple has decided to update its silicon and now there is another, more advanced stepping in form of an A12Z SoC. Thanks to the report from TechInsights, their analysis has shown that the new SoC used in Apple's devices is pretty much the same compared to the A12X SoC of last year, except the GPU used. Namely, the configuration of A12X is translated into the A12Z - there are four Apple Vortex and four Apple Tempest cores for the CPU. There is a 128-bit memory bus designed for LPDDR4X memory, the same as the A12X.

What is different, however, is the GPU cluster configuration. In A12X there was a cluster filled with 7 working and one disabled A12-gen GPU core. In A12Z SoC all of the 8 GPUs present are enabled and working, and they are also of the same A12 generation. The new SoC is even built using the same N7 7 nm manufacturing process from TSMC. While we don't know the silicon stepping revision of the A12Z, there aren't any new features besides the additional GPU core.

Huawei's subsidiary, HiSilicon, which designs the processors used in Huawei's smartphones and telecommunications equipment, has reportedly moved its silicon orders from Taiwan Semiconductor Manufacturing Company (TSMC) to Semiconductor Manufacturing International Corporation (SMIC), according to DigiTimes. Why Huawei decided to do is move all of the 14 nm orders from Taiwanese foundry to China's largest silicon manufacturing fab, is to give itself peace of mind if the plan of the US Government goes through to stop TSMC from supplying Huawei. At least for the mid-tier chips built using 14 nm node, Huawei would gain some peace as a Chinese fab is a safer choice given the current political situation.

When it comes to the high-end SoCs built on 7 nm, and 5 nm in the future, it is is still uncertain how will Huawei behave in this situation, meaning that if US cuts off TSMC's supply to Huawei, they will be forced to use SMIC's 7 nm-class N+1 node instead of anything from TSMC. Another option would be Samsung, but it is a question will Huawei put itself in risk to be dependant on another foreign company. The lack of 14 nm orders from Huawei will not be reflecting much on TSMC, because whenever someone decides to cut orders, another company takes up the manufacturing capactiy. For example, when Huawei cut its 5 nm orders, Apple absorbed by ordering more capacity. When Huawei also cut 7 nm orders, AMD and other big customers decided to order more, making the situation feel like there is a real fight for TSMC's capacity.

TSMC, Taiwan's flagship manufacturer of silicon, has seen a substantial increase in demand for Chip-on-Wafer-on-Substrate (CoWoS) packaging technology, according to the report from DigiTimes. CoWoS is a multi-chip packaging technology that gives an option to build silicon like LEGO, allowing for dies to be placed side by side on interposer that is providing high interconnect density and performance. You can see more about CoWoS in detail here. Some of the examples of CoWoS are NVIDIA's P100 and V100 dies that integrate logic (computing elements), and memory (in the form of HBM) on a single die.

Recently, TSMC updated its CoWoS technology, where this new second-generation parts could scale far larger than the first-generation implementation - up to 1700 squared millimeters of die space, allowing for some very creative solutions to be implemented. This may be the reason that the demand in Q2 has risen so substantially and that TSMC's production lines are now running at full capacity, trying to meet the demand for this packaging technology.

AMD's 4th generation Ryzen desktop processors are expected to launch around September 2020, sources in the motherboard industry tell DigiTimes. Codenamed "Vermeer," successor to "Matisse," these processors will be socket AM4 multi-chip modules of up to two CPU complex dies based on the "Zen 3" microarchitecture, combined with an I/O controller die. The "Zen 3" chiplets are expected to be fabricated on a newer 7 nm-class process by TSMC, either N7P or N7+. The biggest design change with "Zen 3" is the doing away of CCX arrangement of CPU cores, with each chiplet holding a common block of cores sharing a last-level cache. This, along with clock speed headroom gains from the new node are expected to yield generational price-performance increases.

The "Zen 2" based 8-core "Renoir" die is also expected to make its socket AM4 debut within 2020, succeeding the "Picasso" based quad-core Ryzen 3000-series APUs. This is a particularly important product for AMD, as it is expected to compete with Intel's 10th generation Core i5 6-core/12-thread processors in terms of pricing, while offering more cores (8-core/16-thread) and a faster iGPU. The 4th gen Ryzen socket AM4 processor lineup will launch alongside AMD's 600-series motherboard chipset, with forwards- and backwards-compatibility (i.e., "Vermeer" and "Renoir" working with older chipsets, and older AM4 processors working on 600-series chipset motherboards). AMD was originally expected to unveil these processors at the 2020 Computex trade-show in June, but Computex itself is rescheduled to late-September.

China's state-backed SMIC (Semiconductor Manufacturing International Corporation) has set an ambitious target of Q4-2020 for its 7 nanometer-class N+1 foundry node to go live, achieving "small scale production," according to a cnTechPost report. The company has a lot of weight on its shoulders as geopolitical hostility between the U.S. and China threatens to derail the country's plans to dominate 5G technology markets around the world. The SMIC N+1 node is designed to improve performance by 20%, reduce chip power consumption by 57%, reduce logic area by 63%, and reduce SoC area by 55%, in comparison to the SMIC's 14 nm FinFET node, Chinese press reports citing a statement from SMIC's co-CEO Dr. Liang Mengsong.

Dr. Liang confirmed that the N+1 7 nm node and its immediate successor will not use EUV lithography. N+1 will receive a refinement in the form of N+2, with modest chip power consumption improvement goals compared to N+1. This is similar to SMIC's 12 nm FinFET node being a refinement of its 14 nm FinFET node. Later down its lifecycle, once the company has got a handle of its EUV lithography equipment, N+2 could receive various photomasks, including a switch to EUV at scale.

The U.S. government announced advanced measures that make it harder for foreign companies, such as Taiwan's TSMC, to supply chips to Chinese telecom hardware giant Huawei. Foreign companies that use American chipmaking equipment, are required to obtain a license from the U.S. before supplying certain chips to Huawei. Sources comment that the new rule was tailor-made to curb TSMC fabricating smartphone SoCs for Huawei's HiSilicon subsidiary.

Mainland Chinese semiconductor companies are still behind Samsung and TSMC in 7 nm-class fab technologies, forcing HiSilicon to source from the latter. 7 nm fabrication is a key requirement for SoCs and modem chips capable of 5G. The high data transceiving rates of 5G requires a certain amount of compute power that can fit into smartphone-level power-envelopes only with the help of 7 nm, at least for premium smartphone form-factors. Same applies to 5G infrastructure equipment. This is hence perceived as a means for the U.S. to clamp brakes on Huawei's plans of playing a big role in 5G tech rollouts around the world, buying western 5G tech suppliers such as Nokia time to catch up. Huawei has been a flashpoint for a bitter political spat between the U.S. and China, with the Chinese press even threatening that the matter could hamper medical supplies to the U.S. to fight the COVID-19 pandemic.

A WikiChip analysis of TSMC's next-generation 5 nanometer N5P silicon fabrication node estimates a massive 84-87% increase in transistor densities on offer compared to the company's first commercial 7 nm-class node, the N7 (7 nm DUV). The report estimates an 87% transistor-density increase, even though TSMC's own figure is slightly modest, at 84%. TSMC N5P node is expected to commence production later this year. Its precursor, TSMC N5, began risk production earlier this year, with production on the node commencing in April or May, unless derailed by the COVID-19 pandemic. The N5P node provides transistor densities of an estimated 171.3 million transistors per mm² die area, compared to 91.2 mTr/mm² of N7. Apple is expected to be the node's biggest customer in 2020, with the company building its A14-series SoC on it.

TSMC will be doing good on their previous expectations for a H2 2020 ramp-up for high volume production (HVM) on their 5 nm manufacturing process. The new 5 nm fabrication process is an Extreme Ultraviolet lithography (EUV) one, with up to 14 layers being etchable onto the silicon wafers, as opposed to five and six, respectively, for TSMC's N7+ and N6 processes.

Volume production will start with Apple's A14 SoC, meant to be driving next-generation iPhones that should hit shelves by September this year (should the COVID-19 pandemic let it be so). Apple is using two thirds of TSMC's capacity for 5 nm as is with this SoC; it's currently unclear which client (or clients) are getting the leftover one third capacity. TSMC announced back in December that they were seeing yields upwards of 80% in 5 nm EUV fabrication, so now it's "just" a matter of monetizing the process until their 3 nm iteration comes online, expectedly, in 2022.

Xilinx, Inc. today announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry's highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Versal is the industry's first adaptive compute acceleration platform (ACAP), a revolutionary new category of heterogeneous compute devices with capabilities that far exceed those of conventional silicon architectures. Developed on TSMC's 7-nanometer process technology, Versal Premium combines software programmability with dynamically configurable hardware acceleration and pre-engineered connectivity and security features to enable a faster time-to-market. The Versal Premium series delivers up to 3X higher throughput compared to current generation FPGAs, with built-in Ethernet, Interlaken, and cryptographic engines that enable fast and secure networks. The series doubles the compute density of currently deployed mainstream FPGAs and provides the adaptability to keep pace with increasingly diverse and evolving cloud and networking workloads.

Intel is rumored to be aligning its future-generation Xe GPU development with TSMC's node development cycle, with the company reportedly negotiating with the Taiwanese foundry for 6 nm and 3 nm allocation for its large Xe GPUs. Intel's first Xe discrete GPUs for the market, however, are reportedly built on the company's own 10 nm+ silicon fabrication process.

While Intel's fascination with TSMC 3 nm is understandable, seeking out TSMC's 6 nm node raises eyebrows. Internally referred to as "N6," the 6 nm silicon fabrication node at TSMC is expected to go live either towards the end of 2020 or early 2021, which is when Intel's 10 nm+ node is expected to pick up volume production, beginning with the company's "Tiger Lake" processors. Perhaps a decision has been made internally to ensure that Xe doesn't eat too much into Intel's own foundry capacities meant for processor manufacturing, and to instead outsource Xe manufacturing to third-party foundries like TSMC and Samsung eventually. Way back in April 2019 it was rumored that Intel was evaluating Samsung as a foundry partner for Xe.

AMD at its Financial Analyst Day 2020 presentation made a major clarification about its silicon fabrication process. It was previously believed that the company's upcoming "Zen 3" CPU microarchitecture and RDNA2 graphics architectures were based on TSMC's N7+ (7 nm EUV) silicon fabrication process because AMD would mark the two as "7 nm+" in its marketing slides. Throughout its Financial Analyst Day presentation, however, AMD avoided using that marker, and resorted to an amorphous "7 nm" marker, prompting one of the financial analysts to seek a clarification. At the time, AMD responded that they were aligning their marketing with that of TSMC, and hence chose to use "7 nm" in its new slides.

It turns out that the next step to TSMC N7, the company's current-generation 7 nm DUV silicon fabrication node, isn't N7+ (7 nm EUV), but rather it has a nodelet along the way, which the foundry refers to as N7P. This is a generational refinement of N7, but does not use EUV lithography, which means it may not offer the 15-20 percent gains in transistor densities offered by N7+ over N7. AMD clarified that "7 nm+" in its past presentations did not intend to signify N7+, and that the "+" merely denoted an improvement over N7. At the same time, it won't specify whether "Zen 3" and RDNA2 are based on N7P or N7+, so the company doesn't rule out N7+, either. We'll probably learn more as we near the late-2020 launch of "Zen 3" as EPYC "Milan."

AMD Financial Analyst Day presents an opportunity for AMD to talk straight with the finance industry about the company's current financial health, and a taste of what's to come. Guidance and product teasers made during this time are usually very accurate due to the nature of the audience. In this live blog, we will post information from the Financial Analyst Day 2020 as it unfolds.20:59 UTC: The event has started as of 1 PM PST. CEO Dr Lisa Su takes stage.

Ampere Computing, a startup focusing on making HPC and processors from cloud applications based on Arm Instruction Set Architecture, today announced the release of a first 80 core "cloud-native" processor based on the Arm ISA. The new Ampere Altra CPU is the company's first 80 core CPU meant for hyper scalers like Amazon AWS, Microsoft Azure, and Google Cloud. Being built on TSMC's 7 nm semiconductor manufacturing process, the Altra is a CPU that is utilizing a monolithic die to achieve maximum performance. Using Arm's v8.2+ instruction set, the CPU is using the Neoverse N1 platform as its core, to be ready for any data center workload needed. It also borrows a few security features from v8.3 and v8.5, namely the hardware mitigations of speculative attacks.

When it comes to the core itself, the CPU is running at 3.0 GHz frequency and has some very interesting specifications. The design of the core is such that it is 4-wide superscalar Out of Order Execution (OoOE), which Ampere refers to as "aggressive" meaning that there is a lot of data throughput going on. The cache levels are structured in a way that there is 64 KB of L1D and L1I cache per core, along with 1 MB of L2 cache per core as well. For system-level cache, there is 32 MB of L3 available to the SoC. All of the caches have Error-correcting code (ECC) built-in, giving the CPU a much-needed feature. There are two 128-bit wide Single Instruction Multiple Data (SIMD) units, which are there to do parallel processing if needed. There is no mention if they implement Arm's Scalable Vector Extensions (SVE) or not.

TSMC today announced it has collaborated with Broadcom on enhancing the Chip-on-Wafer-on-Substrate (CoWoS ) platform to support the industry's first and largest 2X reticle size interposer. With an area of approximately 1,700mm2, this next generation CoWoS interposer technology significantly boosts computing power for advanced HPC systems by supporting more SoCs as well as being ready to support TSMC's next-generation five-nanometer (N5) process technology.

This new generation CoWoS technology can accommodate multiple logic system-on-chip (SoC) dies, and up to 6 cubes of high-bandwidth memory (HBM), offering as much as 96 GB of memory. It also provides bandwidth of up to 2.7 terabytes per second, 2.7 times faster than TSMC's previously offered CoWoS solution in 2016. With higher memory capacity and bandwidth, this CoWoS solution is well-suited for memory-intensive workloads such as deep learning, as well as workloads for 5G networking, power-efficient datacenters, and more. In addition to offering additional area to increase compute, I/O, and HBM integration, this enhanced CoWoS technology provides greater design flexibility and yield for complex ASIC designs in advanced process nodes.

TSMC is set to hire about 4000 new staff members to gain a workforce for its development of next-generation semiconductor manufacturing nodes. The goal of the company is to gather talent so it can develop the world's leading semiconductor nodes, like 3 nm and below. With 15 billion USD planned for R&D purposes alone this year, TSMC is investing a big part of its capital back into development on new and improved technology. Markets such as 5G and High-Performance Computing are leading the charge and require smaller, faster, and more efficient semiconductor nodes, which TSMC plans to deliver. To gather talent, TSMC started job listing using recruitment website TaiwanJobs and started campaigns on university campuses to attract grad students.

Apple is currently designing a custom series of CPUs, for its Macbook laptop lineup, based on the Arm Instruction Set Architecture. Having designed some of the most powerful mobile processors that are inside the iPhone series of devices, Apple is preparing to make a jump to an even more powerful device lineup by bringing custom CPUs for MacBook. Tired of the speed by which Intel replaces and upgrades its Core lineup of CPUs, Apple decided to take the matter in its own hands and rumors about the switch to a custom solution have been going on for a while. However, we now have some information about when to expect the first wave of Arm-powered Macs.

According to the analyst Ming-Chi Kuo, who is a well-known insider in the Apple industry, we can expect the first wave of the Arm-powered Macbook in the next 18 months, precisely in the first half of 2021. Supposedly, the first chips for these new Macs are going to be manufactured on a 5 nm manufacturing process, possibly over at TSMC since Apple had a long-lasting history of manufacturing its chips at TSMC foundries. In the meantime, we can expect to see Apple providing developers with tools to transition their x86-64 software to the new Arm ISA. Without a software ecosystem, the hardware platform is essentially worthless. And Apple knows this. We will see how they plan to play it and will report as soon as there is more information.

With a 2.4-liter volume, a conventional black plastic body, and essential connectivity, the Ruijie RG-CT7800 may come across as a run-of-the-mill mini-PCs for small businesses or those who do precious little offline, except what's under the hood. This humble compact desktop is among the first design wins of China's ambitious effort at having an x86 processor built entirely on Chinese soil, the Zhaoxin KaiXian. This processor is making its way to products, and was recently pictured on an embedded motherboard. The KaiXian, along with the notebooks, motherboards, micro-servers, and mini-PCs that implement it, form the tip of China's 3-5-2 policy, an ambitious plan to rid all state- and state-owned institutions of "foreign hardware."

The numerals in "3-5-2" are supposed to correspond to foreign hardware replacement targets set by the country's Central Government - 30% by the end of 2020, an additional 50% by the end of 2021, and the remaining 20% by the end of 2022. To support this plan, the Chinese electronics industry, flush with state investment, has indigenized several key components of the modern PC, including DRAM, NAND flash, and now CPU. The country already dominates the global electronic components market. The RG-CT7800 implements The KaiXian KX-U6780A SoC that sports eight x64 CPU cores running at 2.70 GHz. Interestingly, the chip is manufactured on TSMC's 16 nm FinFET node (a de facto "foreign" source, but one that's de jure China from Beijing's perspective). Ruijie is equipping the RG-CT7800 with 8 GB of DDR4 memory, and 256 GB of SSD-based storage. One can make out industry-standard USB, Ethernet, 3.5 mm audio jacks, etc., from the pictures. The box will be compatible with UOS and NeoKylin (Linux distros built under scrutiny of the Chinese Government). With state institutions being on the clock to implement their 3-5-2 targets, it's possible that the first volumes of RG-CT7800 will be sold exclusively to state customers.