Thursday, January 14th 2021
AMD Talks Zen 4 and RDNA 3, Promises to Offer Extremely Competitive Products
AMD is always in development mode and just when they launch a new product, the company is always gearing up for the next-generation of devices. Just a few months ago, back in November, AMD has launched its Zen 3 core, and today we get to hear about the next steps that the company is taking to stay competitive and grow its product portfolio. In the AnandTech interview with Dr. Lisa Su, and The Street interview with Rick Bergman, the EVP of AMD's Computing and Graphics Business Group, we have gathered information about AMD's plans for Zen 4 core development and RDNA 3 performance target.
Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.When it comes to RDNA 3, the company has plans to offer an architecture that has a high performance-per-watt. Just like AMD improved performance-per-watt of RDNA 2, it plans to do the same with RDNA 3, bringing the efficiency of the architecture to the first spot and making it very high-performance for any possible task.
Sources:
AnandTech, The Street, via WCCFTech
Starting with Zen 4, AMD plans to migrate to the AM5 platform, bringing the new DDR5 and USB 4.0 protocols. The current aim of Zen 4 is to be extremely competitive among competing products and to bring many IPC improvements. Just like Zen 3 used many small advances in cache structures, branch prediction, and pipelines, Zen 4 is aiming to achieve a similar thing with its debut. The state of x86 architecture offers little room for improvement, however, when the advancement is done in many places it adds up quite well, as we could see with 19% IPC improvement of Zen 3 over the previous generation Zen 2 core. As the new core will use TSMC's advanced 5 nm process, there is a possibility to have even more cores found inside CCX/CCD complexes. We are expecting to see Zen 4 sometime close to the end of 2021.When it comes to RDNA 3, the company has plans to offer an architecture that has a high performance-per-watt. Just like AMD improved performance-per-watt of RDNA 2, it plans to do the same with RDNA 3, bringing the efficiency of the architecture to the first spot and making it very high-performance for any possible task.
62 Comments on AMD Talks Zen 4 and RDNA 3, Promises to Offer Extremely Competitive Products
As for RDNA3, multiple dies on a GPU would be the next big thing for GPUs if connected properly to have low latency. Other than that, clocks and efficiency will be the main progress target as usual.
To sum it up, TSMS's manufacturing progress and capacity will be the limiting factor for the PC sector's performance progress.
Would be cool if they really releases zen 4 this time.
On the graphics front, I expect AMD to go all-in on Ray-Tracing and geometry this iteration. I expect them to match, or slightly beat nVidias current RTX gen. nVidia will retake the RT perf crown with whatever architecture they have out next, but the RT wars will properly start in 2021.
What the accelerators do enable is truly excellent performance per watt in select use cases like watching videos or video calls, or encoding stuff.
Also keep in mind that Apple owns the compilers and the OS as well, so they have a different level of system wide control that no other hardware company has today. This allows them to squeeze out extra performance that the competition can not.
There are barely any benchmarks to test the CPU with yet, so let's wait until there are some proper benchmarks out.
I'm not saying Apple made a bad chip, just that you're misunderstanding what IPC means. I'm not saying it's wrong, I'm saying it's not IPC, as in instructions per clock.
Accelerators are fine, I mean, they are there to handle the things that the general purpose CPU cores aren't good at.
It's just that people need to make a difference between overall system performance and IPC, as the two are not directly related these days. In this case, I would simply say that all Apple hardware gets preferential GeekBench scores. Also, it's a pretty crap benchmark.
IPC is NOT what you think it is.
What am I missing here?
edit: for example take these results:
The clock speed of the ryzen 5950x in this test is somewhere between 4.5 and 5 GHz. The M1 runs around 3.2 GHz. Assuming that the compiled executables for SPEC contain around the same amount of instructions for both architectures the IPC of M1 is around 45% higher than ryzen 5950x for single threaded use.
And to clarify, the above test makes no use of fixed function accelerators.
cpu A can execute X amount of it while running SSE code y
but Y on B cpu is returned faster more quickly
Both cpu A and B have the same IPC because the Instructions Pre-clock is the same how ever the return is not. Efficiencies in designs can return more.
If you took all the SSE/AVX/AES/FMA3 and changed them so they ran perfectly from each of a single core each when ran you'd have an X86 cpu with about 14 cores that great at single thread for a given program but junk at multi thread and large increase in silicon space.
sometimes being good a one thing makes you bad at others,
Whichever way you look at it, Seeing the M1 run software that's not even compiled for the architecture, and doing it this quickly to me shows that increasing the processing per clock at least isn't an impossibility. x86 Makers might need to further virtualize their decoding hardware/stack to reach that state however.
PS: Regarding the singlecore perfomance, decoders and instructions, does your view somewhat relate to this story i just found? Exclusive: Why Apple M1 Single "Core" Comparisons Are Fundamentally Flawed (With Benchmarks) (wccftech.com)
This is why Geekbench is a POS. Performance didn't suddenly appear out of nowhere, and people don't differentiate between Geekbench VERSIONS even though the app changes all the time.
You can come up with an "average IPC" but that wouldn't mean much either.