Cadence and Micron have joined forces to build the world's first working DDR5-4400 memory module. Cadence provided their DDR5 memory controller and PHY for the prototype while Micron produced the 8 Gb chips, which were manufactured under TSMC's 7 nm process. They were able to achieve 4400 megatransfers per second, which is roughly 37.5% faster than the fastest DDR4 memory that is currently on the market. Nevertheless, Marc Greenberg from Cadence emphasized that DDR5 aims to provide increased capacity solutions, more than actual performance.

The DDR5 standard should facilitate the production of 16 Gb dies and make vertical stacking easier. Restricted by laws of physics, dies eventually get slower as they increased in size. Once you start putting 16Gb die in 1X memory technology, the distances between them starts to get longer. As a result, core timing parameters become worse. Cadence's prototype had a CAS latency of 42 (No, not a typo). Although, the test module does run at 1.1 volts, which makes it quite impressive when compared to DDR4.

TSMC is close to adapt 3D stacked silicon wafers to complex silicon designs, such as graphics processors, using its new proprietary Wafer-on-Wafer (WoW) Advanced Packaging technology, which will be introduced with its 7 nm+ and 5 nm nodes. 3D stacked silicon fabrication is currently only implemented on "less complex" silicon designs, such as NAND flash, which don't run anywhere near as hot as complex designs ASIC designs, such as GPUs or CPUs. In its current form, TSMC achieved 2-layer stacks, in which two silicon layers that are "mirror images" of each other (for perfect alignment), sandwich bonding layers, through which pins for the upper layer pass through.

The bonding of the two layers is where the bulk of TSMC's innovations and "secret sauces" lie. For 3D NAND flash, multiple pancaked dies are wired out through their edges. You don't need as many pins to talk to a NAND flash die, as say a GPU die. For complex dies, designers have to pass thousands of pins through the "bottom layer," the connecting substrate, and eventually to the "top layer." The bottom layer hence is bumped out on both ends, one side interfacing with the package substrate for both dies, and the top side serving as a sort of substrate for the top die. This innovation is what TSMC calls "thru-silicon-vias" or TSVs.

AMD has announced via its Twitter feed that the Vega die shrink from current 14 nm down to 7 nm has actually coalesced into a hardware product that can be tested and vetted at their labs. Via a teaser image, the company said that "7nm @RadeonInstinct product for machine learning is running in our labs."

Of course, working silicon is only half the battle - considerations such as yields, leakage, and others are all demons that must be worked out for actual production silicon, which may thus be some months off. Only AMD and TSMC themselves themselves know how the actual production run went - and the performance and power efficiency that can be expected from this design (remember that AMD's CEO Lisa SU herself said they'd partner with both TSMC and Globalfoundries for the 7 nm push, though it seems TSMC may be pulling ahead in that field). Considering AMD's timeline for the die-shrunk Vega to 7 nm - with predicted product launch for 2H 2018 - the fact that there is working silicon being sampled right now is definitely good news.

Semiconductor manufacturers have been historically bullish when it comes to the introduction of new manufacturing technologies. Intel, AMD (and then Globalfoundries), TSMC, all are companies who thrive in investors' confidence: they want to paint the prettiest picture they can in terms of advancements and research leadership, because that's what attracts investment, and increased share value, and thus, increased funds to actually reach those optimistic goals.

However, we've seen in recent years how mighty Intel itself has fallen prey to unforeseen complications when it comes to advancements of its manufacturing processes, which saw us go from a "tick-tock" cadence of new architecture - new manufacturing process, to the introduction of 14 nm ++ processes. And as Intel, Globalfoundries and TSMC race towards sub 7-nm manufacturing processes with 250 mm wafers and EUV usage, things aren't getting as rosy as the ultraviolet moniker would make us believe.

Xilinx, Inc., the leader in adaptive and intelligent computing, today announced a new breakthrough product category called adaptive compute acceleration platform (ACAP) that goes far beyond the capabilities of an FPGA. An ACAP is a highly integrated multi-core heterogeneous compute platform that can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads. An ACAP's adaptability, which can be done dynamically during operation, delivers levels of performance and performance per-watt that is unmatched by CPUs or GPUs.

An ACAP is ideally suited to accelerate a broad set of applications in the emerging era of big data and artificial intelligence. These include: video transcoding, database, data compression, search, AI inference, genomics, machine vision, computational storage and network acceleration. Software and hardware developers will be able to design ACAP-based products for end point, edge and cloud applications. The first ACAP product family, codenamed "Everest," will be developed in TSMC 7nm process technology and will tape out later this year.

In what could bring cheers to PC gamers, and tears to miners, NVIDIA is reportedly wary of a possible drop in cryptocurrencies through 2018. This directly affects the company, since GPUs are used in mining various cryptocurrencies, which triggered inflation in prices of graphics cards from Q2-2017 to Q1-2018. Over the past couple of weeks, prices of popular high-end GPUs such as the GeForce GTX 1080 Ti have cooled, although not back to their original levels. NVIDIA's manufacturing division, which sub-contracts silicon fabrication to TSMC, is calculating the impact a cryptocurrency slump could have on its supply-chain, and are being conservative with their orders to the foundry. A drop in demand could leave the company with vast amounts of unsold inventories based on an old-generation architecture (Pascal, in the wake of Volta/Ampere), which could result in multi-billion-dollar inventory write-offs. According to a Digitimes report, NVIDIA has placed restrictions on its add-in card (AIC) partners on marketing cryptocurrency mining abilities of their graphics cards, and selling directly to large miners.

In addition to a slump in demand for cryptocurrencies, 2018 could see introduction of purpose-built crypto-mining ASICs that are tailored for popular cryptocurrencies. Purpose-built ASICs tend to be extremely economical for medium-thru-large scale miners, in comparison to GPUs. The third horseman is policy. While several governments around the world have developed an appreciation for blockchain technology for its resilience to tampering, fraud, and data-theft (which could be implemented in safekeeping government- and bank-records); governments are, understandably, anti-cryptocurrency, as it undermines sovereign legal tender issued by central banks, and aids tax-evasion. Several governments through 2017-18 have announced measures to crack down on cryptocurrency mining and use as tender. This has led to a further drop in public interest in cryptocurrencies, as large ICO investors are weary of losing money in a highly volatile market. Close to half the ICOs have failed.

TSMC is the world's sole ASIC manufacturer for Bitmain - the world's largest ASIC vendor by far, commanding some 70% of the ASIC market share. DigiTimes is reporting that ASIC manufacturing will be a major part of bridging the 10-15% increase in revenue that TSMC's chairman Morris Chang expects for 2018, which will be mostly fed by high-performance computing (HPC), car-use electronics and Internet of Things (IoT) products.

One other interesting tidbit that DigiTimes is reporting on is that Bitmain might be increasing its ASIC orders from TSMC to bring a new Ethereum ASIC miner to market. Dubbed the F3, reports around the internet have placed these ASICs as leveraging TSMC's 28 nm process in a three-mainboard system. Each mainboard is reported to pack six purpose-built ASIC processors, each paired with 12GB of DDR3 memory. Whether or not this makes sense based on Ethereum's Casper update (moving from a Proof of Work to a Proof of Stake mechanism) remains to be seen. Considering the amount of work and investment that would be required towards the development of an Ethereum ASIC, though (a natively ASIC-resistant algorithm) may very well be an indicator that Casper may be longer off in the horizon than previously thought. Let's hope this is true, though; an Ethereum-geared ASIC, even if short-lived, would certainlydraw demand away from GPUs to these purpose-built systems, and there's been nary a time in the PC world where such an event was as needed as it is today.

NVIDIA prepares to make its annual tech expo, the 2018 Graphics Technology Conference (GTC) action-packed. The company already surprised us with its next-generation "Volta" architecture based TITAN V graphics card priced at 3 grand; and is working to cash in on the crypto-currency wave and ease pressure on consumer graphics card inventories by designing highly optimized mining accelerators under the new Turing brand. There's now talk that NVIDIA could pole-vault launch of the "Volta" architecture for the consumer-space; by unveiling a GeForce graphics card based on its succeeding architecture, "Ampere."

The oldest reports of NVIDIA unveiling "Ampere" date back to November 2017. At the time it was expected that NVIDIA will only share some PR blurbs on some of the key features it brings to the table, or at best, unveil a specialized (non-gaming) silicon, such as a Drive or machine-learning chip. An Expreview report points at the possibility of a GeForce product, one that you can buy in your friendly neighborhood PC store and play games with. The "Ampere" based GPU will still be based on the 12 nanometer silicon fabrication process at TSMC, and is unlikely to be a big halo chip with exotic HBM stacks. Why NVIDIA chose to leapfrog is uncertain. GTC gets underway late-March.

One of the world's largest SoC, DRAM, and NAND flash makers, with its own semiconductor fabs, Samsung, is eyeing itself a large slice of the crypto-currency mining craze. The company reportedly entered volume production of a highly efficient crypto-currency mining ASIC, for an unnamed client from China. The client has placed a gargantuan order for crypto-coin mining ASICs contract-manufactured by Samsung, which appears to be targeted at Bitcoin, for now.

China's largest mining ASIC solutions providers, Bitman and Cannan, have similarly contracted TSMC to manufacture mining ASICs. An ASIC (from a mining context) is a single-chip solution that combines a CPU, a SIMD parallel-processing component tailored for mining, memory, and storage. It has infinitesimally smaller PCB, power, and thermal footprints compared to PCs with GPUs, and can be deployed in extremely large numbers for mining on an industrial-scale.

TSMC today held a groundbreaking ceremony for its Fab 18, Phase 1 facility at the Southern Taiwan Science Park. Led by Chairman Dr. Morris Chang, the event demonstrates TSMC's ongoing commitment to investing in Taiwan as well as to environmental sustainability, and marks another milestone in TSMC's 30-year history and its competitive advantage in technology leadership, manufacturing excellence, and customer trust. TSMC's Fab 18 will be its fourth 12-inch GigaFab in Taiwan and is scheduled for production of the advanced 5 nanometer process.

Following today's groundbreaking, the Company plans to complete construction of Phase 1 and begin equipment move-in in the first quarter of 2019, with volume production in early 2020. Phase 2 will start construction in third quarter 2018 and also enter volume production in 2020, while Phase 3 construction is scheduled for third quarter 2019 for volume production in 2021. Once all three phases enter production, the facility's estimated annual capacity will exceed one million 12-inch wafers, providing 4,000 high-quality jobs and becoming another bastion of TSMC's manufacturing excellence.

If 2015 was all about OLED, and 2016-17 about quantum-dot (QLED), Samsung will herald the MicroLED display panel era in 2018, with its first implementation, a massive 150-inch television, which will be showcased at the 2018 International CES. A MicroLED panel uses solid-state LED elements etched onto a silicon-substrate, that are less than 100 µm in size, each, which act as individual pixels. If you're familiar with microscopic transistors that make up modern semiconductor chips, imagine if LEDs were built on that scale. That's MicroLED.

With further development, MicroLED panels will achieve higher pixel densities, and won't suffer form "burn-in" problems that OLED (organic LED) panels suffer from displaying the same image over extended periods of time. It also offers significantly lower power-draw compared to OLED. The 150-inch MicroLED TV prototype Samsung is showing off at CES will come with 4K Ultra HD resolution. Samsung's next implementation of the MicroLED tech could be smartphone display panels. The company's main rival in this area, Apple, is already working with TSMC to develop MicroLED panels of its own.

TSMC has announced the location for their first 3 nm fab: it will be built in the Tainan Science Park, southern Taiwan. Rumors pegged the new 3 nm factory as possibly being built in the US, due to political reasons; however, TSMC opted to keep their production capabilities clustered in the Tainan Science Park, where they can better leverage their assets and supply chain for the production and support of the world's first 3 nm semiconductor factory. It certainly also helped the Taiwanese government's decision to pledge land, water, electricity and environmental protection support to facilitate TSMC's latest manufacturing plan. It's expected that at least part of the manufacturing machines will be provided by ASML, a Netherlands-based company which has enjoyed 25% revenue growth already just this year.

As part of the announcement, TSMC hasn't given any revised timelines for their 3 nm production, which likely means the company still expects to start 3 nm production by 2022. TSMC said its 7 nm yield is ahead of schedule, and that it expects a fast ramp in 2018 - which is interesting, considering the company has announced plans to insert several extreme ultraviolet (EUV) layers at 7 nm. TSMC has also said its 5 nm roadmap is on track for a launch in the first quarter of 2019.

AMD's RX Vega supply has seen exceedingly limited quantities available since launch. This has been due to a number of reasons, though the two foremost that have been reported are: increased demand from cryptocurrency miners, who are looking towards maximizing their single node hashrate density through Vega's promising mining capabilities; and yield issues with AMD's Vega 10 HBM2 packaging partner, Advanced Semiconductor Engineering (ASE). It's expected that chip yield for Vega 10 is also lower per se, due to it having a 484 mm² die, which is more prone to defects than a smaller one, thus reducing the amount of fully-enabled GPUs.

AMD's production partner, GlobalFoundries, has historically been at the center of considerations on AMD's yield problems. That GlobalFoundries is seemingly doing a good job with Ryzen may not be much to say: those chips have incredibly small die sizes (192 mm²) for their number of cores. It seems that Global Foundries only hits problems with increased die sizes and complexity (which is, unfortunately for AMD, where it matters most).

Dutch company ASML may not be very known to us mortal users, but it has one of the greatest aces up its sleeve: it specializes in what are some of the most complex machines currently made by mankind. Extreme Ultraviolet Lithography Systems (EUV) are the kind of machines that make you look in wonder and amazement at man's ingenuity - ASML, which specializes in this type of systems, has a production capability for 2017 that numbers just 12 of these. That means on average, they take a whole month putting one of these together. That really goes to show the complexity inherent to these systems. And it shows: EUV machines are about the size of a city bus, and typically cost more than 100 million euros ($115.3 million) each.

The revenue growth forecast is spurred by an additional 8 EUV systems being ordered by ASML's clients, which include Intel, Samsung, and TSMC - some of the biggest players in the semiconductor business. The new orders brought the company's order backlog to 27 machines - more than double their current annual output. ASML is taking steps to to ensure an increase in production capability to keep up with the multi million-dollar demand: the company is set to expand its system production capability to 24 in 2018, before reaching an expected capacity of around 40 systems in 2019. Third-quarter revenue will be about 2.2 billion euros ($2.5 billion), the Veldhoven, Netherlands-based maker of chip-making machines predicts. The company's stock valuation has increased some 30% over the past year - the company's valuation currently stands at around €53 billion ($61 billion.)

Microsoft Sunday dropped its mic with the most powerful game console on paper, the Xbox One X, formerly codenamed "Project Scorpio." The bottom-line of this console is that it enables 4K Ultra HD gaming at 60 Hz. Something like this requires you to spend at least $1,200 on a gaming desktop right now. Unlike a Windows 10 PC that's been put together by various pieces of hardware, the Xbox One X is built on a closed ecosystem that's tightly controlled by Microsoft, with heavily optimized software, and a lot of secret sauce the company won't talk about. The console still puts up some mighty impressive hardware specs on paper.

To begin with, at the heart of the Xbox One X is a semi-custom SoC Microsoft co-developed with AMD, built on TSMC's 16 nm FinFET node (the same one NVIDIA builds its "Pascal" GPUs on). This chip features a GPU with almost quadruple the single-precision floating point compute power as the one which drives the Xbox One. It features 40 Graphics CoreNext (GCN) compute units (2,560 stream processors) based on one of the later versions of GCN (likely "Polaris"). The GPU is clocked at 1172 MHz. The other big component of the SoC is an eight-core CPU based on an unnamed micro-architecture evolved from "Jaguar" rather than "Bulldozer" or even "Zen." The eight cores are arranged in two quad-core units of four cores, each; with 4 MB of L2 cache. The CPU is clocked at 2.30 GHz.

AMD co-founder Jerry Sanders, in 2009 was famously quoted as stating that "real men have fabs," a jibe probably targeted at the budding fab-less CPU designers of the time. Years later, AMD spun-off its silicon fabrication business, which with a substantial investment of the Abu Dhabi government through its state-owned Advanced Technology Investment Company (ATIC), became GlobalFoundries (or GloFo in some vernacular). This company built strategic partnerships with the right players in the industry, acquisitions such as IBM's fabs, and is now at the forefront of sub-10 nm fab development. It remained one of AMD's biggest foundry partners besides TSMC and Samsung, and is manufacturing its AMD processors at a brand new facility in Upstate New York, USA.

AMD, on the other hand, doesn't regret spinning off GloFo. Speaking at Merrill Lynch Global Technology and Investment Conference, CTO Mark Papermaster said, that going fab-less has helped AMD focus on chip-design without worrying about manufacturing. Production is no longer a bottleneck for AMD, as it can now put out manufacturing contracts to a wider variety of foundry partners. Its chip-designers aren't limited by the constraints of an in-house fab, and can instead ask external fabs to optimize their nodes for their chip-designs, Papermaster said. 14 nm FinFET has added a level of standardization to the foundry industry.

In the Q&A section of their 2017 Financial Analyst Day, AMD CEO Lisa Su answered an enquiry from a Deutsche-bank questioner regarding the company's aggressive 7 nm plan for their roadmap, on which AMD seems to be balancing its process shrinkage outlook for the foreseeable future. AMD will be developing their next Zen architecture revisions on 7 nm, alongside a push for 7 nm on their next-generation (or is that next-next generation?) Navi architecture. This means al of AMD's products, consumer, enterprise, and graphics, will be eventually built on this node. This is particularly interesting considering AMD's position with GLOBALFOUNDRIES, with which AMD has already had many amendments to their Wafer Supply Agreement, a remain of AMD's silicon production division spin-off, the latest of which runs from 2016 to 2020.

As it is, AMD has to pay GLOBALFOUNDRIES for its wafer orders that go to other silicon producers (in this case, TSMC), in a quarterly basis since the beginning of 2017, based on the volume of certain wafers purchased from another wafer foundry. In addition, AMD has annual wafer purchase targets from 2016 through the end of 2020, fixed wafer prices for 2016, and a framework for yearly wafer pricing in this amendment, so the company is still bleeding money to GLOBALFOUNDRIES. However, AMD is making the correct decision in this instance, I'd wager, considering GLOBALFOUNDRIES' known difficulties in delivering their process nodes absent of quirks.

Today at its GTC keynote, NVIDIA CEO Jensen Huang took the wraps on some of the features on their upcoming V100 accelerator, the Volta-based accelerator for the professional market that will likely pave the way to the company's next-generation 2000 series GeForce graphics cards. If NVIDIA goes on with its product carvings and naming scheme for the next-generation Volta architecture, we can expect to see this processor on the company's next-generation GTX 2080 Ti. Running the nitty-gritty details (like the new Tensor processing approach) on this piece would be impossible, but there are some things we know already from this presentation.

This chip is a beast of a processor: it packs 21 billion transistors (up from 15,3 billion found on the P100); it's built on TSMC's 12 nm FF process (evolving from Pascal's 16 nm FF); and measures a staggering 815 mm² (from the P100's 610 mm².) This is such a considerable leap in die-area that we can only speculate on how yields will be for this monstrous chip, especially considering the novelty of the 12 nm process that it's going to leverage. But now, the most interesting details from a gaming perspective are the 5,120 CUDA cores powering the V100 out of a total possible 5,376 in the whole chip design, which NVIDIA will likely leave for their Titan Xv. These are divided in 84 Volta Streaming Multiprocessor Units with each carrying 64 CUDA cores (84 x 64 = 5,376, from which NVIDIA is cutting 4 Volta Streaming Multiprocessor Units for yields, most likely, which accounts for the announced 5,120.) Even in this cut-down configuration, we're looking at a staggering 42% higher pure CUDA core-count than the P100's. The new V100 will offer up to 15 FP 32 TFLOPS, and will still leverage a 16 GB HBM2 implementation delivering up to 900 GB/s bandwidth (up from the P100's 721 GB/s). No details on clock speed or TDP as of yet, but we already have enough details to enable a lengthy discussion... Wouldn't you agree?

In the highly competitive, high-stakes scene of the business world - and particularly so in the silicon giants of the era - trade secrets, specifications, and protecting one's intellectual property that give the leg-up on competitors is key towards success. And while most companies work within the meanders of law (even if sometimes skirting it ever so lightly), some don't. And things like this happen: the steal (or purported steal, because no one has been convicted yet) of trade secrets by former employees is one of the most dreaded occurrences in the tech world - remember Zenimax and Carmack's "dovetailing"?

Chinese manufacturers are looking to enter the high-performance computing market with their own products, designs, and manufacturing capability. In this case, former TSMC engineer Hsu is being accused of stealing proprietary information and other materials related to the foundry's 28 nm process technology. The goal would be to pass them to China-based Shanghai Huali Microelectronics (HLMC), with which he accepted a job offer, according to the Hsinchu District Prosecutors Office. Digitimes reports that HLMC had been aggressively headhunting for talent to kick start its 28 nm manufacturing process, though if true, this sound like a little too aggressive of a headhunting.

NVIDIA's next-generation "Volta" GPU architecture got its commercial debut in the most unlikely class of products, with the Xavier autonomous car processor. The actual money-spinners based on the architecture, consumer GPUs, will arrive some time in 2018. The company will be banking on its old faithful fab TSMC, to build those chips on a new 12 nanometer FinFET node that's currently under development. TSMC's current frontline process is the 16 nm FFC, which debuted in mid-2015, with mass-production following through in 2016. NVIDIA's "GP104" chip is built on this process.

This could also mean that NVIDIA could slug it out against AMD with its current GeForce GTX 10-series "Pascal" GPUs throughout 2017-18, even as AMD threatens to disrupt NVIDIA's sub-$500 lineup with its Radeon Vega series, scheduled for Q2-2017. NVIDIA's "Volta" architecture could see stacked DRAM technologies such as HBM2 gain more mainstream exposure, although competing memory standards such as GDDR6 aren't too far behind.

TSMC (Taiwan Semiconductor Manufacturing Co.), one of the foremost semiconductor producers in the world - which controls a leading 55% share of the global market - said on Wednesday it plans to build a new, $15.7 billion facility in Taiwan that would churn out 5 nm and 3 nm chips. If TSMC were to achieve these production nodes in a timely fashion (with "timely" meaning "before their competitors"), that would prove a huge boon for the company, as everyone - and especially deep-pocketed smartphone chip designers such as Apple and Qualcomm - is looking towards evolution in process nodes, which allows for improvements in power consumption, performance, size and cost of chips per wafer.

"We're asking the government to help us find a plot that is large enough (123 to 197 acres) and has convenient access so we can build an advanced chip plant to manufacture 5 nm and 3 nm chips," TSMC spokesperson Elizabeth Sun said. The spokesperson declined to provide details about the timing of the construction and production, though it's seemingly still a few years away (yet close enough for it to merit an official request). TSMC co-CEO Mark Liu had already mentioned that the company was working on 5 nm chips, and had assigned the task of developing 3 nm technology and conducting research on 2 nm technology to upwards of 300 engineers. Delays on EUV (Extreme Ultraviolet) lithography have slowed expected advancements in further miniaturization of the process nodes. It remains to be seen which technology TSMC is counting on towards aiding them in their goals for 5 nm, 3 nm and the mentioned 2 nm chip production, especially since at those sizes, we start leaving the usual realm of plane old physics, crossing the threshold towards their exotic cousins, quantum physics.

Microsoft's new slim Xbox One S console achieves its slimness - including its inbuilt power-supply, by significantly reducing thermal load of its key components. This begins at the heart of the console, its SoC. A semi-custom chip by Microsoft and AMD, the SoC powering the Xbox One S is built on the 16 nm FinFET process at TSMC. The chip powering the original Xbox One was built on the same foundry's 28 nm node.

The new SoC isn't merely an optical shrink of the original 28 nm chip down to 16 nm FinFET, Microsoft added a few components to the chip, including an HEVC hardware decoder, hardware CODECs for Blu-ray UHD with HDR; and a revamped display controller with HDMI 2.0 and HDCP 2.2. The chip also performs 1080p to 4K UHD upscaling, with a native upscaling algorithm. The eSRAM memory bandwidth is increased slightly from 204 GB/s from 219 GB/s.

Following the surprise TITAN X Pascal launch slated for 2nd August, it looks like NVIDIA product development cycle is running on steroids, with reports emerging of the company accelerating its next-generation "Volta" architecture debut to May 2017, along the sidelines of next year's GTC. The architecture was originally scheduled to make its debut in 2018.

Much like "Pascal," the "Volta" architecture could first debut with HPC products, before moving on to the consumer graphics segment. NVIDIA could also retain the 16 nm FinFET+ process at TSMC for Volta. Stacked on-package memory such as HBM2 could be more readily available by 2017, and could hit sizable volumes towards the end of the year, making it ripe for implementation in high-volume consumer products.

Japanese conglomerate Softbank acquired British CPU architecture designer ARM in a USD $32 billion deal on Monday. Softbank's bid of $32 billion is a 43 percent premium over ARM's current valuation of $22.3 billion, and the Cambridge-based firm will recommend its shareholders to approve of its acquisition. Shares of ARM surged 45% on the LSE, adding £7.56 billion to its market value. The company reported revenues of $1.49 billion in 2015. ARM founder Herman Hauser, however, isn't happy with the board's decision. "This is a sad day for me and a sad day for technology in Britain," he stated.

ARM designs CPU architectures, which it then licenses to other processor and SoC manufacturers, many of which are fabless themselves, making it an intellectual property giant. None of ARM's products are "tangible" or physical. While Intel, for example, designs CPU architectures (eg: x86), implements it (eg: Core i7, Celeron), and manufactures it (at its Costa Rica and Malaysia fabs) ARM's product is not tangible. It has a CPU architecture, which clients such as Samsung, Huawei, and Qualcomm license, implement (eg: Exynos, Kylin, Snapdragon), and contract-manufacture, through fabs such as GlobalFoundries, TSMC, and ST Microelectronics.

Here are two of the first pictures of NVIDIA's upcoming "GP104" graphics processor. This chip will drive at least three new GeForce SKUs bound for a June 2016 launch; and succeeds the GM204 silicon, which drives the current-gen GTX 980 and GTX 970. Based on the "Pascal" architecture, the GPU will be built on TSMC's latest 16 nm FinFET+ node. The chip appears to feature a 256-bit wide GDDR5 memory interface, and is rumored to feature a memory clock of 8 Gbps, yielding a memory bandwidth of 256 GB/s.