MIT researchers have developed a groundbreaking technology that allows for the growth of 2D transition metal dichalcogenide (TMD) materials directly on fully fabricated silicon chips, enabling denser integrations. Conventional methods require temperatures of about 600°C, which can damage silicon transistors and circuits as they break down above 400°C. The MIT team overcame this challenge by creating a low-temperature growth process that preserves the chip's integrity, allowing 2D semiconductor transistors to be directly integrated on top of standard silicon circuits. The new approach grows a smooth, highly uniform layer across an entire 8-inch wafer, unlike previous methods that involved growing 2D materials elsewhere before transferring them to a chip or wafer. This process often led to imperfections that negatively impacted device and chip performance.

Additionally, the novel technology can grow a uniform layer of TMD material in less than an hour over 8-inch wafers, a significant improvement from previous methods that required over a day for a single layer. The enhanced speed and uniformity of this technology make it suitable for commercial applications, where 8-inch or larger wafers are essential. The researchers focused on molybdenum disulfide, a flexible, transparent 2D material with powerful electronic and photonic properties ideal for semiconductor transistors. They designed a new furnace for the metal-organic chemical vapor deposition process, which has separate low and high-temperature regions. The silicon wafer is placed in the low-temperature region while vaporized molybdenum and sulfur precursors flow into the furnace. Molybdenum remains in the low-temperature region, while the sulfur precursor decomposes in the high-temperature region before flowing back into the low-temperature region to grow molybdenum disulfide on the wafer surface.

SK Hynix representatives unveiled the company's latest breakthrough in 3D NAND development at the ISSCC 2023 conference. Details of a new flash memory prototype featuring over 300 layers were revealed, and the company stated that a team of 35 engineers had contributed to the presentation material. In order to highlight the boost in performance offered by the prototype's improvements, it was compared to SK Hynix's previous record holding seventh-generation 238-layer 3D NAND. The new eighth-generation 3D NAND posted bandwidth figures with a maximum of 194 MB/s, which contrasts favorably with the older model's rate of 164 MB/s, representing an 18% increase in performance.

Recording density also benefits from the 300+ active layer design, with SK Hynix mentioning a 1 Tb (128 GB) capacity with triple level cells and a bit density of over 20 GB/mm^2. The chip features a 16 KB page size, four planes and a 2400 MT/s interface. The increase in density will result in a lower per-Tb cost during the manufacturing process. It is hoped that the end consumer will ultimately benefit from the boost in performance and capacity.