HP has envisioned a new approach to MicroLED monitors that could revolutionize how we design and buikd displays. Dubbed "Composable MicroLED Monitors," this concept proposes a modular system where users can assemble their desired monitor configuration from multiple components. At the core of this concept lies a base unit that serves as the foundation, housing the necessary connections and a stand. Users can then attach flat or curved extension modules to the base, allowing various display sizes and formats. These modules resemble puzzle pieces, seamlessly integrating with the base unit through magnetic holders that ensure precise alignment. The true beauty of this concept lies in its scalability and customization options. By combining multiple base units and extension modules, users can create displays of virtually any size or shape tailored to their specific needs.

Whether it's a compact, single-screen setup or an immersive, curved multi-monitor array, the possibilities are endless. HP's illustrations showcase the potential of this concept, with a proposed base unit size of 12" x 12" and extension modules measuring 12" x 6". With integrated switches or software controls, users can even specify how the operating system treats the connected display tiles - as a unified, large display or as separate, independent screens. While this concept's modular nature promises infinite flexibility, it also presents a challenge: the inevitable gaps between modules. HP's research paper delves into potential solutions to minimize these gaps, ensuring a seamless visual experience for users. Whether HP's "Composable MicroLED Monitors" concept will transition from a study to a tangible product remains to be seen. However, one thing is sure: this pioneering approach could open up a world of possibilities for display technology, enabling users to create truly personalized and tailored visual experiences.

During the recent IEDM conference, TSMC previewed its process roadmap for delivering next-generation chip packages packing over one trillion transistors by 2030. This aligns with similar long-term visions from Intel. Such enormous transistor counts will come through advanced 3D packaging of multiple chipsets. But TSMC also aims to push monolithic chip complexity higher, ultimately enabling 200 billion transistor designs on a single die. This requires steady enhancement of TSMC's planned N2, N2P, N1.4, and N1 nodes, which are slated to arrive between now and the end of the decade. While multi-chipset architectures are currently gaining favor, TSMC asserts both packaging density and raw transistor density must scale up in tandem. Some perspective on the magnitude of TSMC's goals include NVIDIA's 80 billion transistor GH100 GPU—among today's largest chips, excluding wafer-scale designs from Cerebras.

Yet TSMC's roadmap calls for more than doubling that, first with over 100 billion transistor monolithic designs, then eventually 200 billion. Of course, yields become more challenging as die sizes grow, which is where advanced packaging of smaller chiplets becomes crucial. Multi-chip module offerings like AMD's MI300X and Intel's Ponte Vecchio already integrate dozens of tiles, with PVC having 47 tiles. TSMC envisions this expansion to chip packages housing more than a trillion transistors via its CoWoS, InFO, 3D stacking, and many other technologies. While the scaling cadence has recently slowed, TSMC remains confident in achieving both packaging and process breakthroughs to meet future density demands. The foundry's continuous investment ensures progress in unlocking next-generation semiconductor capabilities. But physics ultimately dictates timelines, no matter how aggressive the roadmap.

The Meteor Lake codename has been linked to the fourteenth generation of Intel's Core lineup for a while, following several significant leaks in 2022 and 2023. According to newly unearthed internal documentation and benchmark data, Intel has confirmed that the Meteor Lake family of CPUs will form its upcoming 14th Gen Core lineup - with laptop variations expected to arrive mid-2023 and heavily speculated desktop units in the fourth quarter, although a middle of the year refresh of Raptor Lake could push the entire Meteor Lake range's release window into 2024.

Meteor Lake is anticipated to be Intel's debuting of a "disaggregated" design - the most advanced laptop CPU variant features a top-of-the-line 6P+8E core configuration. Intel is solely responsible for fabrication of an IOE (I/O) tile (the company's own term for a chiplet) with PCIe 5.0 plus Thunderbolt 4, as well as an SoC tile. The GPU part of the design is rumored to be based on their own Arc Alchemist architecture, and TSMC has been contracted to manufacture this graphics tile - not a big surprise since Intel has also placed substantial manufacturing orders for discrete Arc cards with the Taiwanese foundry.