Fujitsu has previewed its next-generation Monaka processor, a 144-core powerhouse for data center. Satoshi Matsuoka of the RIKEN Center for Computational Science showcased the mechanical sample on social media platform X. The Monaka processor is developed in collaboration with Broadcom and employs an innovative 3.5D eXtreme Dimension System-in-Package architecture featuring four 36-core chiplets manufactured using TSMC's N2 process. These chiplets are stacked face-to-face with SRAM tiles through hybrid copper bonding, utilizing TSMC's N5 process for the cache layer. A distinguishing feature of the Monaka design is its approach to memory architecture. Rather than incorporating HBM, Fujitsu has opted for pure cache dies below compute logic in combination with DDR5 DRAM compatibility, potentially leveraging advanced modules like MR-DIMM and MCR-DIMM.

The processor's I/O die supports cutting-edge interfaces, including DDR5 memory, PCIe 6.0, and CXL 3.0 for seamless integration with modern data center infrastructure. Security in the design is taken care of with the implementation of Armv9-A's Confidential Computing Architecture for enhanced workload isolation. Fujitsu has set ambitious goals for the Monaka processor. The company aims to achieve twice the energy efficiency of current x86 processors by 2027 while maintaining air cooling capabilities. The processor aims to do AI and HPC with the Arm SVE 2 support, which enables vector lengths up to 2048 bits. Scheduled for release during Fujitsu's fiscal year 2027 (April 2026 to March 2027), the Monaka processor is shaping up as a competitor to AMD's EPYC and Intel's Xeon processors.

A few days ago, we published a report about Intel's 18A yields being at an abysmal 10%. This sparked quite a lot of discussion among the tech community, as well as responses from industry analysts and Intel's now ex-CEO Pat Gelsinger. Today, we are diving into known information about Intel's 18A node and checking out what the yields of possible products could be, using tools such as Die Yield Calculator from SemiAnalysis. First, we know that the defect rate of the 18A node is 0.4 defects per cm². This information is from August, and up-to-date defect rates could be much lower, especially since semiconductor nodes tend to evolve even when they are production-ready. To measure yields, manufacturers use various yield models based on the information they have, like the aforementioned 0.4 defect density. Expressed in defects per square centimeter (def/cm²), it measures manufacturing process quality by quantifying the average number of defects present in each unit area of a semiconductor wafer.

Measuring yields is a complex task. Manufacturers design some smaller chips for mobile and some bigger chips for HPC tasks. Thus, these two would have different yields, as bigger chips require more silicon area and are more prone to defects. Smaller mobile chips occupy less silicon area, and defects occurring on the wafer often yield more usable chips than wasted silicon. Stating that a node only yields x% of usable chips is only one side of the story, as the size of the test production chip is not known. For example, NVIDIA's H100 die is measuring at 814 mm²—a size that is pushing modern manufacturing to its limits. The size of a modern photomask, the actual pattern mask used in printing the design of a chip to silicon wafer, is only 858 mm² (26x33 mm). Thus, that is the limit before exceeding the mask and needing a redesign. At that size, nodes are yielding much less usable chips than something like a 100 mm² mobile chip, where defects don't wreak havoc on the yield curve.

Ahead of its October 23 release, PC enthusiast and Twitch streamer Madness727 released some of the first pictures of a de-lidded Core Ultra "Arrow Lake-S" desktop processor. There's no word on which processor model this is, but it shouldn't matter—all models being released this month are based on the same exact configuration of tiles of the "Arrow Lake-S," which means a Compute tile with an 8P+16E core CPU complex, a Graphics tile with 4 Xe cores, and the larger version of the breakout I/O tile that features an integrated Thunderbolt 4 controller.

Intel already released information on its Core Ultra "Arrow Lake-H" mobile processor that comes out in Q1-2025, which is shown featuring a physically smaller Compute tile that has a 6P+8E core CPU complex, a larger Graphics tile with 8 Xe cores, and a smaller breakout I/O tile. You can see where this is going for some of the cheaper Core Ultra 5 and Core Ultra 3 desktop processor models that release in Q1-2025. De-lidding is the process of removing the integrated heatspreader of a desktop processor to enable direct contact between the chip below, and the cooling solution. It is preferred by professional overclockers that use extreme cooling solutions.

Intel is preparing to launch its next generation of mobile CPUs with Core Ultra 200 series "Lunar Lake" leading the charge. However, as these processors are about to hit the market, leakers reveal Intel's plans for the next-generation Core Ultra 300 series "Panther Lake". According to rumors, Panther Lake will double the core count of Lunar Lake, which capped out at eight cores. There are several configurations of Panther Lake in the making based on the different combinations of performance (P) "Cougar Cove," efficiency (E) "Skymont," and low power (LP) cores. First is the PTL-U with 4P+0E+4LP cores with four Xe3 "Celestial" GPU cores. This configuration is delivered within a 15 W envelope. Next, we have the PTL-H variant with 4P+8E+4LP cores for a total of 16 cores, with four Xe3 GPU cores, inside a 25 W package. Last but not least, Intel will also make PTL-P SKUs with 4P+8E+4LP cores, with 12 Xe3 cores, to create a potentially decent gaming chip with 25 W of power.

Intel's Panther Lake CPU architecture uses an innovative design approach, utilizing a multi-tile configuration. The processor incorporates five distinct tiles, with three playing active roles in its functionality. The central compute operations are handled by one "Die 4" tile with CPU and NPU, while "Die 1" is dedicated to platform control (PCD). Graphics processing is managed by "Die 5", leveraging Intel's Xe3 technology. Interestingly, two of the five tiles serve a primarily structural purpose. These passive elements are strategically placed to achieve a balanced, rectangular form factor for the chip. This design philosophy echoes a similar strategy employed in Intel's Lunar Lake processors. Panther Lake is poised to offer greater versatility compared to its Lunar Lake counterpart. It's expected to cater to a wider range of market segments and use cases. One notable advancement is the potential for increased memory capacity compared to Lunar Lake, which capped out at 32 GB of LPDDR5X memory running at 8533 MT/s. We can expect to hear more potentially at Intel's upcoming Innovation event in September, while general availability of Panther Lake is expected in late 2025 or early 2026.

HP has envisioned a new approach to MicroLED monitors that could revolutionize how we design and buikd displays. Dubbed "Composable MicroLED Monitors," this concept proposes a modular system where users can assemble their desired monitor configuration from multiple components. At the core of this concept lies a base unit that serves as the foundation, housing the necessary connections and a stand. Users can then attach flat or curved extension modules to the base, allowing various display sizes and formats. These modules resemble puzzle pieces, seamlessly integrating with the base unit through magnetic holders that ensure precise alignment. The true beauty of this concept lies in its scalability and customization options. By combining multiple base units and extension modules, users can create displays of virtually any size or shape tailored to their specific needs.

Whether it's a compact, single-screen setup or an immersive, curved multi-monitor array, the possibilities are endless. HP's illustrations showcase the potential of this concept, with a proposed base unit size of 12" x 12" and extension modules measuring 12" x 6". With integrated switches or software controls, users can even specify how the operating system treats the connected display tiles - as a unified, large display or as separate, independent screens. While this concept's modular nature promises infinite flexibility, it also presents a challenge: the inevitable gaps between modules. HP's research paper delves into potential solutions to minimize these gaps, ensuring a seamless visual experience for users. Whether HP's "Composable MicroLED Monitors" concept will transition from a study to a tangible product remains to be seen. However, one thing is sure: this pioneering approach could open up a world of possibilities for display technology, enabling users to create truly personalized and tailored visual experiences.

During the recent IEDM conference, TSMC previewed its process roadmap for delivering next-generation chip packages packing over one trillion transistors by 2030. This aligns with similar long-term visions from Intel. Such enormous transistor counts will come through advanced 3D packaging of multiple chipsets. But TSMC also aims to push monolithic chip complexity higher, ultimately enabling 200 billion transistor designs on a single die. This requires steady enhancement of TSMC's planned N2, N2P, N1.4, and N1 nodes, which are slated to arrive between now and the end of the decade. While multi-chipset architectures are currently gaining favor, TSMC asserts both packaging density and raw transistor density must scale up in tandem. Some perspective on the magnitude of TSMC's goals include NVIDIA's 80 billion transistor GH100 GPU—among today's largest chips, excluding wafer-scale designs from Cerebras.

Yet TSMC's roadmap calls for more than doubling that, first with over 100 billion transistor monolithic designs, then eventually 200 billion. Of course, yields become more challenging as die sizes grow, which is where advanced packaging of smaller chiplets becomes crucial. Multi-chip module offerings like AMD's MI300X and Intel's Ponte Vecchio already integrate dozens of tiles, with PVC having 47 tiles. TSMC envisions this expansion to chip packages housing more than a trillion transistors via its CoWoS, InFO, 3D stacking, and many other technologies. While the scaling cadence has recently slowed, TSMC remains confident in achieving both packaging and process breakthroughs to meet future density demands. The foundry's continuous investment ensures progress in unlocking next-generation semiconductor capabilities. But physics ultimately dictates timelines, no matter how aggressive the roadmap.

The Meteor Lake codename has been linked to the fourteenth generation of Intel's Core lineup for a while, following several significant leaks in 2022 and 2023. According to newly unearthed internal documentation and benchmark data, Intel has confirmed that the Meteor Lake family of CPUs will form its upcoming 14th Gen Core lineup - with laptop variations expected to arrive mid-2023 and heavily speculated desktop units in the fourth quarter, although a middle of the year refresh of Raptor Lake could push the entire Meteor Lake range's release window into 2024.

Meteor Lake is anticipated to be Intel's debuting of a "disaggregated" design - the most advanced laptop CPU variant features a top-of-the-line 6P+8E core configuration. Intel is solely responsible for fabrication of an IOE (I/O) tile (the company's own term for a chiplet) with PCIe 5.0 plus Thunderbolt 4, as well as an SoC tile. The GPU part of the design is rumored to be based on their own Arc Alchemist architecture, and TSMC has been contracted to manufacture this graphics tile - not a big surprise since Intel has also placed substantial manufacturing orders for discrete Arc cards with the Taiwanese foundry.