Friday, November 6th 2015
AMD Dragged to Court over Core Count on "Bulldozer"
This had to happen eventually. AMD has been dragged to court over misrepresentation of its CPU core count in its "Bulldozer" architecture. Tony Dickey, representing himself in the U.S. District Court for the Northern District of California, accused AMD of falsely advertising the core count in its latest CPUs, and contended that because of they way they're physically structured, AMD's 8-core "Bulldozer" chips really only have four cores.
The lawsuit alleges that Bulldozer processors were designed by stripping away components from two cores and combining what was left to make a single "module." In doing so, however, the cores no longer work independently. Due to this, AMD Bulldozer cannot perform eight instructions simultaneously and independently as claimed, or the way a true 8-core CPU would. Dickey is suing for damages, including statutory and punitive damages, litigation expenses, pre- and post-judgment interest, as well as other injunctive and declaratory relief as is deemed reasonable.
Source:
LegalNewsOnline
The lawsuit alleges that Bulldozer processors were designed by stripping away components from two cores and combining what was left to make a single "module." In doing so, however, the cores no longer work independently. Due to this, AMD Bulldozer cannot perform eight instructions simultaneously and independently as claimed, or the way a true 8-core CPU would. Dickey is suing for damages, including statutory and punitive damages, litigation expenses, pre- and post-judgment interest, as well as other injunctive and declaratory relief as is deemed reasonable.
511 Comments on AMD Dragged to Court over Core Count on "Bulldozer"
As I said before, no one ever said 8 CPU cores needed to be fast but, they're are more than enough components to call it a 8c CPU. Does it have shared resources that can hinder performance, sure but, even in those cases, workloads still scale linearly unlike with just about every form of SMT.
I will not exclude FPU (or any other instructions) because cores must be complete.
Silvermont is not fast even compared to an FX-8350 but it has 8 cores (yes, 8 simultaneous AVX instructions) unlike FX-8350.
Im guessing they lost the court battle?
FPU can only be reasonably separated in specialized processors (like database or network routers). In general processors (which x86 epitomizes), it should not be separated. The fact they're putting it back in Zen proves how stupid that idea was. Last action was a time extension on August 23:
"ORDER GRANTING JOINT STIPULATION TO FURTHER EXTEND TIME FOR PARTIES TO ENGAGE IN ADR PROCESS"
TL;DR: they're trying to settle. It will only go to court if they fail to settle.
Goldmont FPU is a LOT weaker than Piledriver based architecture. By a HUGE margin. Unless they decide to assemble two of their FPUs together and share, they will NEVER achieve the AVX and FMA instructions with a OoO and the TDP. The AMD A10 5750M is totally blasting out any Intel Atom in every possible benchmark.
FX-8350 = 8c/8t, until it needs to achieve an AVX or FMA, that's where the processor need to take two threads to achieve it. You simply don't understand the architecture, at all.
As you are probably under Windows, name me one software compiled to use AVX instructions. Even now, so little games are compiled to take advantage of AVX.
A non-shared L2 was standard for a very long time too. But that changed. AMD tried to change to a shared FPU. It hurt performance, but in the strictest technical term, it did not make each module 1c/2t. Each module can in fact work on two instructions at the exact same time. That is not possible with 1c/2t. Um, no. Die != package or socket.
Even if AMD made it possible to power gate an integer core, I'd still argue it isn't a core because there still isn't a discreet FPU for each. If it had two, or more FPUs and the cores could use 1 to all of them (like Core 2 Duo L2), then yeah, I could take your argument. That is not the case though: they're Siamese twins where disabling one would kill the other. The whole, therefore, is a core, not the parts. This feature is unique with Bulldozer and sons. Even SPARC can do fine without the FPU core.
You can also disable the cores individually, unlike an additional thread. Each of those cores is also a physical presence with a clockgen controlling it and can be clocked independently of the core in the same module next to it.
Mind finding me a "thread" that can do that?
You're making a technical distinction that simply doesn't exist to the public nor does AMD make that distinction clear on their packaging.
I mean, are you expecting them to make it clear these aren't ARM cores? They don't say that on the box, so why shouldn't we expect them be IA-64 cores? Is that the logic you really are going with?
www.webopedia.com/TERM/M/multi_core_technology.html Bulldozer does not represent the norm (complete processors), it represents an exception (Siamesed processors). AMD can't take a well understood word and redefine it to mean something else. If they had put "8-Integer Core" on the box, this lawsuit wouldn't have happened.
You also have frequency scaling. I can scale each core clock speed independently.
I will even leave the linfo so you see the machine running in real time. If those were only one core per module without being independent, i wouldn't be able to change their clock frequency individually for all 6 cores.
malakilab.org/linfo/