The only time two threads within a Bulldozer Module could clash...

FordGT90ConceptCompare two of Intel's "cores" to two of AMD's "cores"...

...is an impossibility in the former. Hyper-Threading Technology does not add "cores." The comparison is therefore invalid.

AMD should have called:
-core -> integer cluster
-module -> core
...lawsuit never would have happened because the description matches the product.

AquinusThe argument falls apart when you consider what would happen if AMD had doubled the width of the single FPU (not add a second one,) per module and it's impact it would have had on floating point performance and I'm willing to bet that you would instantly make up the difference but, that still doesn't fix the integer cores which is where a lot of performance is lost. Once again, the class action makes it sound like bulldozer sucks because it has a shared FPU when it's really because it has gimped FPUs. Sharing it was smart, slimming it out was not. A similarly clocked Intel quad core will have double the floating point performance than an "8 core" BD chip at the same clock. It also happens to be the case (as I said before,) that the FPU per module is half of the width of the FPU on K12 and SB through at least Haswell. If BD had FPUs that were twice as wide, it would still be shared but, if you consider the clocks that BD runs at, you make up some of that difference and floating point performance would line up more with a 6c Intel CPU if that were the case instead of somewhere between a dual-core and quad-core Intel chip at the same clock.

Simply put, you could still have a FPU on every core but, if they make the FPU half as wide than it is now per every module, you're still stuck with the same crappy performance because your ability to dispatch hasn't been improved. When using any streaming SIMD task with floating point data, the wider FPU at any given clock speed will always be faster than a narrower one because half the width means twice as many cycles to do the same thing and fewer cycles to complete a task means better IPC. So despite having twice as many FPUs, the reduced width of each unit harms overall throughput.

tl;dr: Increasing the width of the already shared FPU by double would have the same performance characteristics as doubling the number of FPUs with the current width which is reason alone to reject the "it's not 8 cores," claim based strictly on the FPU itself. Simply put, caveat emptor.

FordGT90ConceptAnd "you're not addressing the real problem" of AMD overstating the capabilities of their processors.

AquinusSimply put, you could still have a FPU on every core but, if they make the FPU half as wide than it is now per every module, you're still stuck with the same crappy performance because your ability to dispatch hasn't been improved.

eidairaman1No point of beating a dead horse. The cpus have 8 physical cores in 4 modules, they share resources between 2 cores, not much different than any cpu sharing the cache.

eidairaman1No point of beating a dead horse. The cpus have 8 physical cores in 4 modules, they share resources between 2 cores, not much different than any cpu sharing the cache.

Aquinus...and people don't seem to get that the problem is that the width of the FPU is 100% responsible for the poor performance, not the fact that there is only one of them. Bulldozer and Haswell both have the same number of FPUs and on a purely floating point benchmark, Haswell will be twice as fast because the width of the FPU is twice as big. So at any given clock speed, you'll see half the performance. Half the width, half the performance. That's not too hard to understand.

FordGT90Concept...evidence that AMD cheated consumers...

FordGT90ConceptCompare two of Intel's "cores" to two of AMD's "cores"...

...is an impossibility in the former. Hyper-Threading Technology does not add "cores." The comparison is therefore invalid.

AMD should have called:
-core -> integer cluster
-module -> core
...lawsuit never would have happened because the description matches the product.

cdawallSeriously your argument is AMD used an undefined word differently. A module isn't a core, the only thing you can argue is the lack of an FPU per core, but guess what it's still a core at that point.

cdawallIt's so defined you yourself had to find basically an urban dictionary of computers to do so.

FordGT90ConceptDoes the equivalent literature exist to say otherwise?

Now, it’s absolutely true that the Bulldozer family of products has had much lower single-thread performance than either previous AMD CPUs (in many cases) or Intel chips (in virtually all cases). But this lawsuit doesn’t appear to argue that AMD mismarketed its CPUs because single-threaded performance was weaker than expected, but because multi-threaded scaling was critically harmed by the decision to share various aspects of the underlying architecture. Weak single-threaded performance and high power consumption created a situation in which BD could neither hit its target clock frequencies nor its IPC targets. Critically, these issues do not disappear when the CPU is run in one-thread per module mode.

Dickey’s lawsuit is wrong on other areas of fact as well. Bulldozer does share a single FPU block per work unit, but consumer workloads are rarely FPU-heavy. Each CPU module does contain the eight integer pipelines you’d expect in a typical dual-core conventional chip (4 ALU + 4 AGU per module). Dickey refers to Bulldozer as being unable to “perform eight calculations simultaneously,” but this is imprecise, inexact language that does not reflect the complexity of how a CPU executes code. Bulldozer is absolutely capable of executing eight threads simultaneously, and executing eight threads on an eight-core FX-8150 is faster than running that same chip in a four-thread, four-module mode. Bulldozer can decode 16 instructions per clock (not eight) and it can keep far more than eight instructions in flight simultaneously.

This lawsuit essentially asks a court to define what a core is and how companies should count them. As annoying as it is to see vendors occasionally abuse core counts in the name of dubious marketing strategies, asking a courtroom to make declarations about relative performance between companies is a cure far worse than the disease. From big iron enterprise markets to mobile devices, companies deploy vastly different architectures to solve different types of problems. An eight-core, Cortex-A7-based, mobile SoC is a very different beast from an eight-core big.Little Cortex-A57 / Cortex-A53 configuration. That chip is very different from an Oracle M7 or the SPARC T5. The T5 doesn’t pack the per-core performance of Intel’s 18-core Xeons, or IBM’s Power8.

Prima.VeraOK, one simple question and I'm gone. If AMD has indeed 8 cores, can you or can you not clock each individual core with a different frequency?

cdawallYou can each core is independent for clocks

BiggieShadySo the equivalent literature doesn't say otherwise which makes urban dictionary the best source for the definition which makes the term well defined.
Not getting your logic.

FordGT90ConceptWhen an entire industry does something the same across a wide variety of hardware

AquinusCan you really control the multiplier on each integer core independently of the other core in the module in the BIOS? If true, I would actually find that really interesting.

FordGT90ConceptThere's a plethora of samples that have everything packed into one unit collectively called a "core." When an entire industry does something the same across a wide variety of hardware, it becomes the definition of what that something is. Case in point: Oxford English Dictionary now recognizes the words [URL='http://www.cnn.com/2016/09/12/health/oxford-new-words-trnd/index.html']'Merica and YOLO[/URL]. The definition of "core" was established with K8 X2, K10, Conroe, Penryn, Nehalem, Westmere, and Sandy Bridge (I'm leaving a lot out) before AMD redefined it with Bulldozer in late 2011. Its launch goes against the five years of established precedent. None of those processors shared anything required to process any type of data.