BiggieShadyOf course, best you can do is port long running thread job part of your app to c or c++, build win32 DLL using MinGW with gcc 4.7 and bulldozer compile flags, then use [DllImport] in your .net wpf app :laugh: and I wouldn't want that to anyone.

Also WinForms is not WPF.

Coincidentally, as I felt like I have seen this before I managed to find an almost year old similar case www.leagle.com/decision/In FDCO 20160408M22/DICKEY v. ADVANCED MICRO DEVICES, INC.
and it was dismissed:

california courtC. Fraud-Based Claims
Assuming that California law applies to plaintiff's claims, defendant argues that plaintiff's CLRA, UCL, FAL, fraudulent inducement, and negligent misrepresentation causes of action must be dismissed due to plaintiff's failure to plead key elements of fraud. Dkt. No. 27 at 13. The Ninth Circuit has held that "where a complaint includes allegations of fraud, Federal Rule of Civil Procedure 9(b) requires more specificity including an account of the time, place, and specific content of the false representations as well as the identities of the parties to the misrepresentations." Swartz v. KPMG LLP, 476 F.3d 756, 764 (9th Cir. 2007) (citation omitted). Plaintiff's claims sound in fraud, and are thus subject to Rule 9(b)'s pleading requirements. See Pirozzi v. Apple Inc., 913 F.Supp.2d 840, 850 (N.D. Cal. 2012) ("Plaintiff's claims under the UCL, FAL, CLRA, and for Negligent Misrepresentation . . . sound in fraud, and are subject to the heightened pleading requirements of Rule 9(b).") (citing Kearns v. Ford Motor Co., 567 F.3d 1120, 1127 (9th Cir. 2009)).

"n order to be deceived, members of the public must have had an expectation or an assumption about the matter in question." Daugherty v. Am. Honda Motor Co., 144 Cal.App.4th 824, 838 (2006) (citation omitted). Under California law, "a class representative proceeding on a claim of misrepresentation as the basis of his or her UCL action must demonstrate actual reliance on the allegedly deceptive or misleading statements, in accordance with well-settled principles regarding the element of reliance in ordinary fraud actions." In re Tobacco II Cases, 46 Cal.4th 298, 306 (2009)

Plaintiff's complaint cites non-technical AMD written materials to support plaintiff's argument that AMD made misleading statements on what constitutes a "core." For example, plaintiff alleges that in an investor filing, AMD stated:

. . . semiconductor companies are designing and developing multi-core [CPUs], where multiple processor cores are placed on a single die or in a single processor. Multi-core [CPUs] offer enhanced overall system performance and efficiency because computing tasks can be spread across two or more processing cores, each of which can execute a task [i.e., a calculation] at full speed.
Compl. ¶ 19 (citing a 2014 AMD form 10-K, Compl. Ex. A). The complaint also alleges that in 2010, AMD stated that its CPUs are offered "[w]ith the power of four processor cores on a single chip, [and] deliver[] industry-leading multitasking performance."3 By contrast, plaintiff alleges, at least one AMD technical presentation acknowledges that AMD's modules have "additional sharing" when compared to existing cores and that "modules," rather than the module processing units that make up modules, have "everything necessary to schedule a code on these processors." Id. ¶ 36 (citing AMD, "Bulldozer" Processor Topology, May 28, 2013, www.youtube.com/watch?v=4EAuVsXWQ0s). The complaint also cites technical publications by third parties that allegedly distinguish between AMD's module processing units and cores. For example, a page on the Tom's Hardware Guide website stated that "the Bulldozer module doesn't incorporate two complete cores."4

Defendant argues that plaintiff fails to plead specific facts to show the basis for his expectations about "cores." Dkt. No. 27 at 13. First, defendant argues that plaintiff does not allege that he personally saw or relied on any statements by AMD indicating that a core is an independent processing unit without any shared resources. Id. at 5. Nor does plaintiff allege that he personally believed that the cores on Bulldozer chips would not share resources when he bought them. Id. Plaintiff responds by arguing that the complaint specifically alleges that plaintiff saw AMD's advertising about the number of cores in its Bulldozer chips and that he relied on that advertising in making his purchase. Dkt. No. 30 at 21-22 (citing Compl. ¶¶ 42-46). The problem with plaintiff's argument is that while plaintiff alleges that he relied on AMD's representations about the number of cores on a chip, the complaint does not allege that plaintiff believed that a core could not share resources or that plaintiff even had a particular understanding of whatconstitutes a "core." Accordingly, the court finds that plaintiff's allegations regarding reliance are insufficient to state a claim for fraud.

Second, defendant argues, none of the statements by AMD that plaintiff cites asserts that a "core" must be an "independent processing unit" without any shared resources. Dkt. No. 27 at 5. Defendant points out that one of the industry articles cited in the complaint actually suggests that AMD's use of the term "core" was appropriate. See Compl. ¶ 34 n. 23 (citing www.tomshardware.com/reviews/fx-8150-zambezi-bulldozer-990fx,3043-3.html) ("To best accommodate its Bulldozer module, the company is saying that anything with its own integer execution pipelines qualifies as a core (no surprise there, right?), if only because most processor workloads emphasize integer math. I don't personally have any problem with that definition."). The court agrees with defendant that the alleged statements by AMD cited in the complaint do not suggest that AMD told consumers that a core had to be completely independent from other cores and could not share any resources. While an alleged statement by AMD's competitor Intel cited in the complaint refers to "independent central processing units in a single computing environment," the complaint does not describe any statements by AMD that suggest complete independence of cores. See Compl. ¶¶ 19-21.

and this section is why it will just get dismissed again.

BiggieShadyCoincidentally, as I felt like I have seen this before I managed to find an almost year old similar case www.leagle.com/decision/In FDCO 20160408M22/DICKEY v. ADVANCED MICRO DEVICES, INC.
and it was dismissed:

That's the same case but it appears that Dickey is in Alabama but the lawsuit was in California. As a result of that, amendments had to be made to the claim and refile the suit. Here's the whole quote:

For the foregoing reasons, the court GRANTS defendant's motion to dismiss with leave to amend. Within 14 days, plaintiff shall submit an amended complaint that corrects the deficiencies identified in this order. Furthermore, a case management conference will be held on May 13, 2016 at 10:30 a.m. The parties shall submit a joint case management statement by May 6, 2013.

That's why it is on-going.


Dickey et. al. needs to expand on this:

The court agrees with defendant that the alleged statements by AMD cited in the complaint do not suggest that AMD told consumers that a core had to be completely independent from other cores and could not share any resources.

I'd argue that the word "core" explicitly means independence to the public. To say otherwise, is to let AMD define the word in a way that is inconsistent with competitor offerings and even their own previous offerings.

FordGT90ConceptI'd argue that the word "core" explicitly means independence to the public. To say otherwise, is to let AMD define the word in a way that is inconsistent with competitor offerings and even their own previous offerings.

L1, L2, L3, L4/edram would all be shared resources.

L1 usually isn't shared. L2 can belong to a single core but sometimes not. L3 and L4 are never claimed by a single core at this point.

It's pretty easy to tell what is shared and what isn't by comparing number of pools of L2 and up with number of cores in the system. It should be 1:1. Bulldozer split the L1 data cache from what should be 32-64 KB to two 16 KB caches.

Ha, so it's the same Dicky winning the case by citing Tom's Hardware :laugh:
it was funny until I remembered the same company now owns AnandTech ... now it's just sad

FordGT90ConceptL1 usually isn't shared. L2 can belong to a single core but sometimes not. L3 and L4 are never claimed by a single core at this point.

It's pretty easy to tell what is shared and what isn't by comparing number of pools of L2 and up with number of cores in the system. It should be 1:1. Bulldozer split the L1 data cache from what should be 32-64 KB to two 16 KB caches.

Read what you quoted.

The court agrees with defendant that the alleged statements by AMD cited in the complaint do not suggest that AMD told consumers that a core had to be completely independent from other cores and could not share any resources.

ANY resources, I know what the argument is aimed at (shared FPU), but a resource is a resource can't nitpick.

Bulldozer shares:
-L1 instruction
-Instruction Fetch
-Branch Predicition
-Predecode/Pick
-Instruction decoder
-Dispatch
-FPU
-Write Coalescing Cache
-Core Interface Unit



If you plucked the integer cluster out of the module and tried to use it by itself, you'd find it capable of little more than running a calculator. It needs that shared instruction decoder or it is completely worthless in an x86 system.

As far as I know all of that can handle more than one instruction at a time...so what difference does it make if they are shared that part of the performance wouldn't change. The integer cores themselves are the weak point not the ability to force instructions down them.

Because nothing is shared in a core. A core is incomplete if it can't go from instruction all of the way to result. If an instruction decoder malfunctions, you lose 25% of your processor, not 12.5%.

FordGT90ConceptBecause nothing is shared in a core. A core is incomplete if it can't go from instruction all of the way to result. If an instruction decoder malfunctions, you lose 25% of your processor, not 12.5%.

According to whom?

Everything that is not a Bulldozer. Even UltraSPARC T1 went instruction to result without leaving the core (page 16):
www.oracle.com/technetwork/systems/opensparc/t1-08-ust1-uasuppl-draft-p-ext-1537736.html
Floating-point work went to the "external interface" to reach the FPU.

cdawallAccording to whom?

I think we know where this is going.

The problem with plaintiff's argument is that while plaintiff alleges that he relied on AMD's representations about the number of cores on a chip, the complaint does not allege that plaintiff believed that a core could not share resources or that plaintiff even had a particular understanding of whatconstitutes a "core." Accordingly, the court finds that plaintiff's allegations regarding reliance are insufficient to state a claim for fraud.

In other words, Dickey didn't know what the heck he was talking about and AMD's usage of terminology was valid as there is no precedent for assuming that a core is purely independent without any shared resources, nor did AMD claim that the core doesn't have shared resources.

FordGT90ConceptThis is all very irrelevant anyway because a core is a core, not an integer cluster. AMD, at best, is going to settle which means they don't admit guilt to misleading the public. At worse, it will go to court, AMD will lose, and they'll likely have to pay out hundreds of millions or billions for making consumers think they got twice what they got.

Remember when you said that? The court actually said practically the opposite.

Second, defendant argues, none of the statements by AMD that plaintiff cites asserts that a "core" must be an "independent processing unit" without any shared resources. Dkt. No. 27 at 5. Defendant points out that one of the industry articles cited in the complaint actually suggests that AMD's use of the term "core" was appropriate. See Compl. ¶ 34 n. 23 (citing www.tomshardware.com/reviews/fx-8150-zambezi-bulldozer-990fx,3043-3.html) ("To best accommodate its Bulldozer module, the company is saying that anything with its own integer execution pipelines qualifies as a core (no surprise there, right?), if only because most processor workloads emphasize integer math. I don't personally have any problem with that definition."). The court agrees with defendant that the alleged statements by AMD cited in the complaint do not suggest that AMD told consumers that a core had to be completely independent from other cores and could not share any resources. While an alleged statement by AMD's competitor Intel cited in the complaint refers to "independent central processing units in a single computing environment," the complaint does not describe any statements by AMD that suggest complete independence of cores.See Compl. ¶¶ 19-21.

Yeah, so you want to say this again?

FordGT90ConceptBecause nothing is shared in a core.

Sorry Ford, your hardline stance on what constitutes a core doesn't seem to hold up, just as Dickey's didn't, not that I expect this to change your mind.

In other words, what constitutes a core depends on the hardware, its architecture, and any claims made by the company. No surprise there to be honest.

Defendant moves to dismiss on several grounds. Defendant argues that (1) Alabama law, not California law, governs plaintiff's claims, and so the UCL, FAL, and CRLA claims should be dismissed; (2) even under California law, plaintiff fails to state a claim for fraud; (3) the breach of warranty allegations fail to state a claim; and (4) plaintiff's unjust enrichment allegations fail to state a claim. Dkt. No. 27 at 2-3. The court addresses each of these arguments below.

It was dismissed for:
1, 3, 4) legalese
2) plaintiff should have gotten IBM, Intel, ARM, and Sun to testify instead of relying on Tom's Hardware
Which leads to this:

For the foregoing reasons, the court GRANTS defendant's motion to dismiss with leave to amend. Within 14 days, plaintiff shall submit an amended complaint that corrects the deficiencies identified in this order.

Which is why the case is still open:
www.pacermonitor.com/public/case/9674725/Dickey_v_Advanced_Micro_Devices,_Inc


Dickey did a terrible job at making his case:

Defendant argues that plaintiff fails to plead specific facts to show the basis for his expectations about "cores." Dkt. No. 27 at 13. First, defendant argues that plaintiff does not allege that he personally saw or relied on any statements by AMD indicating that a core is an independent processing unit without any shared resources. Id. at 5. Nor does plaintiff allege that he personally believed that the cores on Bulldozer chips would not share resources when he bought them. Id. Plaintiff responds by arguing that the complaint specifically alleges that plaintiff saw AMD's advertising about the number of cores in its Bulldozer chips and that he relied on that advertising in making his purchase. Dkt. No. 30 at 21-22 (citing Compl. ¶¶ 42-46). The problem with plaintiff's argument is that while plaintiff alleges that he relied on AMD's representations about the number of cores on a chip, the complaint does not allege that plaintiff believed that a core could not share resources or that plaintiff even had a particular understanding of what constitutes a "core." Accordingly, the court finds that plaintiff's allegations regarding reliance are insufficient to state a claim for fraud.

Dickey clearly didn't do his homework before filing suit.


Edit: I'm not certain he can win his case because of that testimony. He had to go into the purchase "believing the would not share resources." The logical conclusion is that he realized the performance was poor, did some searching on the internet, found the Tom's Hardware article, and sued without really thinking about it nor consulting experts on how to make the strongest case against AMD. It doesn't prove AMD right, it proves Dickey didn't make his case.

FordGT90ConceptEdit: I'm not certain he can win his case because of that testimony. He had to go into the purchase "believing the would not share resources." The logical conclusion is that he realized the performance was poor, did some searching on the internet, found the Tom's Hardware article, and sued without really thinking about it nor consulting experts on how to make the strongest case against AMD. It doesn't prove AMD right, it proves Dickey didn't make his case.

Actually winning a court case that says it is an 8 core CPU would mean they were correct. That's kinda how this works.

Dismissing isn't winning unless the plaintiff gives up (Dickey has not) or the judge closes the door to trying again (which was not). The fact AMD and Dickey are trying to settle now suggests that AMD thinks there is a case to be made and they want to stop it. AMD wants this behind them for Zen's launch.

FordGT90ConceptBecause nothing is shared in a core.

... it's shared in the module not in the core, each core owns shared module resources either all of them half of the time (front end) or half of them all the time (FPU) ... regarding definition of what core is, why would we suddenly start making fixed definitions in rapidly changing tech fields?

As I said, the "integer clusters" are useless without using hardware at "module" level; ergo, the "module" represents the "core."

Because all processors require decoders, prefetcher, ALUs, AGUs, and in most cases, FPUs, to qualify as a general processor. If we start defining processors by integer clusters, there's going to be a race to cram as many integer clusters as they can into a processor--all of the blocking components be damned. This is not a good path to travel down for consumers. This is why Xeon Phi never made it to consumers. Dumbed down cores aren't very useful to the public.

FordGT90ConceptAs I said, the "integer clusters" are useless without using hardware at "module" level; ergo, the "module" represents the "core."

Because all processors require decoders, prefetcher, ALUs, AGUs, and in most cases, FPUs, to qualify as a general processor. If we start defining processors by integer clusters, there's going to be a race to cram as many integer clusters as they can into a processor--all of the blocking components be damned. This is not a good path to travel down for consumers. This is why Xeon Phi never made it to consumers. Dumbed down cores aren't very useful to the public.

Bulldozer was designed to be in HPC clusters, not sit in consumer hands. AMD foolishly released them for consumers because well they have to have a consumer level CPU.

FordGT90ConceptDickey clearly didn't do his homework before filing suit.

That first one that's highlighted was him admitting that he knew that there were shared resources before he bought it which makes fraud a hard nut to crack because AMD most definitely disclosed that bulldozer was going to have shared resources. It doesn't really matter if you consider it a core or not, he knew what he was buying regardless of what your definition of a core is. He didn't just not do his homework, he doesn't seem to understand that fraud requires being deceived and being deceived doesn't mean being ignorant about what you're reading.

FordGT90ConceptBecause all processors require decoders, prefetcher, ALUs, AGUs, and in most cases, FPUs, to qualify as a general processor.

Sure, but, invoking the unwritten rule that all of those things must be dedicated hardware to constitute a core is still the primary problem.

FordGT90ConceptThis is why Xeon Phi never made it to consumers. Dumbed down cores aren't very useful to the public.

The Xeon Phi never made it to the consumer because it's like GPGPU. Consumers don't really care about machine learning or HPC applications. To think consumers would have benefited from having a Xeon Phi in their system (a co-processor mind you,) is a pretty big stretch.

BiggieShadyregarding definition of what core is, why would we suddenly start making fixed definitions in rapidly changing tech fields?

We wouldn't? I think this is really all just to help Ford sleep at night. Simply put, Ford was pretty insistent that not only Dickey was going to win but, that it would be a crushing defeat for AMD when it wasn't since even the first page of this now 19 page thread. I suspect that isn't the only thing Ford is wrong about regardless of whether we wants to admit that to himself or not and I think the hardliner attitude only makes it that much more apparent. Honestly, people who actually work in the field and are good at it understand that you can't think this way. As a developer, it doesn't really matter about the specifics about the core. If I can expect core-like performance characteristics as opposed to SMT-like characteristics, then I consider it a core. If BD was like hyper-threading in the sense that speed up is 0-40%, I would agree with Ford but, it's not. There is almost always speed up and it's more often than not, more than 50% which is better speed up versus what Intel's SMT implementation is capable of on a good day.

FordGT90ConceptDismissing isn't winning unless the plaintiff gives up (Dickey has not) or the judge closes the door to trying again (which was not). The fact AMD and Dickey are trying to settle now suggests that AMD thinks there is a case to be made and they want to stop it. AMD wants this behind them for Zen's launch.

It was dismissed because the court agreed with AMD that Dickey's argument wasn't strong enough (to put it lightly.) Heck, they even used his own resources against him. That does not mean that they're trying to settle, it means that it's at a standstill until Dickey makes a better case. AMD isn't going to settle if Dickey can't made a half decent argument where the court is willing to dismiss on AMD's request. Until Dickey actually tries to force the issue (and I would love him to try,) it might not be a win for AMD, but it's most definitely not a loss considering there has been practically no press on this as of late. Probably for very good reason (it's a dead end.)

Don't forget that the lawsuit isn't if AMD has 8 fully independent cores or not (which the court as seemed to have accepted that they are independent enough to call them cores using Dickey's own resources,) but, rather if AMD misled the public with regards to how the CPU operates. Simply put, core or not, AMD stated from the get-go that it would have shared components well before it was even released. That alone is enough to throw away half of the case.

AquinusSure, but, invoking the unwritten rule that all of those things must be dedicated hardware to constitute a core is still the primary problem.

Courts work on precedent and certainly you can't deny the precedent is there.

AquinusThe Xeon Phi never made it to the consumer because it's like GPGPU. Consumers don't really care about machine learning or HPC applications. To think consumers would have benefited from having a Xeon Phi in their system (a co-processor mind you,) is a pretty big stretch.

They could only sell it to consumers if it could run DirectX 9 on it and it be competitive with NVIDIA and AMD offerings. Intel abandoned that project and abandoned the idea of bringing it to consumers with it. Had Intel succeeded, it would have performed competently at GPU and CPU tasks.

AquinusSimply put, Ford was pretty insistent that not only Dickey was going to win but, that it would be a crushing defeat for AMD when it wasn't since even the first page of this now 19 page thread.

He still could.

AquinusIf I can expect core-like performance characteristics as opposed to SMT-like characteristics, then I consider it a core.

You're forgetting I'm a programmer too and probably 25-50% of my programs utilize async-multithreading. I was actually surprised to see HTT boosted Random Password Generator about 30% boost per core.

AquinusIf BD was like hyper-threading in the sense that speed up is 0-40%, I would agree with Ford but, it's not.

Where my understanding of a core is that it represents a 100% clone of hardware which translates to 80-100% performance increase per core versus a single thread. My testing shows this in threads 1-4. It's threads 5-8 where HTT and Bulldozer's design exposes itself. I'm eagerly awaiting that data to compare because I suspect know Bulldozer will not show 80-100% in 5-8 like it does in 1-4. It represents proof they aren't cores but SMT inside a core.

AquinusThere is almost always speed up and it's more often than not, more than 50% which is better speed up versus what Intel's SMT implementation is capable of on a good day.

There's nothing wrong about that. What is wrong is calling it a "core" when it isn't.

AquinusThat does not mean that they're trying to settle, it means that it's at a standstill until Dickey makes a better case.

Negative, the latest court documents says they are pursuing alternative dispute resolution which means they are trying to reach an agreement (settle) before it ends up back in court.

Aquinus...but it's most definitely not a loss considering there has been practically no press on this as of late.

There's only press coverage of these things when they start and when they end--not in between.

FordGT90ConceptL3 and L4 are never claimed by a single core at this point.

On intel chips each core has its own L3 cache. But each core can also access another core's L3 cache if the data it needs is stored there instead of accessing the RAM but it has increased latency to do so compared to its own L3 cache. A bi-directional ring bus connects the cores and their caches together. The cores are clearly independent even including the "shared" last level cache.

FordGT90ConceptThere's nothing wrong about that. What is wrong is calling it a "core" when it isn't.

This is where AMD failed. If Bulldozer was marketed as a 4c/8t chip it may not have been such a bust; because without a doubt its performance running 5-8 threads is much better compared to a hyperthreaded 4c/8t intel chip under most workloads. Yet calling it an 8 core chip set the bar higher and threads 5-8 couldnt reach that mark.

I wonder what the settlement will be, $25 off of next year's Zen chips? In the end, only the lawyers will come out with any real money in this suit.

FR@NKOn intel chips each core has its own L3 cache. But each core can also access another core's L3 cache if the data it needs is stored there instead of accessing the RAM but it has increased latency to do so compared to its own L3 cache. A bi-directional ring bus connects the cores and their caches together. The cores are clearly independent even including the "shared" last level cache.

That's kind of my point: memory has to be shared at some point because they can't coexist without it. That said, never knew Xeon had such a crazy internal bus like that.

FR@NKThis is where AMD failed. If Bulldozer was marketed as a 4c/8t chip it may not have been such a bust; because without a doubt its performance running 5-8 threads is much better compared to a hyperthreaded 4c/8t intel chip under most workloads. Yet calling it an 8 core chip set the bar higher and threads 5-8 couldnt reach that mark.

Exactly! They shot themselves in the foot.

AquinusWe wouldn't? I think this is really all just to help Ford sleep at night. Simply put, Ford was pretty insistent that not only Dickey was going to win but, that it would be a crushing defeat for AMD when it wasn't since even the first page of this now 19 page thread. I suspect that isn't the only thing Ford is wrong about regardless of whether we wants to admit that to himself or not and I think the hardliner attitude only makes it that much more apparent. Honestly, people who actually work in the field and are good at it understand that you can't think this way. As a developer, it doesn't really matter about the specifics about the core. If I can expect core-like performance characteristics as opposed to SMT-like characteristics, then I consider it a core. If BD was like hyper-threading in the sense that speed up is 0-40%, I would agree with Ford but, it's not. There is almost always speed up and it's more often than not, more than 50% which is better speed up versus what Intel's SMT implementation is capable of on a good day.

Well, AMD has been pretty outspoken about Bulldozer design coming from this IEEE scientific paper: www.microarch.org/micro37/papers/18_Kumar-Conjoined-Core.pdf

Abstract:

This paper proposes conjoined-core chip multiprocessing – topologically feasible resource sharing between adjacent cores of a chip multiprocessor to reduce die area with minimal impact on performance and hence improving the overall computational efficiency.

Figure 2 in the paper looks almost exactly like a BD module.

So, @FordGT90Concept, this type of core has a scientific name, it's a conjoined core ... keyword here is core.

AMD gave us branch misprediction penalty of a Northwood, L1D cache of a Prescott and conjoined cores from an IEEE paper ... last one being the least offensive ... too bad they can't be punished for the first two instead

I was calling it "hybrid," "conjoined" works too. Anyway you shake, AMD still omitted a key word in "8-core" they advertised it as. I'd be okay with "8-conjoined core" or "8-integer core." They need to make it clear to the public it is different.

Not sharing the L1D cache is bewildering. Even in that IEEE paper, they show a 64KiB shared L1D cache. If they were going to keep it separate, they should have had at least 32 KiB in each.


Edit: The paper says there is a performance cost:

We show that, given a set of novel optimizations that reduce the negative impacts of this sharing, we can reduce area requirements by more than 50%, while achieving performance within 9-12% of conventional cores without conjoining. Alternatively, by only sharing floating point units and crossbar ports, core area can be reduced by more than 23% while achieving performance within 2% of conventional cores without conjoining.

I think that's something the public has the right to know because that is significant.

Yea lets add words because that makes consumers happy. I like how you keep calling them cores however.