Monday, December 18th 2006
B-2 to L-2 Stepping For 2MB Conroes
- New S-Spec and MM numbers for the converting products
- CPUID will change from 6F6 to 6F2
- Extended HALT power specification will reduce from 22 Watts to 12 Watts
- Die size optimized for manufacturability
- Minor visible difference between the B-2 and L-2 packages; see below for a visual comparison
- L-2 package is pin compatible with B-2 package
14 Comments on B-2 to L-2 Stepping For 2MB Conroes
Also I think it will be cheaper to manufacture since the cache was finally cut.
wheee~
"As AMD is stepping in 65nm process soon, its cost efficiency is the biggest advantage for the company to against Intel. As 4MB L2 Cache shared almost 60% of the transistors in Conroe, a cut to native 2MB L2 Cache may help in lower 20% of the cost. In fact, the L2 stepping samples have been sent to mainboard manufacturers in order to update the microcode for BIOS."
www.hkepc.com/bbs/news.php?tid=686996&starttime=0&endtime=0
Means, 2 of 4MB cache disables. So basically the same chip with different multiplier and only 2MB cache enabled.
Those with 'native 2MB cache' will be the first _true_ Allendales.
A revision could provide much more effective use of what power it DOES have, potentially giving great strides to overclocking..
But then, there could also be things hindering overclocking- the changes in resistors, etc. Could be corner cutting. Could just be a Low power, low clock yield, too. Similar to winchesters. Didn't clock for crap, but ran like an ice cube.
ALthough if this is only for the super low end 6300/6400, I'd put my bets on lowered overclocking.