Tuesday, August 23rd 2016
AMD ZEN Quad-Core Subunit Named CPU-Complex (CCX)
We've been chasing AMD Zen for a long time now. Our older report from April 2015 uncovered an important detail about component organization on Zen processors - the clumping of four CPU cores into a highly-specialized, possibly indivisible subunit referred to then, as the "Zen Quad-core Unit." Some of the latest presentations about the architecture, following AMD's "performance reveal" event from earlier this month, shed more light on this quad-core unit.
AMD is referring to the Zen quad-core unit as the CPU-Complex (CCX). Each CCX is a combination of four independent CPU cores. Unlike on "Bulldozer," a "Zen" core does not share any of its number-crunching machinery with neighboring cores. Each "Zen" core has a dedicated L2 cache of 512 KB, and four Zen cores share an 8 MB L3 cache. AMD will control core-counts by controlling CCX units. A "Summit Ridge" socket AM4 processor features two CCX units (making up eight cores in all), sharing a dual-channel DDR4 memory controller, and the platform core-logic (chipset), complete with an integrated PCI-Express root complex. Socket AM4 APUs will feature one CCX unit, and an integrated GPU in place of the second CCX. With this, AMD is able to bring the two diverse desktop platforms under one socket.
Source:
Heise.de
AMD is referring to the Zen quad-core unit as the CPU-Complex (CCX). Each CCX is a combination of four independent CPU cores. Unlike on "Bulldozer," a "Zen" core does not share any of its number-crunching machinery with neighboring cores. Each "Zen" core has a dedicated L2 cache of 512 KB, and four Zen cores share an 8 MB L3 cache. AMD will control core-counts by controlling CCX units. A "Summit Ridge" socket AM4 processor features two CCX units (making up eight cores in all), sharing a dual-channel DDR4 memory controller, and the platform core-logic (chipset), complete with an integrated PCI-Express root complex. Socket AM4 APUs will feature one CCX unit, and an integrated GPU in place of the second CCX. With this, AMD is able to bring the two diverse desktop platforms under one socket.
44 Comments on AMD ZEN Quad-Core Subunit Named CPU-Complex (CCX)
The new Zen sounds interesting enough, I hope for the most part we do get base model quads since at this day and age dual cores are just to little (Least in my opinion).
I have stuff that only needs one core that needs love.
Each CCX can access the other L3, but it's over a slower bus, of course. The bandwith/latency hit....who knows how much.
I don't buy into the notion that a mobile i7 is the source of your problems, even considering the existence of ULV parts. If a i7-4510U can handle it all with the help of an Intel SSD 530 without chewing through the battery and burning up, so can just about everything else with a -M suffix.
Back on topic: the CCX looks promising for Zen. The whole issue about having to split it up to create APU parts or core counts that aren't multiples of 2 don't seem to be much of a problem; I recall reading about the E5 v4s when they came out and some SKUs looked a little bit irregular and more asymmetric than usual due to the newly increased core counts.
"The L3 cache is actually a victim cache, taking data from L1 and L2 evictions rather than collecting data from prefetch/demand instructions. Victim caches tend to be less effective than inclusive caches, however Zen counters this by having a sufficiency large L2 to compensate. The use of a victim cache means that it does not have to hold L2 data inside, effectively increasing its potential capacity with less data redundancy.
It is worth noting that a single CCX has 8 MB of cache, and as a result the 8-core Zen being displayed by AMD at the current events involves two CPU Complexes. This affords a total of 16 MB of L3 cache, albeit in two distinct parts. This means that the true LLC for the entire chip is actually DRAM, although AMD states that the two CCXes can communicate with each other through the custom fabric which connects both the complexes, the memory controller, the IO, the PCIe lanes etc."
So... yeah, it doesn't look good.
Note: LLC means Last Level Cache.